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[CIR] Implement logical not for VectorType #160762

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Merged
merged 4 commits into from
Sep 27, 2025
Merged

[CIR] Implement logical not for VectorType #160762

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c5a0b25
[CIR] Implement logical not for VectorType
AmrDeveloper Sep 25, 2025
6a2a7fa
Add test case for vector of floats
AmrDeveloper Sep 26, 2025
a4887ec
Merge branch 'main' into cir_vector_logical_not
AmrDeveloper Sep 26, 2025
eca2bb5
Merge branch 'main' into cir_vector_logical_not
AmrDeveloper Sep 26, 2025
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8 changes: 5 additions & 3 deletions clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2087,9 +2087,11 @@ mlir::Value ScalarExprEmitter::VisitUnaryLNot(const UnaryOperator *e) {
if (e->getType()->isVectorType() &&
e->getType()->castAs<VectorType>()->getVectorKind() ==
VectorKind::Generic) {
assert(!cir::MissingFeatures::vectorType());
cgf.cgm.errorNYI(e->getSourceRange(), "vector logical not");
return {};
mlir::Value oper = Visit(e->getSubExpr());
mlir::Location loc = cgf.getLoc(e->getExprLoc());
mlir::Value zero = builder.getNullValue(oper.getType(), loc);
return cir::VecCmpOp::create(builder, loc, oper.getType(),
cir::CmpOpKind::eq, oper, zero);
}

// Compare operand to zero.
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28 changes: 27 additions & 1 deletion clang/test/CIR/CodeGen/vector-ext.cpp
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Expand Up @@ -1295,4 +1295,30 @@ void foo23() {
// OGCG: %[[NE_B_ZERO:.*]] = icmp ne <4 x i32> %[[TMP_B]], zeroinitializer
// OGCG: %[[VEC_OR:.*]] = and <4 x i1> %[[NE_A_ZERO]], %[[NE_B_ZERO]]
// OGCG: %[[RESULT:.*]] = sext <4 x i1> %[[VEC_OR]] to <4 x i32>
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16

void logical_not() {
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@andykaylor andykaylor Sep 25, 2025

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Can you also add a test for a floating-point type?

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@andykaylor andykaylor Sep 25, 2025

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Actually, it looks like clang won't let you do this with floats and ext vector types, but with the GNU-style vector attribute, you get an interesting result:

https://godbolt.org/z/njdWcWEWM

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@AmrDeveloper AmrDeveloper Sep 26, 2025

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First time to know that float f = 0.0f/0.0f; results in -nan in GCC and nan in clang :D

https://godbolt.org/z/1qv3aMvP8

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@andykaylor andykaylor Sep 26, 2025

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First time to know that float f = 0.0f/0.0f; results in -nan in GCC and nan in clang :D

Clang is constant folding the operation. The sign you get depends on the hardware.

https://godbolt.org/z/snWd9rdMb

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@AmrDeveloper AmrDeveloper Sep 26, 2025

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Wow, thanks for the information

vi4 a;
vi4 b = !a;
}

// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a"]
// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init]
// CIR: %[[TMP_A:.*]] = cir.load{{.*}}) %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
// CIR: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i>
// CIR: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>
// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>

// LLVM: %[[A_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
// LLVM: %[[B_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
// LLVM: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
// LLVM: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
// LLVM: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16

// OGCG: %[[A_ADDR:.*]] = alloca <4 x i32>, align 16
// OGCG: %[[B_ADDR:.*]] = alloca <4 x i32>, align 16
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
// OGCG: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
// OGCG: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
// OGCG: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16
28 changes: 27 additions & 1 deletion clang/test/CIR/CodeGen/vector.cpp
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Expand Up @@ -1337,4 +1337,30 @@ void foo26() {
// OGCG: %[[NE_B_ZERO:.*]] = icmp ne <4 x i32> %[[TMP_B]], zeroinitializer
// OGCG: %[[VEC_OR:.*]] = and <4 x i1> %[[NE_A_ZERO]], %[[NE_B_ZERO]]
// OGCG: %[[RESULT:.*]] = sext <4 x i1> %[[VEC_OR]] to <4 x i32>
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16
// OGCG: store <4 x i32> %[[RESULT]], ptr %[[C_ADDR]], align 16

void logical_not() {
vi4 a;
vi4 b = !a;
}

// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a"]
// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init]
// CIR: %[[TMP_A:.*]] = cir.load{{.*}}) %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i>
// CIR: %[[CONST_V0:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i>
// CIR: %[[RESULT:.*]] = cir.vec.cmp(eq, %[[TMP_A]], %[[CONST_V0]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i>
// CIR: cir.store{{.*}} %[[RESULT]], %[[B_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>

// LLVM: %[[A_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
// LLVM: %[[B_ADDR:.*]] = alloca <4 x i32>, i64 1, align 16
// LLVM: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
// LLVM: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
// LLVM: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
// LLVM: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16

// OGCG: %[[A_ADDR:.*]] = alloca <4 x i32>, align 16
// OGCG: %[[B_ADDR:.*]] = alloca <4 x i32>, align 16
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[A_ADDR]], align 16
// OGCG: %[[RESULT:.*]] = icmp eq <4 x i32> %[[TMP_A]], zeroinitializer
// OGCG: %[[RESULT_VI4:.*]] = sext <4 x i1> %[[RESULT]] to <4 x i32>
// OGCG: store <4 x i32> %[[RESULT_VI4]], ptr %[[B_ADDR]], align 16