diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index 53633eac3d2c3..54050242b1854 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1049,6 +1049,19 @@ void RISCVInstructionSelector::preISelLower(MachineInstr &MI,
     MRI->setType(DstReg, sXLen);
     break;
   }
+  case TargetOpcode::G_STORE: {
+    Register SrcReg = MI.getOperand(0).getReg();
+    MachineInstr *Def = MRI->getVRegDef(SrcReg);
+    if (Def && Def->getOpcode() == TargetOpcode::G_FCONSTANT) {
+      if (Def->getOperand(1).getFPImm()->getValueAPF().isPosZero()) {
+        MI.getOperand(0).setReg(RISCV::X0);
+
+        if (MRI->use_nodbg_empty(SrcReg))
+          Def->eraseFromParent();
+      }
+    }
+    break;
+  }
   }
 }
 
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll b/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
new file mode 100644
index 0000000000000..d9a6e4b5ec53a
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/store-fp-zero-to-x0.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -global-isel -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix=RV64
+
+define void @zero_f32(ptr %i) {
+; RV32-LABEL: zero_f32:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    sw zero, 0(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: zero_f32:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    sw zero, 0(a0)
+; RV64-NEXT:    ret
+entry:
+  store float 0.000000e+00, ptr %i, align 4
+  ret void
+}
+
+
+define void @zero_f64(ptr %i) {
+; RV32-LABEL: zero_f64:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32-NEXT:    addi a1, a1, %lo(.LCPI1_0)
+; RV32-NEXT:    lw a2, 0(a1)
+; RV32-NEXT:    lw a1, 4(a1)
+; RV32-NEXT:    sw a2, 0(a0)
+; RV32-NEXT:    sw a1, 4(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: zero_f64:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    sd zero, 0(a0)
+; RV64-NEXT:    ret
+entry:
+  store double 0.000000e+00, ptr %i, align 8
+  ret void
+}