diff --git a/clang/test/CodeGen/msp430-abi-complex.c b/clang/test/CodeGen/msp430-abi-complex.c index faafcd2cde3f8..8fc0d6d97ce64 100644 --- a/clang/test/CodeGen/msp430-abi-complex.c +++ b/clang/test/CodeGen/msp430-abi-complex.c @@ -202,7 +202,7 @@ float _Complex complex_float_res(void) { // CHECK-DAG: clr r12 // CHECK-DAG: mov #16256, r13 __imag__ res = -1; -// CHECK-DAG: clr r14 +// CHECK-DAG: mov r12, r14 // CHECK-DAG: mov #-16512, r15 return res; // CHECK: ret diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index ebfea8e5581bf..6fe1699d8b2b2 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -1326,6 +1326,79 @@ bool RegisterCoalescer::reMaterializeDef(const CoalescerPair &CP, if (!TII->isAsCheapAsAMove(*DefMI)) return false; + // Skip rematerialization for physical registers used as return values within + // the same basic block to enable better coalescing. + if (DstReg.isPhysical()) { + MachineBasicBlock *MBB = CopyMI->getParent(); + if (DefMI->getParent() == MBB && !MBB->empty()) { + // Quick check: is the last instruction a return using DstReg? + const MachineInstr &LastInstr = MBB->back(); + if (LastInstr.isReturn() && LastInstr.readsRegister(DstReg, TRI)) { + // This is a return register, perform checks + + // Exception: allow rematerialization for zero-idiom instructions + // (e.g., xorps %xmm0, %xmm0) because rematerialization produces + // independent zero-latency instructions, which is better than copying + const TargetSubtargetInfo &STI = MF->getSubtarget(); + APInt Mask; + if (STI.isZeroIdiom(DefMI, Mask)) { + LLVM_DEBUG(dbgs() << "\tAllow remat: zero-idiom instruction\n"); + } else { + // Check for duplicate DefMI before CopyMI + bool HasDuplicateDef = false; + for (MachineBasicBlock::iterator I = MBB->begin(); &*I != CopyMI; + ++I) { + if (&*I != DefMI && + I->isIdenticalTo(*DefMI, MachineInstr::IgnoreDefs)) { + HasDuplicateDef = true; + break; + } + } + + // Check if register is redefined after CopyMI + bool RegRedefinedAfterCopy = false; + for (MachineBasicBlock::iterator I = std::next(CopyMI->getIterator()); + I != MBB->end(); ++I) { + if (I->modifiesRegister(DstReg, TRI)) { + RegRedefinedAfterCopy = true; + break; + } + if (I->isReturn()) + break; + } + + // Skip remat only if: no duplicate def AND reg not redefined + if (!HasDuplicateDef && !RegRedefinedAfterCopy) { + // Exception: allow remat for constant moves with limited uses + if (DefMI->isMoveImmediate()) { + if (!MRI->hasOneNonDBGUse(SrcReg)) { + // Check if all uses are copies + bool OnlyUsedByCopies = true; + for (const MachineOperand &MO : MRI->use_operands(SrcReg)) { + const MachineInstr *UseMI = MO.getParent(); + if (!UseMI->isCopy() && !UseMI->isSubregToReg()) { + OnlyUsedByCopies = false; + break; + } + } + + if (!OnlyUsedByCopies || MRI->use_empty(SrcReg)) { + LLVM_DEBUG(dbgs() << "\tSkip remat for return register: " + << printReg(DstReg, TRI) << '\n'); + return false; + } + } + } else { + LLVM_DEBUG(dbgs() << "\tSkip remat for return register: " + << printReg(DstReg, TRI) << '\n'); + return false; + } + } + } + } + } + } + if (!TII->isReMaterializable(*DefMI)) return false; diff --git a/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll b/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll index 7d488c9ca2002..ea268ed83f3de 100644 --- a/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll +++ b/llvm/test/CodeGen/AArch64/aarch64_win64cc_vararg.ll @@ -52,9 +52,8 @@ define win64cc ptr @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 ; CHECK-LABEL: f9: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill -; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: add x0, sp, #24 -; CHECK-NEXT: str x8, [sp, #8] +; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret ; @@ -78,9 +77,8 @@ define win64cc ptr @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 ; CHECK-LABEL: f8: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: str x18, [sp, #-16]! // 8-byte Folded Spill -; CHECK-NEXT: add x8, sp, #16 ; CHECK-NEXT: add x0, sp, #16 -; CHECK-NEXT: str x8, [sp, #8] +; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: ldr x18, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ret ; @@ -104,10 +102,9 @@ define win64cc ptr @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 ; CHECK-LABEL: f7: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: str x18, [sp, #-32]! // 8-byte Folded Spill -; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: add x0, sp, #24 ; CHECK-NEXT: str x7, [sp, #24] -; CHECK-NEXT: str x8, [sp, #8] +; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: ldr x18, [sp], #32 // 8-byte Folded Reload ; CHECK-NEXT: ret ; diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll index e18a5f695ba29..98c3071de3ae8 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -2156,6 +2156,7 @@ define <4 x i16> @concat_vector_v4i16_const() { ; CHECK-LABEL: concat_vector_v4i16_const: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %r = shufflevector <1 x i16> zeroinitializer, <1 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %r @@ -2183,6 +2184,7 @@ define <8 x i8> @concat_vector_v8i8_const() { ; CHECK-LABEL: concat_vector_v8i8_const: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %r = shufflevector <1 x i8> zeroinitializer, <1 x i8> undef, <8 x i32> zeroinitializer ret <8 x i8> %r diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll index 197a385b0e7cb..b462fe99cbf64 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vector-ext.ll @@ -20,6 +20,7 @@ define void @func30(%T0_30 %v0, ptr %p1) { define <1 x i32> @autogen_SD7918() { ; CHECK-LABEL: autogen_SD7918 ; CHECK: movi.2d v0, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %I29 = insertelement <1 x i1> zeroinitializer, i1 false, i32 0 %ZE = zext <1 x i1> %I29 to <1 x i32> diff --git a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll index b225d9a1acaf5..86cf62304cc1c 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vshuffle.ll @@ -4,6 +4,7 @@ define <8 x i1> @test1() { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: movi.16b v0, #0 +; CHECK-NEXT: ; kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret entry: %Shuff = shufflevector <8 x i1> @foo1(<2 x i32> %a) { ; CHECK-SD-LABEL: foo1: ; CHECK-SD: // %bb.0: ; CHECK-SD-NEXT: movi v0.2d, #0000000000000000 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: foo1: @@ -28,6 +29,7 @@ define <4 x i16> @foo2(<2 x i32> %a) { ; CHECK-SD-LABEL: foo2: ; CHECK-SD: // %bb.0: ; CHECK-SD-NEXT: movi v0.2d, #0000000000000000 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: foo2: diff --git a/llvm/test/CodeGen/AArch64/combine-mul.ll b/llvm/test/CodeGen/AArch64/combine-mul.ll index ff6d1a571a084..5d65b21f902b7 100644 --- a/llvm/test/CodeGen/AArch64/combine-mul.ll +++ b/llvm/test/CodeGen/AArch64/combine-mul.ll @@ -18,6 +18,7 @@ define <4 x i1> @PR48683_vec(<4 x i32> %x) { ; CHECK-LABEL: PR48683_vec: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %a = mul <4 x i32> %x, %x %b = and <4 x i32> %a, @@ -29,6 +30,7 @@ define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) { ; CHECK-LABEL: PR48683_vec_undef: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %a = mul <4 x i32> %x, %x %b = and <4 x i32> %a, diff --git a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll index f62cfef9baf28..017971df99d6e 100644 --- a/llvm/test/CodeGen/AArch64/ext-narrow-index.ll +++ b/llvm/test/CodeGen/AArch64/ext-narrow-index.ll @@ -251,6 +251,7 @@ define <8 x i8> @i8_zero_off22(<16 x i8> %arg1) { ; CHECK-SD-LABEL: i8_zero_off22: ; CHECK-SD: // %bb.0: // %entry ; CHECK-SD-NEXT: movi v0.2d, #0000000000000000 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-SD-NEXT: ret ; ; CHECK-GISEL-LABEL: i8_zero_off22: @@ -302,6 +303,7 @@ define <4 x i16> @i16_zero_off8(<8 x i16> %arg1) { ; CHECK-LABEL: i16_zero_off8: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret entry: %shuffle = shufflevector <8 x i16> %arg1, <8 x i16> zeroinitializer, <4 x i32> @@ -346,6 +348,7 @@ define <2 x i32> @i32_zero_off4(<4 x i32> %arg1) { ; CHECK-LABEL: i32_zero_off4: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret entry: %shuffle = shufflevector <4 x i32> %arg1, <4 x i32> zeroinitializer, <2 x i32> diff --git a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll index 4de2c934a672e..fbb71ba1c295f 100644 --- a/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll +++ b/llvm/test/CodeGen/AArch64/fast-isel-const-float.ll @@ -9,6 +9,7 @@ define float @select_fp_const() { ; GISEL-LABEL: select_fp_const: ; GISEL: // %bb.0: // %entry ; GISEL-NEXT: movi v0.2s, #79, lsl #24 +; GISEL-NEXT: // kill: def $s0 killed $s0 killed $d0 ; GISEL-NEXT: ret ; ; FISEL-LABEL: select_fp_const: diff --git a/llvm/test/CodeGen/AArch64/movi64_sve.ll b/llvm/test/CodeGen/AArch64/movi64_sve.ll index 1d4e00d0c3d10..3253b35d77470 100644 --- a/llvm/test/CodeGen/AArch64/movi64_sve.ll +++ b/llvm/test/CodeGen/AArch64/movi64_sve.ll @@ -12,6 +12,7 @@ define <2 x i64> @movi_1_v2i64() { ; SVE-LABEL: movi_1_v2i64: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #1 // =0x1 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <2 x i64> splat (i64 1) } @@ -26,6 +27,7 @@ define <2 x i64> @movi_127_v2i64() { ; SVE-LABEL: movi_127_v2i64: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #127 // =0x7f +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <2 x i64> splat (i64 127) } @@ -40,6 +42,7 @@ define <2 x i64> @movi_m128_v2i64() { ; SVE-LABEL: movi_m128_v2i64: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #-128 // =0xffffffffffffff80 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <2 x i64> splat (i64 -128) } @@ -54,6 +57,7 @@ define <2 x i64> @movi_256_v2i64() { ; SVE-LABEL: movi_256_v2i64: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #256 // =0x100 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <2 x i64> splat (i64 256) } @@ -68,6 +72,7 @@ define <2 x i64> @movi_32512_v2i64() { ; SVE-LABEL: movi_32512_v2i64: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #32512 // =0x7f00 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <2 x i64> splat (i64 32512) } @@ -82,6 +87,7 @@ define <2 x i64> @movi_m32768_v2i64() { ; SVE-LABEL: movi_m32768_v2i64: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #-32768 // =0xffffffffffff8000 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <2 x i64> splat (i64 -32768) } @@ -98,6 +104,7 @@ define <4 x i32> @movi_v4i32_1() { ; SVE-LABEL: movi_v4i32_1: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #127 // =0x7f +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <4 x i32> } @@ -112,6 +119,7 @@ define <4 x i32> @movi_v4i32_2() { ; SVE-LABEL: movi_v4i32_2: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #32512 // =0x7f00 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <4 x i32> } @@ -126,6 +134,7 @@ define <8 x i16> @movi_v8i16_1() { ; SVE-LABEL: movi_v8i16_1: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #127 // =0x7f +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <8 x i16> } @@ -140,6 +149,7 @@ define <8 x i16> @movi_v8i16_2() { ; SVE-LABEL: movi_v8i16_2: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #32512 // =0x7f00 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <8 x i16> } @@ -154,6 +164,7 @@ define <16 x i8> @movi_v16i8_1() { ; SVE-LABEL: movi_v16i8_1: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #127 // =0x7f +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <16 x i8> } @@ -168,6 +179,7 @@ define <16 x i8> @movi_v16i8_2() { ; SVE-LABEL: movi_v16i8_2: ; SVE: // %bb.0: ; SVE-NEXT: mov z0.d, #32512 // =0x7f00 +; SVE-NEXT: // kill: def $q0 killed $q0 killed $z0 ; SVE-NEXT: ret ret <16 x i8> } diff --git a/llvm/test/CodeGen/AArch64/neon-abd.ll b/llvm/test/CodeGen/AArch64/neon-abd.ll index 314edd2fc81a7..c81438aa2250e 100644 --- a/llvm/test/CodeGen/AArch64/neon-abd.ll +++ b/llvm/test/CodeGen/AArch64/neon-abd.ll @@ -525,6 +525,7 @@ define <4 x i16> @combine_sabd_4h_zerosign(<4 x i16> %a, <4 x i16> %b) #0 { ; CHECK-LABEL: combine_sabd_4h_zerosign: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %a.ext = ashr <4 x i16> %a, %b.ext = ashr <4 x i16> %b, diff --git a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll index 11b3b62ec1c8d..47ceeece0a6e5 100644 --- a/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll +++ b/llvm/test/CodeGen/AArch64/neon-compare-instructions.ll @@ -2482,6 +2482,7 @@ define <2 x i32> @fcmal2xfloat(<2 x float> %A, <2 x float> %B) { ; CHECK-SD-LABEL: fcmal2xfloat: ; CHECK-SD: // %bb.0: ; CHECK-SD-NEXT: movi v0.2d, #0xffffffffffffffff +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: fcmal2xfloat: @@ -2535,6 +2536,7 @@ define <2 x i32> @fcmnv2xfloat(<2 x float> %A, <2 x float> %B) { ; CHECK-LABEL: fcmnv2xfloat: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret %tmp3 = fcmp false <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> diff --git a/llvm/test/CodeGen/AArch64/neon-mov.ll b/llvm/test/CodeGen/AArch64/neon-mov.ll index 5be9394f61b30..4e5b099d62e7f 100644 --- a/llvm/test/CodeGen/AArch64/neon-mov.ll +++ b/llvm/test/CodeGen/AArch64/neon-mov.ll @@ -16,6 +16,7 @@ define <8 x i8> @movi8b_0() { ; CHECK-LABEL: movi8b_0: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret ret <8 x i8> zeroinitializer } @@ -48,6 +49,7 @@ define <2 x i32> @movi2s_0() { ; CHECK-LABEL: movi2s_0: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret ret <2 x i32> zeroinitializer } @@ -417,6 +419,7 @@ define <2 x float> @fmov2s_0() { ; CHECK-LABEL: fmov2s_0: ; CHECK: // %bb.0: ; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 ; CHECK-NEXT: ret ret <2 x float> zeroinitializer } diff --git a/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll b/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll index 2a19d258f1adf..6f1b68dbcd667 100644 --- a/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll +++ b/llvm/test/CodeGen/AArch64/remat-const-float-simd.ll @@ -10,6 +10,7 @@ define float @foo() { ; CHECK-NEON-LABEL: foo: ; CHECK-NEON: // %bb.0: // %entry ; CHECK-NEON-NEXT: movi v0.2s, #79, lsl #24 +; CHECK-NEON-NEXT: // kill: def $s0 killed $s0 killed $d0 ; CHECK-NEON-NEXT: ret ; ; CHECK-SCALAR-LABEL: foo: diff --git a/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll b/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll index ebec275c92c52..1bdfac8d6c979 100644 --- a/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll +++ b/llvm/test/CodeGen/AArch64/sve-implicit-zero-filling.ll @@ -195,8 +195,8 @@ define @zero_fill_non_zero_index( %pg, @zero_fill_type_mismatch( %pg, %a) #0 { ; CHECK-LABEL: zero_fill_type_mismatch: ; CHECK: // %bb.0: -; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: movi v1.2d, #0000000000000000 +; CHECK-NEXT: uminv d0, p0, z0.d ; CHECK-NEXT: ret %t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64( %pg, %a) %t2 = insertelement zeroinitializer, i64 %t1, i64 0 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll index ad00e99b704dd..275d13ebfd949 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll @@ -419,6 +419,7 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) { ; CHECK-LABEL: insertelement_v1i64: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.d, #5 // =0x5 +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: insertelement_v1i64: diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll index 37435e35ceabf..9c7a3d5046d0e 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-test-register-mov.ll @@ -39,6 +39,7 @@ define <2 x i64> @fixed_vec_zero_constant() { ; CHECK-LABEL: fixed_vec_zero_constant: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.d, #0 // =0x0 +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fixed_vec_zero_constant: @@ -53,6 +54,7 @@ define <2 x double> @fixed_vec_fp_zero_constant() { ; CHECK-LABEL: fixed_vec_fp_zero_constant: ; CHECK: // %bb.0: ; CHECK-NEXT: mov z0.d, #0 // =0x0 +; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0 ; CHECK-NEXT: ret ; ; NONEON-NOSVE-LABEL: fixed_vec_fp_zero_constant: diff --git a/llvm/test/CodeGen/AArch64/win64_vararg.ll b/llvm/test/CodeGen/AArch64/win64_vararg.ll index d72dee9021251..f453f887453a0 100644 --- a/llvm/test/CodeGen/AArch64/win64_vararg.ll +++ b/llvm/test/CodeGen/AArch64/win64_vararg.ll @@ -32,9 +32,8 @@ define ptr @f9(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i6 ; CHECK-LABEL: f9: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: add x0, sp, #24 -; CHECK-NEXT: str x8, [sp, #8] +; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret entry: @@ -48,9 +47,8 @@ define ptr @f8(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, i6 ; CHECK-LABEL: f8: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: add x8, sp, #16 ; CHECK-NEXT: add x0, sp, #16 -; CHECK-NEXT: str x8, [sp, #8] +; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret entry: @@ -64,10 +62,9 @@ define ptr @f7(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, i64 %a5, i64 %a6, .. ; CHECK-LABEL: f7: ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: sub sp, sp, #32 -; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: add x0, sp, #24 ; CHECK-NEXT: str x7, [sp, #24] -; CHECK-NEXT: str x8, [sp, #8] +; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll index 833be2066cd54..0efe09371bd6f 100644 --- a/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll +++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.new.ll @@ -4453,6 +4453,7 @@ define float @v_fmul_0_fsub_0_safe_infloop_regression(float %arg) { ; SI-NSZ-NEXT: s_brev_b32 s4, 1 ; SI-NSZ-NEXT: v_fma_f32 v0, v0, s4, 0 ; SI-NSZ-NEXT: s_setpc_b64 s[30:31] +; ; FIXME: utils/update_llc_test_checks.py will generate redundant VI ; labels, remove them, they will cause test failure. bb: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll index d9f2fc55709a6..f47aac14bff3a 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.load.tr.gfx1250.w32.ll @@ -341,16 +341,27 @@ define { i32, <3 x i32> } @global_load_tr6_b96_vaddr_no_align2_requirement(ptr a } define { i32, <3 x i32> } @global_load_tr6_b96_saddr_no_align2_requirement(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use) { -; GFX1250-LABEL: global_load_tr6_b96_saddr_no_align2_requirement: -; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32 -; GFX1250-NEXT: s_wait_loadcnt 0x0 -; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2 -; GFX1250-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4 -; GFX1250-NEXT: s_set_pc_i64 s[30:31] +; GFX1250-SDAG-LABEL: global_load_tr6_b96_saddr_no_align2_requirement: +; GFX1250-SDAG: ; %bb.0: +; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 +; GFX1250-SDAG-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32 +; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v3 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v3, v4 +; GFX1250-SDAG-NEXT: s_set_pc_i64 s[30:31] +; +; GFX1250-GISEL-LABEL: global_load_tr6_b96_saddr_no_align2_requirement: +; GFX1250-GISEL: ; %bb.0: +; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 +; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0 +; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 +; GFX1250-GISEL-NEXT: global_load_tr6_b96 v[2:4], v0, s[0:1] offset:32 +; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v2 +; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, v3 :: v_dual_mov_b32 v3, v4 +; GFX1250-GISEL-NEXT: s_set_pc_i64 s[30:31] %gep = getelementptr i64, ptr addrspace(1) %addr, i32 4 %val = call <3 x i32> @llvm.amdgcn.global.load.tr6.b96.v3i32.p1(ptr addrspace(1) %gep) %insert0 = insertvalue { i32, <3 x i32> } poison, i32 0, 0 diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll index 7cc623fb0a616..79da8726fdde7 100644 --- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll +++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll @@ -560,20 +560,20 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { ; ARM6-LABEL: vec_4xi32_nonsplat_eq: ; ARM6: @ %bb.0: -; ARM6-NEXT: ldr r12, [sp, #4] +; ARM6-NEXT: push {r11, lr} +; ARM6-NEXT: ldr r12, [sp, #12] ; ARM6-NEXT: mov r0, #1 +; ARM6-NEXT: mov lr, #65280 +; ARM6-NEXT: orr lr, lr, #16711680 ; ARM6-NEXT: bic r1, r0, r1, lsl r12 -; ARM6-NEXT: ldr r12, [sp, #8] -; ARM6-NEXT: mov r0, #65280 -; ARM6-NEXT: orr r0, r0, #16711680 -; ARM6-NEXT: and r0, r0, r2, lsl r12 -; ARM6-NEXT: clz r0, r0 -; ARM6-NEXT: lsr r2, r0, #5 -; ARM6-NEXT: ldr r0, [sp, #12] -; ARM6-NEXT: mvn r0, r3, lsl r0 -; ARM6-NEXT: lsr r3, r0, #31 -; ARM6-NEXT: mov r0, #1 -; ARM6-NEXT: bx lr +; ARM6-NEXT: ldr r12, [sp, #16] +; ARM6-NEXT: and r2, lr, r2, lsl r12 +; ARM6-NEXT: ldr r12, [sp, #20] +; ARM6-NEXT: clz r2, r2 +; ARM6-NEXT: mvn r3, r3, lsl r12 +; ARM6-NEXT: lsr r2, r2, #5 +; ARM6-NEXT: lsr r3, r3, #31 +; ARM6-NEXT: pop {r11, pc} ; ; ARM78-LABEL: vec_4xi32_nonsplat_eq: ; ARM78: @ %bb.0: @@ -656,16 +656,14 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind { ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq: ; ARM6: @ %bb.0: -; ARM6-NEXT: push {r11, lr} -; ARM6-NEXT: ldr r2, [sp, #12] -; ARM6-NEXT: mov lr, #1 -; ARM6-NEXT: ldr r12, [sp, #8] -; ARM6-NEXT: bic r1, lr, r1, lsl r2 -; ARM6-NEXT: ldr r2, [sp, #20] -; ARM6-NEXT: bic r0, lr, r0, lsl r12 -; ARM6-NEXT: bic r3, lr, r3, lsl r2 +; ARM6-NEXT: ldr r12, [sp] ; ARM6-NEXT: mov r2, #1 -; ARM6-NEXT: pop {r11, pc} +; ARM6-NEXT: bic r0, r2, r0, lsl r12 +; ARM6-NEXT: ldr r12, [sp, #4] +; ARM6-NEXT: bic r1, r2, r1, lsl r12 +; ARM6-NEXT: ldr r12, [sp, #12] +; ARM6-NEXT: bic r3, r2, r3, lsl r12 +; ARM6-NEXT: bx lr ; ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq: ; ARM78: @ %bb.0: diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll index a8421ae9a6a89..335dc797e2a5e 100644 --- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll +++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll @@ -576,20 +576,20 @@ define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { ; ARM6-LABEL: vec_4xi32_nonsplat_eq: ; ARM6: @ %bb.0: -; ARM6-NEXT: ldr r12, [sp, #4] +; ARM6-NEXT: push {r11, lr} +; ARM6-NEXT: ldr r12, [sp, #12] ; ARM6-NEXT: mov r0, #1 +; ARM6-NEXT: mov lr, #65280 +; ARM6-NEXT: orr lr, lr, #16711680 ; ARM6-NEXT: bic r1, r0, r1, lsr r12 -; ARM6-NEXT: ldr r12, [sp, #8] -; ARM6-NEXT: mov r0, #65280 -; ARM6-NEXT: orr r0, r0, #16711680 -; ARM6-NEXT: and r0, r0, r2, lsr r12 -; ARM6-NEXT: clz r0, r0 -; ARM6-NEXT: lsr r2, r0, #5 -; ARM6-NEXT: ldr r0, [sp, #12] -; ARM6-NEXT: mvn r0, r3, lsr r0 -; ARM6-NEXT: lsr r3, r0, #31 -; ARM6-NEXT: mov r0, #1 -; ARM6-NEXT: bx lr +; ARM6-NEXT: ldr r12, [sp, #16] +; ARM6-NEXT: and r2, lr, r2, lsr r12 +; ARM6-NEXT: ldr r12, [sp, #20] +; ARM6-NEXT: clz r2, r2 +; ARM6-NEXT: mvn r3, r3, lsr r12 +; ARM6-NEXT: lsr r2, r2, #5 +; ARM6-NEXT: lsr r3, r3, #31 +; ARM6-NEXT: pop {r11, pc} ; ; ARM78-LABEL: vec_4xi32_nonsplat_eq: ; ARM78: @ %bb.0: @@ -670,16 +670,14 @@ define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind { ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq: ; ARM6: @ %bb.0: -; ARM6-NEXT: push {r11, lr} -; ARM6-NEXT: ldr r2, [sp, #12] -; ARM6-NEXT: mov lr, #1 -; ARM6-NEXT: ldr r12, [sp, #8] -; ARM6-NEXT: bic r1, lr, r1, lsr r2 -; ARM6-NEXT: ldr r2, [sp, #20] -; ARM6-NEXT: bic r0, lr, r0, lsr r12 -; ARM6-NEXT: bic r3, lr, r3, lsr r2 +; ARM6-NEXT: ldr r12, [sp] ; ARM6-NEXT: mov r2, #1 -; ARM6-NEXT: pop {r11, pc} +; ARM6-NEXT: bic r0, r2, r0, lsr r12 +; ARM6-NEXT: ldr r12, [sp, #4] +; ARM6-NEXT: bic r1, r2, r1, lsr r12 +; ARM6-NEXT: ldr r12, [sp, #12] +; ARM6-NEXT: bic r3, r2, r3, lsr r12 +; ARM6-NEXT: bx lr ; ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq: ; ARM78: @ %bb.0: diff --git a/llvm/test/CodeGen/ARM/select_const.ll b/llvm/test/CodeGen/ARM/select_const.ll index 180daa12e7c52..9419e212d52c1 100644 --- a/llvm/test/CodeGen/ARM/select_const.ll +++ b/llvm/test/CodeGen/ARM/select_const.ll @@ -766,7 +766,7 @@ define i64 @func(i64 %arg) { ; ARM-NEXT: adds r0, r0, #1 ; ARM-NEXT: mov r2, #0 ; ARM-NEXT: adcs r0, r1, #0 -; ARM-NEXT: mov r1, #0 +; ARM-NEXT: mov r1, r2 ; ARM-NEXT: adcs r0, r2, #0 ; ARM-NEXT: movne r0, #8 ; ARM-NEXT: mov pc, lr @@ -776,7 +776,7 @@ define i64 @func(i64 %arg) { ; THUMB2-NEXT: adds r0, #1 ; THUMB2-NEXT: mov.w r2, #0 ; THUMB2-NEXT: adcs r0, r1, #0 -; THUMB2-NEXT: mov.w r1, #0 +; THUMB2-NEXT: mov r1, r2 ; THUMB2-NEXT: adcs r0, r2, #0 ; THUMB2-NEXT: it ne ; THUMB2-NEXT: movne r0, #8 diff --git a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll index 6f154a9afffae..3065b4f46d476 100644 --- a/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll +++ b/llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll @@ -6,9 +6,9 @@ start: ; for some reason the i16 is loaded to r24:r25 ; and then moved to r23:r24 ; CHECK: ldi r22, 64 - ; CHECK-NEXT: r23, - ; CHECK-NEXT: r24, - ; CHECK-NEXT: r25, 11 + ; CHECK-NEXT: ldi r18, 0 + ; CHECK-NEXT: ldi r19, 4 + ; CHECK-NEXT: ldi r25, 11 %0 = insertvalue {i8, i16, i8} undef, i8 64, 0 %1 = insertvalue {i8, i16, i8} %0, i16 1024, 1 %2 = insertvalue {i8, i16, i8} %1, i8 11, 2 diff --git a/llvm/test/CodeGen/BPF/BTF/filename.ll b/llvm/test/CodeGen/BPF/BTF/filename.ll index ae08aea71b2cb..1d8f7ce6bf4b3 100644 --- a/llvm/test/CodeGen/BPF/BTF/filename.ll +++ b/llvm/test/CodeGen/BPF/BTF/filename.ll @@ -47,8 +47,8 @@ define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 { ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 20 ; CHECK-NEXT: .long 20 -; CHECK-NEXT: .long 28 -; CHECK-NEXT: .long 48 +; CHECK-NEXT: .long 44 +; CHECK-NEXT: .long 64 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 8 # FuncInfo ; CHECK-NEXT: .long 10 # FuncInfo section string offset=10 @@ -57,7 +57,11 @@ define dso_local i32 @test() local_unnamed_addr #0 !dbg !7 { ; CHECK-NEXT: .long 3 ; CHECK-NEXT: .long 16 # LineInfo ; CHECK-NEXT: .long 10 # LineInfo section string offset=10 -; CHECK-NEXT: .long 1 +; CHECK-NEXT: .long 2 +; CHECK-NEXT: .long .Lfunc_begin{{[0-9]+}} +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long 1024 # Line 1 Col 0 ; CHECK-NEXT: .long .Ltmp{{[0-9]+}} ; CHECK-NEXT: .long 16 ; CHECK-NEXT: .long 0 diff --git a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll index f9439e606ae87..121669e18e0eb 100644 --- a/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll +++ b/llvm/test/CodeGen/BPF/BTF/func-unused-arg.ll @@ -52,8 +52,8 @@ define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 { ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 20 ; CHECK-NEXT: .long 20 -; CHECK-NEXT: .long 28 -; CHECK-NEXT: .long 48 +; CHECK-NEXT: .long 44 +; CHECK-NEXT: .long 64 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 8 # FuncInfo ; CHECK-NEXT: .long 11 # FuncInfo section string offset=11 @@ -62,7 +62,11 @@ define dso_local i32 @f1(i32) local_unnamed_addr #0 !dbg !7 { ; CHECK-NEXT: .long 3 ; CHECK-NEXT: .long 16 # LineInfo ; CHECK-NEXT: .long 11 # LineInfo section string offset=11 -; CHECK-NEXT: .long 1 +; CHECK-NEXT: .long 2 +; CHECK-NEXT: .long .Lfunc_begin0 +; CHECK-NEXT: .long 17 +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long 1024 # Line 1 Col 0 ; CHECK-NEXT: .long .Ltmp{{[0-9]+}} ; CHECK-NEXT: .long 17 ; CHECK-NEXT: .long 0 diff --git a/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll b/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll index 67ad819108c7f..4e58b06e16a68 100644 --- a/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll +++ b/llvm/test/CodeGen/BPF/CORE/intrinsic-fieldinfo-existence-4.ll @@ -27,7 +27,12 @@ entry: } ; CHECK: r0 = 1 -; CHECK-NEXT: exit +; CHECK-NEXT: # kill: def $w0 killed $w0 killed $r0 +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: .loc 1 6 3 prologue_end # test.c:6:3 +; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: .Ltmp3: +; CHECK-NEXT: exit ; CHECK: .long 26 # BTF_KIND_STRUCT(id = 4) ; CHECK-NEXT: .long 67108865 # 0x4000001 diff --git a/llvm/test/CodeGen/BPF/fi_ri.ll b/llvm/test/CodeGen/BPF/fi_ri.ll index 8d60d29b52726..c5049d8cabc67 100644 --- a/llvm/test/CodeGen/BPF/fi_ri.ll +++ b/llvm/test/CodeGen/BPF/fi_ri.ll @@ -5,10 +5,10 @@ ; Function Attrs: nounwind uwtable define i32 @test() #0 { %key = alloca %struct.key_t, align 4 -; CHECK: r1 = 0 -; CHECK: *(u32 *)(r10 - 8) = r1 -; CHECK: *(u64 *)(r10 - 16) = r1 -; CHECK: *(u64 *)(r10 - 24) = r1 +; CHECK: r6 = 0 +; CHECK: *(u32 *)(r10 - 8) = r6 +; CHECK: *(u64 *)(r10 - 16) = r6 +; CHECK: *(u64 *)(r10 - 24) = r6 call void @llvm.memset.p0.i64(ptr align 4 %key, i8 0, i64 20, i1 false) ; CHECK: r1 = r10 ; CHECK: r1 += -20 diff --git a/llvm/test/CodeGen/BPF/inlineasm-wreg.ll b/llvm/test/CodeGen/BPF/inlineasm-wreg.ll index 496a2d909cb7c..3b17d89e906da 100644 --- a/llvm/test/CodeGen/BPF/inlineasm-wreg.ll +++ b/llvm/test/CodeGen/BPF/inlineasm-wreg.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: test_inlineasm_w_input_constraint define dso_local i32 @test_inlineasm_w_input_constraint() { tail call void asm sideeffect "w0 = $0", "w"(i32 42) -; CHECK: w0 = w1 +; CHECK: w0 = w0 ret i32 42 } diff --git a/llvm/test/CodeGen/BPF/rodata_1.ll b/llvm/test/CodeGen/BPF/rodata_1.ll index 26dd85caa1d21..560988b60115a 100644 --- a/llvm/test/CodeGen/BPF/rodata_1.ll +++ b/llvm/test/CodeGen/BPF/rodata_1.ll @@ -35,13 +35,13 @@ define i32 @test() local_unnamed_addr #0 { entry: tail call void @llvm.memcpy.p0.p0.i64(ptr @g1, ptr @test.t1, i64 3, i1 false) tail call void @llvm.memcpy.p0.p0.i64(ptr align 4 @g2, ptr align 4 @test.t2, i64 20, i1 false) -; CHECK: r1 = g1 -; CHECK: r2 = 0 -; CHECK: *(u8 *)(r1 + 1) = r2 -; CHECK: r3 = 1 -; CHECK: *(u8 *)(r1 + 2) = r3 -; CHECK: r1 = g2 -; CHECK: *(u32 *)(r1 + 8) = r3 +; CHECK: r1 = g1 ll +; CHECK: r0 = 0 +; CHECK: *(u8 *)(r1 + 1) = r0 +; CHECK: r2 = 1 +; CHECK: *(u8 *)(r1 + 2) = r2 +; CHECK: r1 = g2 ll +; CHECK: *(u32 *)(r1 + 8) = r2 ret i32 0 } ; CHECK: .section .rodata,"a",@progbits diff --git a/llvm/test/CodeGen/BPF/rodata_2.ll b/llvm/test/CodeGen/BPF/rodata_2.ll index bb7bf4ba8ace7..19cca46afbb5c 100644 --- a/llvm/test/CodeGen/BPF/rodata_2.ll +++ b/llvm/test/CodeGen/BPF/rodata_2.ll @@ -39,11 +39,11 @@ entry: ; CHECK: *(u32 *)(r1 + 20) = r2 ; CHECK: r2 = 1 ; CHECK: *(u32 *)(r1 + 16) = r2 -; CHECK: r2 = 0 -; CHECK: *(u32 *)(r1 + 28) = r2 -; CHECK: *(u32 *)(r1 + 8) = r2 -; CHECK: *(u32 *)(r1 + 4) = r2 -; CHECK: *(u32 *)(r1 + 0) = r2 +; CHECK: r0 = 0 +; CHECK: *(u32 *)(r1 + 28) = r0 +; CHECK: *(u32 *)(r1 + 8) = r0 +; CHECK: *(u32 *)(r1 + 4) = r0 +; CHECK: *(u32 *)(r1 + 0) = r0 ret i32 0 } ; CHECK: .section .rodata.cst32,"aM",@progbits,32 diff --git a/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll b/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll index 733c53697b987..97fe01e40e5b2 100644 --- a/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll +++ b/llvm/test/CodeGen/LoongArch/calling-conv-lp64d.ll @@ -92,6 +92,7 @@ define double @callee_double_ret() nounwind { ; CHECK-LABEL: callee_double_ret: ; CHECK: # %bb.0: ; CHECK-NEXT: vldi $vr0, -912 +; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 ; CHECK-NEXT: ret ret double 1.0 } diff --git a/llvm/test/CodeGen/LoongArch/double-imm.ll b/llvm/test/CodeGen/LoongArch/double-imm.ll index 0b715cb18f8ad..ab575a653487e 100644 --- a/llvm/test/CodeGen/LoongArch/double-imm.ll +++ b/llvm/test/CodeGen/LoongArch/double-imm.ll @@ -377,6 +377,7 @@ define double @f64_positive_fimm1() nounwind { ; LA64-LABEL: f64_positive_fimm1: ; LA64: # %bb.0: ; LA64-NEXT: vldi $vr0, -912 +; LA64-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0 ; LA64-NEXT: ret ret double 1.0 } diff --git a/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll b/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll index 551ab6ea44c66..93d27243e66bf 100644 --- a/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll +++ b/llvm/test/CodeGen/LoongArch/float-imm-vldi.ll @@ -7,6 +7,8 @@ define dso_local { float, double } @test1() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1280 ; CHECK-NEXT: vldi $vr1, -1024 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.0000000000, double 2.0000000000 } @@ -17,6 +19,8 @@ define dso_local { float, double } @test2() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1279 ; CHECK-NEXT: vldi $vr1, -1023 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.1250000000, double 2.1250000000 } @@ -27,6 +31,8 @@ define dso_local { float, double } @test3() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1278 ; CHECK-NEXT: vldi $vr1, -1022 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.2500000000, double 2.2500000000 } @@ -37,6 +43,8 @@ define dso_local { float, double } @test4() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1277 ; CHECK-NEXT: vldi $vr1, -1021 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.3750000000, double 2.3750000000 } @@ -47,6 +55,8 @@ define dso_local { float, double } @test5() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1276 ; CHECK-NEXT: vldi $vr1, -1020 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.5000000000, double 2.5000000000 } @@ -57,6 +67,8 @@ define dso_local { float, double } @test6() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1275 ; CHECK-NEXT: vldi $vr1, -1019 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.6250000000, double 2.6250000000 } @@ -67,6 +79,8 @@ define dso_local { float, double } @test7() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1274 ; CHECK-NEXT: vldi $vr1, -1018 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.7500000000, double 2.7500000000 } @@ -77,6 +91,8 @@ define dso_local { float, double } @test8() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1273 ; CHECK-NEXT: vldi $vr1, -1017 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 2.8750000000, double 2.8750000000 } @@ -87,6 +103,8 @@ define dso_local { float, double } @test9() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1272 ; CHECK-NEXT: vldi $vr1, -1016 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.0000000000, double 3.0000000000 } @@ -97,6 +115,8 @@ define dso_local { float, double } @test10() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1271 ; CHECK-NEXT: vldi $vr1, -1015 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.1250000000, double 3.1250000000 } @@ -107,6 +127,8 @@ define dso_local { float, double } @test11() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1270 ; CHECK-NEXT: vldi $vr1, -1014 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.2500000000, double 3.2500000000 } @@ -117,6 +139,8 @@ define dso_local { float, double } @test12() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1269 ; CHECK-NEXT: vldi $vr1, -1013 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.3750000000, double 3.3750000000 } @@ -127,6 +151,8 @@ define dso_local { float, double } @test13() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1268 ; CHECK-NEXT: vldi $vr1, -1012 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.5000000000, double 3.5000000000 } @@ -137,6 +163,8 @@ define dso_local { float, double } @test14() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1267 ; CHECK-NEXT: vldi $vr1, -1011 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.6250000000, double 3.6250000000 } @@ -147,6 +175,8 @@ define dso_local { float, double } @test15() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1266 ; CHECK-NEXT: vldi $vr1, -1010 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.7500000000, double 3.7500000000 } @@ -157,6 +187,8 @@ define dso_local { float, double } @test16() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1265 ; CHECK-NEXT: vldi $vr1, -1009 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 3.8750000000, double 3.8750000000 } @@ -167,6 +199,8 @@ define dso_local { float, double } @test17() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1264 ; CHECK-NEXT: vldi $vr1, -1008 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 4.0000000000, double 4.0000000000 } @@ -177,6 +211,8 @@ define dso_local { float, double } @test18() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1263 ; CHECK-NEXT: vldi $vr1, -1007 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 4.2500000000, double 4.2500000000 } @@ -187,6 +223,8 @@ define dso_local { float, double } @test19() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1262 ; CHECK-NEXT: vldi $vr1, -1006 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 4.5000000000, double 4.5000000000 } @@ -197,6 +235,8 @@ define dso_local { float, double } @test20() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1261 ; CHECK-NEXT: vldi $vr1, -1005 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 4.7500000000, double 4.7500000000 } @@ -207,6 +247,8 @@ define dso_local { float, double } @test21() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1260 ; CHECK-NEXT: vldi $vr1, -1004 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 5.0000000000, double 5.0000000000 } @@ -217,6 +259,8 @@ define dso_local { float, double } @test22() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1259 ; CHECK-NEXT: vldi $vr1, -1003 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 5.2500000000, double 5.2500000000 } @@ -227,6 +271,8 @@ define dso_local { float, double } @test23() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1258 ; CHECK-NEXT: vldi $vr1, -1002 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 5.5000000000, double 5.5000000000 } @@ -237,6 +283,8 @@ define dso_local { float, double } @test24() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1257 ; CHECK-NEXT: vldi $vr1, -1001 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 5.7500000000, double 5.7500000000 } @@ -247,6 +295,8 @@ define dso_local { float, double } @test25() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1256 ; CHECK-NEXT: vldi $vr1, -1000 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 6.0000000000, double 6.0000000000 } @@ -257,6 +307,8 @@ define dso_local { float, double } @test26() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1255 ; CHECK-NEXT: vldi $vr1, -999 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 6.2500000000, double 6.2500000000 } @@ -267,6 +319,8 @@ define dso_local { float, double } @test27() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1254 ; CHECK-NEXT: vldi $vr1, -998 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 6.5000000000, double 6.5000000000 } @@ -277,6 +331,8 @@ define dso_local { float, double } @test28() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1253 ; CHECK-NEXT: vldi $vr1, -997 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 6.7500000000, double 6.7500000000 } @@ -287,6 +343,8 @@ define dso_local { float, double } @test29() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1252 ; CHECK-NEXT: vldi $vr1, -996 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 7.0000000000, double 7.0000000000 } @@ -297,6 +355,8 @@ define dso_local { float, double } @test30() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1251 ; CHECK-NEXT: vldi $vr1, -995 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 7.2500000000, double 7.2500000000 } @@ -307,6 +367,8 @@ define dso_local { float, double } @test31() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1250 ; CHECK-NEXT: vldi $vr1, -994 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 7.5000000000, double 7.5000000000 } @@ -317,6 +379,8 @@ define dso_local { float, double } @test32() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1249 ; CHECK-NEXT: vldi $vr1, -993 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 7.7500000000, double 7.7500000000 } @@ -327,6 +391,8 @@ define dso_local { float, double } @test33() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1248 ; CHECK-NEXT: vldi $vr1, -992 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 8.0000000000, double 8.0000000000 } @@ -337,6 +403,8 @@ define dso_local { float, double } @test34() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1247 ; CHECK-NEXT: vldi $vr1, -991 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 8.5000000000, double 8.5000000000 } @@ -347,6 +415,8 @@ define dso_local { float, double } @test35() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1246 ; CHECK-NEXT: vldi $vr1, -990 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 9.0000000000, double 9.0000000000 } @@ -357,6 +427,8 @@ define dso_local { float, double } @test36() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1245 ; CHECK-NEXT: vldi $vr1, -989 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 9.5000000000, double 9.5000000000 } @@ -367,6 +439,8 @@ define dso_local { float, double } @test37() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1244 ; CHECK-NEXT: vldi $vr1, -988 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 10.0000000000, double 10.0000000000 } @@ -377,6 +451,8 @@ define dso_local { float, double } @test38() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1243 ; CHECK-NEXT: vldi $vr1, -987 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 10.5000000000, double 10.5000000000 } @@ -387,6 +463,8 @@ define dso_local { float, double } @test39() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1242 ; CHECK-NEXT: vldi $vr1, -986 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 11.0000000000, double 11.0000000000 } @@ -397,6 +475,8 @@ define dso_local { float, double } @test40() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1241 ; CHECK-NEXT: vldi $vr1, -985 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 11.5000000000, double 11.5000000000 } @@ -407,6 +487,8 @@ define dso_local { float, double } @test41() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1240 ; CHECK-NEXT: vldi $vr1, -984 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 12.0000000000, double 12.0000000000 } @@ -417,6 +499,8 @@ define dso_local { float, double } @test42() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1239 ; CHECK-NEXT: vldi $vr1, -983 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 12.5000000000, double 12.5000000000 } @@ -427,6 +511,8 @@ define dso_local { float, double } @test43() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1238 ; CHECK-NEXT: vldi $vr1, -982 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 13.0000000000, double 13.0000000000 } @@ -437,6 +523,8 @@ define dso_local { float, double } @test44() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1237 ; CHECK-NEXT: vldi $vr1, -981 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 13.5000000000, double 13.5000000000 } @@ -447,6 +535,8 @@ define dso_local { float, double } @test45() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1236 ; CHECK-NEXT: vldi $vr1, -980 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 14.0000000000, double 14.0000000000 } @@ -457,6 +547,8 @@ define dso_local { float, double } @test46() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1235 ; CHECK-NEXT: vldi $vr1, -979 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 14.5000000000, double 14.5000000000 } @@ -467,6 +559,8 @@ define dso_local { float, double } @test47() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1234 ; CHECK-NEXT: vldi $vr1, -978 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 15.0000000000, double 15.0000000000 } @@ -477,6 +571,8 @@ define dso_local { float, double } @test48() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1233 ; CHECK-NEXT: vldi $vr1, -977 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 15.5000000000, double 15.5000000000 } @@ -487,6 +583,8 @@ define dso_local { float, double } @test49() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1232 ; CHECK-NEXT: vldi $vr1, -976 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 16.0000000000, double 16.0000000000 } @@ -497,6 +595,8 @@ define dso_local { float, double } @test50() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1231 ; CHECK-NEXT: vldi $vr1, -975 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 17.0000000000, double 17.0000000000 } @@ -507,6 +607,8 @@ define dso_local { float, double } @test51() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1230 ; CHECK-NEXT: vldi $vr1, -974 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 18.0000000000, double 18.0000000000 } @@ -517,6 +619,8 @@ define dso_local { float, double } @test52() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1229 ; CHECK-NEXT: vldi $vr1, -973 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 19.0000000000, double 19.0000000000 } @@ -527,6 +631,8 @@ define dso_local { float, double } @test53() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1228 ; CHECK-NEXT: vldi $vr1, -972 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 20.0000000000, double 20.0000000000 } @@ -537,6 +643,8 @@ define dso_local { float, double } @test54() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1227 ; CHECK-NEXT: vldi $vr1, -971 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 21.0000000000, double 21.0000000000 } @@ -547,6 +655,8 @@ define dso_local { float, double } @test55() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1226 ; CHECK-NEXT: vldi $vr1, -970 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 22.0000000000, double 22.0000000000 } @@ -557,6 +667,8 @@ define dso_local { float, double } @test56() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1225 ; CHECK-NEXT: vldi $vr1, -969 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 23.0000000000, double 23.0000000000 } @@ -567,6 +679,8 @@ define dso_local { float, double } @test57() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1224 ; CHECK-NEXT: vldi $vr1, -968 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 24.0000000000, double 24.0000000000 } @@ -577,6 +691,8 @@ define dso_local { float, double } @test58() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1223 ; CHECK-NEXT: vldi $vr1, -967 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 25.0000000000, double 25.0000000000 } @@ -587,6 +703,8 @@ define dso_local { float, double } @test59() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1222 ; CHECK-NEXT: vldi $vr1, -966 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 26.0000000000, double 26.0000000000 } @@ -597,6 +715,8 @@ define dso_local { float, double } @test60() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1221 ; CHECK-NEXT: vldi $vr1, -965 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 27.0000000000, double 27.0000000000 } @@ -607,6 +727,8 @@ define dso_local { float, double } @test61() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1220 ; CHECK-NEXT: vldi $vr1, -964 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 28.0000000000, double 28.0000000000 } @@ -617,6 +739,8 @@ define dso_local { float, double } @test62() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1219 ; CHECK-NEXT: vldi $vr1, -963 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 29.0000000000, double 29.0000000000 } @@ -627,6 +751,8 @@ define dso_local { float, double } @test63() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1218 ; CHECK-NEXT: vldi $vr1, -962 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 30.0000000000, double 30.0000000000 } @@ -637,6 +763,8 @@ define dso_local { float, double } @test64() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1217 ; CHECK-NEXT: vldi $vr1, -961 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 31.0000000000, double 31.0000000000 } @@ -647,6 +775,8 @@ define dso_local { float, double } @test65() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1216 ; CHECK-NEXT: vldi $vr1, -960 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1250000000, double 0.1250000000 } @@ -657,6 +787,8 @@ define dso_local { float, double } @test66() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1215 ; CHECK-NEXT: vldi $vr1, -959 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1328125000, double 0.1328125000 } @@ -667,6 +799,8 @@ define dso_local { float, double } @test67() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1214 ; CHECK-NEXT: vldi $vr1, -958 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1406250000, double 0.1406250000 } @@ -677,6 +811,8 @@ define dso_local { float, double } @test68() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1213 ; CHECK-NEXT: vldi $vr1, -957 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1484375000, double 0.1484375000 } @@ -687,6 +823,8 @@ define dso_local { float, double } @test69() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1212 ; CHECK-NEXT: vldi $vr1, -956 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1562500000, double 0.1562500000 } @@ -697,6 +835,8 @@ define dso_local { float, double } @test70() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1211 ; CHECK-NEXT: vldi $vr1, -955 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1640625000, double 0.1640625000 } @@ -707,6 +847,8 @@ define dso_local { float, double } @test71() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1210 ; CHECK-NEXT: vldi $vr1, -954 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1718750000, double 0.1718750000 } @@ -717,6 +859,8 @@ define dso_local { float, double } @test72() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1209 ; CHECK-NEXT: vldi $vr1, -953 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1796875000, double 0.1796875000 } @@ -727,6 +871,8 @@ define dso_local { float, double } @test73() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1208 ; CHECK-NEXT: vldi $vr1, -952 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1875000000, double 0.1875000000 } @@ -737,6 +883,8 @@ define dso_local { float, double } @test74() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1207 ; CHECK-NEXT: vldi $vr1, -951 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.1953125000, double 0.1953125000 } @@ -747,6 +895,8 @@ define dso_local { float, double } @test75() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1206 ; CHECK-NEXT: vldi $vr1, -950 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2031250000, double 0.2031250000 } @@ -757,6 +907,8 @@ define dso_local { float, double } @test76() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1205 ; CHECK-NEXT: vldi $vr1, -949 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2109375000, double 0.2109375000 } @@ -767,6 +919,8 @@ define dso_local { float, double } @test77() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1204 ; CHECK-NEXT: vldi $vr1, -948 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2187500000, double 0.2187500000 } @@ -777,6 +931,8 @@ define dso_local { float, double } @test78() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1203 ; CHECK-NEXT: vldi $vr1, -947 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2265625000, double 0.2265625000 } @@ -787,6 +943,8 @@ define dso_local { float, double } @test79() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1202 ; CHECK-NEXT: vldi $vr1, -946 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2343750000, double 0.2343750000 } @@ -797,6 +955,8 @@ define dso_local { float, double } @test80() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1201 ; CHECK-NEXT: vldi $vr1, -945 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2421875000, double 0.2421875000 } @@ -807,6 +967,8 @@ define dso_local { float, double } @test81() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1200 ; CHECK-NEXT: vldi $vr1, -944 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2500000000, double 0.2500000000 } @@ -817,6 +979,8 @@ define dso_local { float, double } @test82() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1199 ; CHECK-NEXT: vldi $vr1, -943 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2656250000, double 0.2656250000 } @@ -827,6 +991,8 @@ define dso_local { float, double } @test83() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1198 ; CHECK-NEXT: vldi $vr1, -942 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2812500000, double 0.2812500000 } @@ -837,6 +1003,8 @@ define dso_local { float, double } @test84() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1197 ; CHECK-NEXT: vldi $vr1, -941 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.2968750000, double 0.2968750000 } @@ -847,6 +1015,8 @@ define dso_local { float, double } @test85() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1196 ; CHECK-NEXT: vldi $vr1, -940 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.3125000000, double 0.3125000000 } @@ -857,6 +1027,8 @@ define dso_local { float, double } @test86() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1195 ; CHECK-NEXT: vldi $vr1, -939 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.3281250000, double 0.3281250000 } @@ -867,6 +1039,8 @@ define dso_local { float, double } @test87() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1194 ; CHECK-NEXT: vldi $vr1, -938 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.3437500000, double 0.3437500000 } @@ -877,6 +1051,8 @@ define dso_local { float, double } @test88() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1193 ; CHECK-NEXT: vldi $vr1, -937 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.3593750000, double 0.3593750000 } @@ -887,6 +1063,8 @@ define dso_local { float, double } @test89() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1192 ; CHECK-NEXT: vldi $vr1, -936 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.3750000000, double 0.3750000000 } @@ -897,6 +1075,8 @@ define dso_local { float, double } @test90() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1191 ; CHECK-NEXT: vldi $vr1, -935 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.3906250000, double 0.3906250000 } @@ -907,6 +1087,8 @@ define dso_local { float, double } @test91() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1190 ; CHECK-NEXT: vldi $vr1, -934 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.4062500000, double 0.4062500000 } @@ -917,6 +1099,8 @@ define dso_local { float, double } @test92() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1189 ; CHECK-NEXT: vldi $vr1, -933 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.4218750000, double 0.4218750000 } @@ -927,6 +1111,8 @@ define dso_local { float, double } @test93() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1188 ; CHECK-NEXT: vldi $vr1, -932 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.4375000000, double 0.4375000000 } @@ -937,6 +1123,8 @@ define dso_local { float, double } @test94() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1187 ; CHECK-NEXT: vldi $vr1, -931 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.4531250000, double 0.4531250000 } @@ -947,6 +1135,8 @@ define dso_local { float, double } @test95() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1186 ; CHECK-NEXT: vldi $vr1, -930 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.4687500000, double 0.4687500000 } @@ -957,6 +1147,8 @@ define dso_local { float, double } @test96() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1185 ; CHECK-NEXT: vldi $vr1, -929 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.4843750000, double 0.4843750000 } @@ -967,6 +1159,8 @@ define dso_local { float, double } @test97() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1184 ; CHECK-NEXT: vldi $vr1, -928 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.5000000000, double 0.5000000000 } @@ -977,6 +1171,8 @@ define dso_local { float, double } @test98() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1183 ; CHECK-NEXT: vldi $vr1, -927 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.5312500000, double 0.5312500000 } @@ -987,6 +1183,8 @@ define dso_local { float, double } @test99() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1182 ; CHECK-NEXT: vldi $vr1, -926 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.5625000000, double 0.5625000000 } @@ -997,6 +1195,8 @@ define dso_local { float, double } @test100() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1181 ; CHECK-NEXT: vldi $vr1, -925 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.5937500000, double 0.5937500000 } @@ -1007,6 +1207,8 @@ define dso_local { float, double } @test101() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1180 ; CHECK-NEXT: vldi $vr1, -924 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.6250000000, double 0.6250000000 } @@ -1017,6 +1219,8 @@ define dso_local { float, double } @test102() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1179 ; CHECK-NEXT: vldi $vr1, -923 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.6562500000, double 0.6562500000 } @@ -1027,6 +1231,8 @@ define dso_local { float, double } @test103() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1178 ; CHECK-NEXT: vldi $vr1, -922 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.6875000000, double 0.6875000000 } @@ -1037,6 +1243,8 @@ define dso_local { float, double } @test104() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1177 ; CHECK-NEXT: vldi $vr1, -921 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.7187500000, double 0.7187500000 } @@ -1047,6 +1255,8 @@ define dso_local { float, double } @test105() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1176 ; CHECK-NEXT: vldi $vr1, -920 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.7500000000, double 0.7500000000 } @@ -1057,6 +1267,8 @@ define dso_local { float, double } @test106() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1175 ; CHECK-NEXT: vldi $vr1, -919 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.7812500000, double 0.7812500000 } @@ -1067,6 +1279,8 @@ define dso_local { float, double } @test107() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1174 ; CHECK-NEXT: vldi $vr1, -918 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.8125000000, double 0.8125000000 } @@ -1077,6 +1291,8 @@ define dso_local { float, double } @test108() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1173 ; CHECK-NEXT: vldi $vr1, -917 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.8437500000, double 0.8437500000 } @@ -1087,6 +1303,8 @@ define dso_local { float, double } @test109() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1172 ; CHECK-NEXT: vldi $vr1, -916 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.8750000000, double 0.8750000000 } @@ -1097,6 +1315,8 @@ define dso_local { float, double } @test110() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1171 ; CHECK-NEXT: vldi $vr1, -915 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.9062500000, double 0.9062500000 } @@ -1107,6 +1327,8 @@ define dso_local { float, double } @test111() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1170 ; CHECK-NEXT: vldi $vr1, -914 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.9375000000, double 0.9375000000 } @@ -1117,6 +1339,8 @@ define dso_local { float, double } @test112() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1169 ; CHECK-NEXT: vldi $vr1, -913 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 0.9687500000, double 0.9687500000 } @@ -1127,6 +1351,8 @@ define dso_local { float, double } @test113() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1168 ; CHECK-NEXT: vldi $vr1, -912 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.0000000000, double 1.0000000000 } @@ -1137,6 +1363,8 @@ define dso_local { float, double } @test114() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1167 ; CHECK-NEXT: vldi $vr1, -911 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.0625000000, double 1.0625000000 } @@ -1147,6 +1375,8 @@ define dso_local { float, double } @test115() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1166 ; CHECK-NEXT: vldi $vr1, -910 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.1250000000, double 1.1250000000 } @@ -1157,6 +1387,8 @@ define dso_local { float, double } @test116() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1165 ; CHECK-NEXT: vldi $vr1, -909 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.1875000000, double 1.1875000000 } @@ -1167,6 +1399,8 @@ define dso_local { float, double } @test117() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1164 ; CHECK-NEXT: vldi $vr1, -908 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.2500000000, double 1.2500000000 } @@ -1177,6 +1411,8 @@ define dso_local { float, double } @test118() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1163 ; CHECK-NEXT: vldi $vr1, -907 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.3125000000, double 1.3125000000 } @@ -1187,6 +1423,8 @@ define dso_local { float, double } @test119() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1162 ; CHECK-NEXT: vldi $vr1, -906 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.3750000000, double 1.3750000000 } @@ -1197,6 +1435,8 @@ define dso_local { float, double } @test120() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1161 ; CHECK-NEXT: vldi $vr1, -905 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.4375000000, double 1.4375000000 } @@ -1207,6 +1447,8 @@ define dso_local { float, double } @test121() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1160 ; CHECK-NEXT: vldi $vr1, -904 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.5000000000, double 1.5000000000 } @@ -1217,6 +1459,8 @@ define dso_local { float, double } @test122() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1159 ; CHECK-NEXT: vldi $vr1, -903 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.5625000000, double 1.5625000000 } @@ -1227,6 +1471,8 @@ define dso_local { float, double } @test123() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1158 ; CHECK-NEXT: vldi $vr1, -902 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.6250000000, double 1.6250000000 } @@ -1237,6 +1483,8 @@ define dso_local { float, double } @test124() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1157 ; CHECK-NEXT: vldi $vr1, -901 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.6875000000, double 1.6875000000 } @@ -1247,6 +1495,8 @@ define dso_local { float, double } @test125() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1156 ; CHECK-NEXT: vldi $vr1, -900 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.7500000000, double 1.7500000000 } @@ -1257,6 +1507,8 @@ define dso_local { float, double } @test126() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1155 ; CHECK-NEXT: vldi $vr1, -899 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.8125000000, double 1.8125000000 } @@ -1267,6 +1519,8 @@ define dso_local { float, double } @test127() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1154 ; CHECK-NEXT: vldi $vr1, -898 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.8750000000, double 1.8750000000 } @@ -1277,6 +1531,8 @@ define dso_local { float, double } @test128() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1153 ; CHECK-NEXT: vldi $vr1, -897 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float 1.9375000000, double 1.9375000000 } @@ -1287,6 +1543,8 @@ define dso_local { float, double } @test129() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1152 ; CHECK-NEXT: vldi $vr1, -896 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.0000000000, double -2.0000000000 } @@ -1297,6 +1555,8 @@ define dso_local { float, double } @test130() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1151 ; CHECK-NEXT: vldi $vr1, -895 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.1250000000, double -2.1250000000 } @@ -1307,6 +1567,8 @@ define dso_local { float, double } @test131() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1150 ; CHECK-NEXT: vldi $vr1, -894 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.2500000000, double -2.2500000000 } @@ -1317,6 +1579,8 @@ define dso_local { float, double } @test132() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1149 ; CHECK-NEXT: vldi $vr1, -893 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.3750000000, double -2.3750000000 } @@ -1327,6 +1591,8 @@ define dso_local { float, double } @test133() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1148 ; CHECK-NEXT: vldi $vr1, -892 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.5000000000, double -2.5000000000 } @@ -1337,6 +1603,8 @@ define dso_local { float, double } @test134() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1147 ; CHECK-NEXT: vldi $vr1, -891 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.6250000000, double -2.6250000000 } @@ -1347,6 +1615,8 @@ define dso_local { float, double } @test135() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1146 ; CHECK-NEXT: vldi $vr1, -890 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.7500000000, double -2.7500000000 } @@ -1357,6 +1627,8 @@ define dso_local { float, double } @test136() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1145 ; CHECK-NEXT: vldi $vr1, -889 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -2.8750000000, double -2.8750000000 } @@ -1367,6 +1639,8 @@ define dso_local { float, double } @test137() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1144 ; CHECK-NEXT: vldi $vr1, -888 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.0000000000, double -3.0000000000 } @@ -1377,6 +1651,8 @@ define dso_local { float, double } @test138() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1143 ; CHECK-NEXT: vldi $vr1, -887 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.1250000000, double -3.1250000000 } @@ -1387,6 +1663,8 @@ define dso_local { float, double } @test139() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1142 ; CHECK-NEXT: vldi $vr1, -886 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.2500000000, double -3.2500000000 } @@ -1397,6 +1675,8 @@ define dso_local { float, double } @test140() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1141 ; CHECK-NEXT: vldi $vr1, -885 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.3750000000, double -3.3750000000 } @@ -1407,6 +1687,8 @@ define dso_local { float, double } @test141() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1140 ; CHECK-NEXT: vldi $vr1, -884 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.5000000000, double -3.5000000000 } @@ -1417,6 +1699,8 @@ define dso_local { float, double } @test142() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1139 ; CHECK-NEXT: vldi $vr1, -883 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.6250000000, double -3.6250000000 } @@ -1427,6 +1711,8 @@ define dso_local { float, double } @test143() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1138 ; CHECK-NEXT: vldi $vr1, -882 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.7500000000, double -3.7500000000 } @@ -1437,6 +1723,8 @@ define dso_local { float, double } @test144() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1137 ; CHECK-NEXT: vldi $vr1, -881 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -3.8750000000, double -3.8750000000 } @@ -1447,6 +1735,8 @@ define dso_local { float, double } @test145() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1136 ; CHECK-NEXT: vldi $vr1, -880 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -4.0000000000, double -4.0000000000 } @@ -1457,6 +1747,8 @@ define dso_local { float, double } @test146() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1135 ; CHECK-NEXT: vldi $vr1, -879 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -4.2500000000, double -4.2500000000 } @@ -1467,6 +1759,8 @@ define dso_local { float, double } @test147() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1134 ; CHECK-NEXT: vldi $vr1, -878 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -4.5000000000, double -4.5000000000 } @@ -1477,6 +1771,8 @@ define dso_local { float, double } @test148() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1133 ; CHECK-NEXT: vldi $vr1, -877 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -4.7500000000, double -4.7500000000 } @@ -1487,6 +1783,8 @@ define dso_local { float, double } @test149() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1132 ; CHECK-NEXT: vldi $vr1, -876 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -5.0000000000, double -5.0000000000 } @@ -1497,6 +1795,8 @@ define dso_local { float, double } @test150() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1131 ; CHECK-NEXT: vldi $vr1, -875 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -5.2500000000, double -5.2500000000 } @@ -1507,6 +1807,8 @@ define dso_local { float, double } @test151() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1130 ; CHECK-NEXT: vldi $vr1, -874 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -5.5000000000, double -5.5000000000 } @@ -1517,6 +1819,8 @@ define dso_local { float, double } @test152() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1129 ; CHECK-NEXT: vldi $vr1, -873 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -5.7500000000, double -5.7500000000 } @@ -1527,6 +1831,8 @@ define dso_local { float, double } @test153() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1128 ; CHECK-NEXT: vldi $vr1, -872 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -6.0000000000, double -6.0000000000 } @@ -1537,6 +1843,8 @@ define dso_local { float, double } @test154() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1127 ; CHECK-NEXT: vldi $vr1, -871 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -6.2500000000, double -6.2500000000 } @@ -1547,6 +1855,8 @@ define dso_local { float, double } @test155() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1126 ; CHECK-NEXT: vldi $vr1, -870 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -6.5000000000, double -6.5000000000 } @@ -1557,6 +1867,8 @@ define dso_local { float, double } @test156() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1125 ; CHECK-NEXT: vldi $vr1, -869 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -6.7500000000, double -6.7500000000 } @@ -1567,6 +1879,8 @@ define dso_local { float, double } @test157() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1124 ; CHECK-NEXT: vldi $vr1, -868 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -7.0000000000, double -7.0000000000 } @@ -1577,6 +1891,8 @@ define dso_local { float, double } @test158() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1123 ; CHECK-NEXT: vldi $vr1, -867 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -7.2500000000, double -7.2500000000 } @@ -1587,6 +1903,8 @@ define dso_local { float, double } @test159() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1122 ; CHECK-NEXT: vldi $vr1, -866 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -7.5000000000, double -7.5000000000 } @@ -1597,6 +1915,8 @@ define dso_local { float, double } @test160() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1121 ; CHECK-NEXT: vldi $vr1, -865 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -7.7500000000, double -7.7500000000 } @@ -1607,6 +1927,8 @@ define dso_local { float, double } @test161() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1120 ; CHECK-NEXT: vldi $vr1, -864 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -8.0000000000, double -8.0000000000 } @@ -1617,6 +1939,8 @@ define dso_local { float, double } @test162() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1119 ; CHECK-NEXT: vldi $vr1, -863 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -8.5000000000, double -8.5000000000 } @@ -1627,6 +1951,8 @@ define dso_local { float, double } @test163() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1118 ; CHECK-NEXT: vldi $vr1, -862 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -9.0000000000, double -9.0000000000 } @@ -1637,6 +1963,8 @@ define dso_local { float, double } @test164() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1117 ; CHECK-NEXT: vldi $vr1, -861 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -9.5000000000, double -9.5000000000 } @@ -1647,6 +1975,8 @@ define dso_local { float, double } @test165() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1116 ; CHECK-NEXT: vldi $vr1, -860 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -10.0000000000, double -10.0000000000 } @@ -1657,6 +1987,8 @@ define dso_local { float, double } @test166() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1115 ; CHECK-NEXT: vldi $vr1, -859 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -10.5000000000, double -10.5000000000 } @@ -1667,6 +1999,8 @@ define dso_local { float, double } @test167() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1114 ; CHECK-NEXT: vldi $vr1, -858 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -11.0000000000, double -11.0000000000 } @@ -1677,6 +2011,8 @@ define dso_local { float, double } @test168() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1113 ; CHECK-NEXT: vldi $vr1, -857 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -11.5000000000, double -11.5000000000 } @@ -1687,6 +2023,8 @@ define dso_local { float, double } @test169() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1112 ; CHECK-NEXT: vldi $vr1, -856 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -12.0000000000, double -12.0000000000 } @@ -1697,6 +2035,8 @@ define dso_local { float, double } @test170() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1111 ; CHECK-NEXT: vldi $vr1, -855 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -12.5000000000, double -12.5000000000 } @@ -1707,6 +2047,8 @@ define dso_local { float, double } @test171() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1110 ; CHECK-NEXT: vldi $vr1, -854 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -13.0000000000, double -13.0000000000 } @@ -1717,6 +2059,8 @@ define dso_local { float, double } @test172() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1109 ; CHECK-NEXT: vldi $vr1, -853 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -13.5000000000, double -13.5000000000 } @@ -1727,6 +2071,8 @@ define dso_local { float, double } @test173() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1108 ; CHECK-NEXT: vldi $vr1, -852 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -14.0000000000, double -14.0000000000 } @@ -1737,6 +2083,8 @@ define dso_local { float, double } @test174() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1107 ; CHECK-NEXT: vldi $vr1, -851 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -14.5000000000, double -14.5000000000 } @@ -1747,6 +2095,8 @@ define dso_local { float, double } @test175() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1106 ; CHECK-NEXT: vldi $vr1, -850 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -15.0000000000, double -15.0000000000 } @@ -1757,6 +2107,8 @@ define dso_local { float, double } @test176() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1105 ; CHECK-NEXT: vldi $vr1, -849 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -15.5000000000, double -15.5000000000 } @@ -1767,6 +2119,8 @@ define dso_local { float, double } @test177() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1104 ; CHECK-NEXT: vldi $vr1, -848 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -16.0000000000, double -16.0000000000 } @@ -1777,6 +2131,8 @@ define dso_local { float, double } @test178() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1103 ; CHECK-NEXT: vldi $vr1, -847 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -17.0000000000, double -17.0000000000 } @@ -1787,6 +2143,8 @@ define dso_local { float, double } @test179() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1102 ; CHECK-NEXT: vldi $vr1, -846 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -18.0000000000, double -18.0000000000 } @@ -1797,6 +2155,8 @@ define dso_local { float, double } @test180() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1101 ; CHECK-NEXT: vldi $vr1, -845 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -19.0000000000, double -19.0000000000 } @@ -1807,6 +2167,8 @@ define dso_local { float, double } @test181() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1100 ; CHECK-NEXT: vldi $vr1, -844 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -20.0000000000, double -20.0000000000 } @@ -1817,6 +2179,8 @@ define dso_local { float, double } @test182() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1099 ; CHECK-NEXT: vldi $vr1, -843 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -21.0000000000, double -21.0000000000 } @@ -1827,6 +2191,8 @@ define dso_local { float, double } @test183() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1098 ; CHECK-NEXT: vldi $vr1, -842 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -22.0000000000, double -22.0000000000 } @@ -1837,6 +2203,8 @@ define dso_local { float, double } @test184() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1097 ; CHECK-NEXT: vldi $vr1, -841 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -23.0000000000, double -23.0000000000 } @@ -1847,6 +2215,8 @@ define dso_local { float, double } @test185() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1096 ; CHECK-NEXT: vldi $vr1, -840 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -24.0000000000, double -24.0000000000 } @@ -1857,6 +2227,8 @@ define dso_local { float, double } @test186() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1095 ; CHECK-NEXT: vldi $vr1, -839 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -25.0000000000, double -25.0000000000 } @@ -1867,6 +2239,8 @@ define dso_local { float, double } @test187() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1094 ; CHECK-NEXT: vldi $vr1, -838 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -26.0000000000, double -26.0000000000 } @@ -1877,6 +2251,8 @@ define dso_local { float, double } @test188() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1093 ; CHECK-NEXT: vldi $vr1, -837 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -27.0000000000, double -27.0000000000 } @@ -1887,6 +2263,8 @@ define dso_local { float, double } @test189() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1092 ; CHECK-NEXT: vldi $vr1, -836 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -28.0000000000, double -28.0000000000 } @@ -1897,6 +2275,8 @@ define dso_local { float, double } @test190() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1091 ; CHECK-NEXT: vldi $vr1, -835 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -29.0000000000, double -29.0000000000 } @@ -1907,6 +2287,8 @@ define dso_local { float, double } @test191() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1090 ; CHECK-NEXT: vldi $vr1, -834 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -30.0000000000, double -30.0000000000 } @@ -1917,6 +2299,8 @@ define dso_local { float, double } @test192() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1089 ; CHECK-NEXT: vldi $vr1, -833 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -31.0000000000, double -31.0000000000 } @@ -1927,6 +2311,8 @@ define dso_local { float, double } @test193() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1088 ; CHECK-NEXT: vldi $vr1, -832 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1250000000, double -0.1250000000 } @@ -1937,6 +2323,8 @@ define dso_local { float, double } @test194() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1087 ; CHECK-NEXT: vldi $vr1, -831 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1328125000, double -0.1328125000 } @@ -1947,6 +2335,8 @@ define dso_local { float, double } @test195() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1086 ; CHECK-NEXT: vldi $vr1, -830 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1406250000, double -0.1406250000 } @@ -1957,6 +2347,8 @@ define dso_local { float, double } @test196() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1085 ; CHECK-NEXT: vldi $vr1, -829 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1484375000, double -0.1484375000 } @@ -1967,6 +2359,8 @@ define dso_local { float, double } @test197() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1084 ; CHECK-NEXT: vldi $vr1, -828 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1562500000, double -0.1562500000 } @@ -1977,6 +2371,8 @@ define dso_local { float, double } @test198() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1083 ; CHECK-NEXT: vldi $vr1, -827 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1640625000, double -0.1640625000 } @@ -1987,6 +2383,8 @@ define dso_local { float, double } @test199() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1082 ; CHECK-NEXT: vldi $vr1, -826 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1718750000, double -0.1718750000 } @@ -1997,6 +2395,8 @@ define dso_local { float, double } @test200() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1081 ; CHECK-NEXT: vldi $vr1, -825 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1796875000, double -0.1796875000 } @@ -2007,6 +2407,8 @@ define dso_local { float, double } @test201() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1080 ; CHECK-NEXT: vldi $vr1, -824 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1875000000, double -0.1875000000 } @@ -2017,6 +2419,8 @@ define dso_local { float, double } @test202() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1079 ; CHECK-NEXT: vldi $vr1, -823 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.1953125000, double -0.1953125000 } @@ -2027,6 +2431,8 @@ define dso_local { float, double } @test203() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1078 ; CHECK-NEXT: vldi $vr1, -822 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2031250000, double -0.2031250000 } @@ -2037,6 +2443,8 @@ define dso_local { float, double } @test204() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1077 ; CHECK-NEXT: vldi $vr1, -821 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2109375000, double -0.2109375000 } @@ -2047,6 +2455,8 @@ define dso_local { float, double } @test205() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1076 ; CHECK-NEXT: vldi $vr1, -820 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2187500000, double -0.2187500000 } @@ -2057,6 +2467,8 @@ define dso_local { float, double } @test206() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1075 ; CHECK-NEXT: vldi $vr1, -819 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2265625000, double -0.2265625000 } @@ -2067,6 +2479,8 @@ define dso_local { float, double } @test207() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1074 ; CHECK-NEXT: vldi $vr1, -818 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2343750000, double -0.2343750000 } @@ -2077,6 +2491,8 @@ define dso_local { float, double } @test208() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1073 ; CHECK-NEXT: vldi $vr1, -817 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2421875000, double -0.2421875000 } @@ -2087,6 +2503,8 @@ define dso_local { float, double } @test209() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1072 ; CHECK-NEXT: vldi $vr1, -816 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2500000000, double -0.2500000000 } @@ -2097,6 +2515,8 @@ define dso_local { float, double } @test210() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1071 ; CHECK-NEXT: vldi $vr1, -815 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2656250000, double -0.2656250000 } @@ -2107,6 +2527,8 @@ define dso_local { float, double } @test211() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1070 ; CHECK-NEXT: vldi $vr1, -814 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2812500000, double -0.2812500000 } @@ -2117,6 +2539,8 @@ define dso_local { float, double } @test212() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1069 ; CHECK-NEXT: vldi $vr1, -813 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.2968750000, double -0.2968750000 } @@ -2127,6 +2551,8 @@ define dso_local { float, double } @test213() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1068 ; CHECK-NEXT: vldi $vr1, -812 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.3125000000, double -0.3125000000 } @@ -2137,6 +2563,8 @@ define dso_local { float, double } @test214() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1067 ; CHECK-NEXT: vldi $vr1, -811 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.3281250000, double -0.3281250000 } @@ -2147,6 +2575,8 @@ define dso_local { float, double } @test215() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1066 ; CHECK-NEXT: vldi $vr1, -810 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.3437500000, double -0.3437500000 } @@ -2157,6 +2587,8 @@ define dso_local { float, double } @test216() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1065 ; CHECK-NEXT: vldi $vr1, -809 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.3593750000, double -0.3593750000 } @@ -2167,6 +2599,8 @@ define dso_local { float, double } @test217() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1064 ; CHECK-NEXT: vldi $vr1, -808 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.3750000000, double -0.3750000000 } @@ -2177,6 +2611,8 @@ define dso_local { float, double } @test218() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1063 ; CHECK-NEXT: vldi $vr1, -807 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.3906250000, double -0.3906250000 } @@ -2187,6 +2623,8 @@ define dso_local { float, double } @test219() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1062 ; CHECK-NEXT: vldi $vr1, -806 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.4062500000, double -0.4062500000 } @@ -2197,6 +2635,8 @@ define dso_local { float, double } @test220() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1061 ; CHECK-NEXT: vldi $vr1, -805 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.4218750000, double -0.4218750000 } @@ -2207,6 +2647,8 @@ define dso_local { float, double } @test221() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1060 ; CHECK-NEXT: vldi $vr1, -804 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.4375000000, double -0.4375000000 } @@ -2217,6 +2659,8 @@ define dso_local { float, double } @test222() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1059 ; CHECK-NEXT: vldi $vr1, -803 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.4531250000, double -0.4531250000 } @@ -2227,6 +2671,8 @@ define dso_local { float, double } @test223() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1058 ; CHECK-NEXT: vldi $vr1, -802 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.4687500000, double -0.4687500000 } @@ -2237,6 +2683,8 @@ define dso_local { float, double } @test224() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1057 ; CHECK-NEXT: vldi $vr1, -801 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.4843750000, double -0.4843750000 } @@ -2247,6 +2695,8 @@ define dso_local { float, double } @test225() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1056 ; CHECK-NEXT: vldi $vr1, -800 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.5000000000, double -0.5000000000 } @@ -2257,6 +2707,8 @@ define dso_local { float, double } @test226() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1055 ; CHECK-NEXT: vldi $vr1, -799 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.5312500000, double -0.5312500000 } @@ -2267,6 +2719,8 @@ define dso_local { float, double } @test227() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1054 ; CHECK-NEXT: vldi $vr1, -798 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.5625000000, double -0.5625000000 } @@ -2277,6 +2731,8 @@ define dso_local { float, double } @test228() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1053 ; CHECK-NEXT: vldi $vr1, -797 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.5937500000, double -0.5937500000 } @@ -2287,6 +2743,8 @@ define dso_local { float, double } @test229() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1052 ; CHECK-NEXT: vldi $vr1, -796 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.6250000000, double -0.6250000000 } @@ -2297,6 +2755,8 @@ define dso_local { float, double } @test230() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1051 ; CHECK-NEXT: vldi $vr1, -795 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.6562500000, double -0.6562500000 } @@ -2307,6 +2767,8 @@ define dso_local { float, double } @test231() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1050 ; CHECK-NEXT: vldi $vr1, -794 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.6875000000, double -0.6875000000 } @@ -2317,6 +2779,8 @@ define dso_local { float, double } @test232() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1049 ; CHECK-NEXT: vldi $vr1, -793 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.7187500000, double -0.7187500000 } @@ -2327,6 +2791,8 @@ define dso_local { float, double } @test233() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1048 ; CHECK-NEXT: vldi $vr1, -792 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.7500000000, double -0.7500000000 } @@ -2337,6 +2803,8 @@ define dso_local { float, double } @test234() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1047 ; CHECK-NEXT: vldi $vr1, -791 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.7812500000, double -0.7812500000 } @@ -2347,6 +2815,8 @@ define dso_local { float, double } @test235() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1046 ; CHECK-NEXT: vldi $vr1, -790 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.8125000000, double -0.8125000000 } @@ -2357,6 +2827,8 @@ define dso_local { float, double } @test236() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1045 ; CHECK-NEXT: vldi $vr1, -789 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.8437500000, double -0.8437500000 } @@ -2367,6 +2839,8 @@ define dso_local { float, double } @test237() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1044 ; CHECK-NEXT: vldi $vr1, -788 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.8750000000, double -0.8750000000 } @@ -2377,6 +2851,8 @@ define dso_local { float, double } @test238() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1043 ; CHECK-NEXT: vldi $vr1, -787 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.9062500000, double -0.9062500000 } @@ -2387,6 +2863,8 @@ define dso_local { float, double } @test239() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1042 ; CHECK-NEXT: vldi $vr1, -786 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.9375000000, double -0.9375000000 } @@ -2397,6 +2875,8 @@ define dso_local { float, double } @test240() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1041 ; CHECK-NEXT: vldi $vr1, -785 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -0.9687500000, double -0.9687500000 } @@ -2407,6 +2887,8 @@ define dso_local { float, double } @test241() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1040 ; CHECK-NEXT: vldi $vr1, -784 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.0000000000, double -1.0000000000 } @@ -2417,6 +2899,8 @@ define dso_local { float, double } @test242() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1039 ; CHECK-NEXT: vldi $vr1, -783 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.0625000000, double -1.0625000000 } @@ -2427,6 +2911,8 @@ define dso_local { float, double } @test243() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1038 ; CHECK-NEXT: vldi $vr1, -782 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.1250000000, double -1.1250000000 } @@ -2437,6 +2923,8 @@ define dso_local { float, double } @test244() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1037 ; CHECK-NEXT: vldi $vr1, -781 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.1875000000, double -1.1875000000 } @@ -2447,6 +2935,8 @@ define dso_local { float, double } @test245() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1036 ; CHECK-NEXT: vldi $vr1, -780 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.2500000000, double -1.2500000000 } @@ -2457,6 +2947,8 @@ define dso_local { float, double } @test246() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1035 ; CHECK-NEXT: vldi $vr1, -779 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.3125000000, double -1.3125000000 } @@ -2467,6 +2959,8 @@ define dso_local { float, double } @test247() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1034 ; CHECK-NEXT: vldi $vr1, -778 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.3750000000, double -1.3750000000 } @@ -2477,6 +2971,8 @@ define dso_local { float, double } @test248() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1033 ; CHECK-NEXT: vldi $vr1, -777 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.4375000000, double -1.4375000000 } @@ -2487,6 +2983,8 @@ define dso_local { float, double } @test249() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1032 ; CHECK-NEXT: vldi $vr1, -776 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.5000000000, double -1.5000000000 } @@ -2497,6 +2995,8 @@ define dso_local { float, double } @test250() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1031 ; CHECK-NEXT: vldi $vr1, -775 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.5625000000, double -1.5625000000 } @@ -2507,6 +3007,8 @@ define dso_local { float, double } @test251() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1030 ; CHECK-NEXT: vldi $vr1, -774 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.6250000000, double -1.6250000000 } @@ -2517,6 +3019,8 @@ define dso_local { float, double } @test252() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1029 ; CHECK-NEXT: vldi $vr1, -773 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.6875000000, double -1.6875000000 } @@ -2527,6 +3031,8 @@ define dso_local { float, double } @test253() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1028 ; CHECK-NEXT: vldi $vr1, -772 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.7500000000, double -1.7500000000 } @@ -2537,6 +3043,8 @@ define dso_local { float, double } @test254() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1027 ; CHECK-NEXT: vldi $vr1, -771 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.8125000000, double -1.8125000000 } @@ -2547,6 +3055,8 @@ define dso_local { float, double } @test255() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1026 ; CHECK-NEXT: vldi $vr1, -770 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.8750000000, double -1.8750000000 } @@ -2557,6 +3067,8 @@ define dso_local { float, double } @test256() { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vldi $vr0, -1025 ; CHECK-NEXT: vldi $vr1, -769 +; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0 +; CHECK-NEXT: # kill: def $f1_64 killed $f1_64 killed $vr1 ; CHECK-NEXT: ret entry: ret { float, double } { float -1.9375000000, double -1.9375000000 } diff --git a/llvm/test/CodeGen/Mips/cmov.ll b/llvm/test/CodeGen/Mips/cmov.ll index bb3c7c27a122d..dcf8392b3c4f2 100644 --- a/llvm/test/CodeGen/Mips/cmov.ll +++ b/llvm/test/CodeGen/Mips/cmov.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc -mtriple=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV -; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -mtriple=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV1 +; RUN: llc -mtriple=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV2 +; RUN: llc -mtriple=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV3 ; RUN: llc -mtriple=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP -; RUN: llc -mtriple=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV -; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -mtriple=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV1 +; RUN: llc -mtriple=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV2 ; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @@ -11,10 +11,20 @@ ; ALL-LABEL: cmov1: -; 32-CMOV-DAG: lw $[[R0:[0-9]+]], %got(i3) -; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) -; 32-CMOV-DAG: movn $[[R0]], $[[R1]], $4 -; 32-CMOV-DAG: lw $2, 0($[[R0]]) +; 32-CMOV1-DAG: lw $[[R0:[0-9]+]], %got(i3) +; 32-CMOV1-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) +; 32-CMOV1-DAG: movn $[[R0]], $[[R1]], $4 +; 32-CMOV1-DAG: lw $2, 0($[[R0]]) + +; 32-CMOV2-DAG: lw $[[R0:[0-9]+]], %got(i3) +; 32-CMOV2-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) +; 32-CMOV2-DAG: movn $[[R0]], $[[R1]], $4 +; 32-CMOV2-DAG: lw $2, 0($[[R0]]) + +; 32-CMOV3-DAG: lw $[[R0:[0-9]+]], %got(i3) +; 32-CMOV3-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) +; 32-CMOV3-DAG: movn $[[R0]], $[[R1]], $4 +; 32-CMOV3-DAG: lw $2, 0($[[R0]]) ; 32-CMP-DAG: lw $[[R0:[0-9]+]], %got(i3) ; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(i1) @@ -23,9 +33,17 @@ ; 32-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]] ; 32-CMP-DAG: lw $2, 0($[[T2]]) -; 64-CMOV-DAG: ldr $[[R0:[0-9]+]] -; 64-CMOV-DAG: ld $[[R1:[0-9]+]], %got_disp(i1) -; 64-CMOV-DAG: movn $[[R0]], $[[R1]], $4 +; 64-CMOV1-DAG: ldr $[[R0:[0-9]+]] +; 64-CMOV1-DAG: ld $[[R1:[0-9]+]], %got_disp(i1) +; 64-CMOV1-DAG: movn $[[R0]], $[[R1]], $4 + +; 64-CMOV2-DAG: ldr $[[R0:[0-9]+]] +; 64-CMOV2-DAG: ld $[[R1:[0-9]+]], %got_disp(i1) +; 64-CMOV2-DAG: movn $[[R0]], $[[R1]], $4 + +; 64-CMOV3-DAG: ldr $[[R0:[0-9]+]] +; 64-CMOV3-DAG: ld $[[R1:[0-9]+]], %got_disp(i1) +; 64-CMOV3-DAG: movn $[[R0]], $[[R1]], $4 ; 64-CMP-DAG: ld $[[R0:[0-9]+]], %got_disp(i3)( ; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(i1) @@ -51,10 +69,20 @@ entry: ; ALL-LABEL: cmov2: -; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d) -; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c) -; 32-CMOV-DAG: movn $[[R1]], $[[R0]], $4 -; 32-CMOV-DAG: lw $2, 0($[[R0]]) +; 32-CMOV1-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d) +; 32-CMOV1-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c) +; 32-CMOV1-DAG: movn $[[R1]], $[[R0]], $4 +; 32-CMOV1-DAG: lw $2, 0($[[R0]]) + +; 32-CMOV2-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d) +; 32-CMOV2-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c) +; 32-CMOV2-DAG: movn $[[R1]], $[[R0]], $4 +; 32-CMOV2-DAG: lw $2, 0($[[R0]]) + +; 32-CMOV3-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d) +; 32-CMOV3-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c) +; 32-CMOV3-DAG: movn $[[R1]], $[[R0]], $4 +; 32-CMOV3-DAG: lw $2, 0($[[R0]]) ; 32-CMP-DAG: addiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got(d) ; 32-CMP-DAG: addiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got(c) @@ -63,9 +91,13 @@ entry: ; 32-CMP-DAG: or $[[T2:[0-9]+]], $[[T0]], $[[T1]] ; 32-CMP-DAG: lw $2, 0($[[T2]]) -; 64-CMOV: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d) -; 64-CMOV: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c) -; 64-CMOV: movn $[[R1]], $[[R0]], $4 +; 64-CMOV1: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d) +; 64-CMOV1: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c) +; 64-CMOV1: movn $[[R1]], $[[R0]], $4 + +; 64-CMOV2: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d) +; 64-CMOV2: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c) +; 64-CMOV2: movn $[[R1]], $[[R0]], $4 ; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d) ; 64-CMP-DAG: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c) @@ -123,9 +155,17 @@ entry: ; check that. ; FIXME: Use xori instead of addiu+xor. -; 32-CMOV: addiu $[[R0:[0-9]+]], $zero, 234 -; 32-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]] -; 32-CMOV: movn ${{[26]}}, $5, $[[R1]] +; 32-CMOV1: addiu $[[R0:[0-9]+]], $zero, 234 +; 32-CMOV1: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 32-CMOV1: movn ${{[26]}}, $5, $[[R1]] + +; 32-CMOV2: addiu $[[R0:[0-9]+]], $zero, 234 +; 32-CMOV2: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 32-CMOV2: movn ${{[26]}}, $5, $[[R1]] + +; 32-CMOV3: addiu $[[R0:[0-9]+]], $zero, 234 +; 32-CMOV3: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 32-CMOV3: movn ${{[26]}}, $5, $[[R1]] ; 32-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234 ; 32-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]] @@ -133,9 +173,13 @@ entry: ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] ; FIXME: Use xori instead of addiu+xor. -; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234 -; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]] -; 64-CMOV: movn ${{[26]}}, $5, $[[R1]] +; 64-CMOV1: addiu $[[R0:[0-9]+]], $zero, 234 +; 64-CMOV1: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 64-CMOV1: movn ${{[26]}}, $5, $[[R1]] + +; 64-CMOV2: addiu $[[R0:[0-9]+]], $zero, 234 +; 64-CMOV2: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 64-CMOV2: movn ${{[26]}}, $5, $[[R1]] ; 64-CMP-DAG: xori $[[CC:[0-9]+]], $4, 234 ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[CC]] @@ -155,11 +199,23 @@ entry: ; or last. We do know it will be one of two registers so we can at least check ; that. -; 32-CMOV-DAG: xori $[[R0:[0-9]+]], $4, 234 -; 32-CMOV-DAG: lw $[[R1:2]], 16($sp) -; 32-CMOV-DAG: lw $[[R2:3]], 20($sp) -; 32-CMOV-DAG: movz $[[R1]], $6, $[[R0]] -; 32-CMOV-DAG: movz $[[R2]], $7, $[[R0]] +; 32-CMOV1-DAG: xori $[[R0:[0-9]+]], $4, 234 +; 32-CMOV1-DAG: lw $[[R1:2]], 16($sp) +; 32-CMOV1-DAG: lw $[[R2:3]], 20($sp) +; 32-CMOV1-DAG: movz $[[R1]], $6, $[[R0]] +; 32-CMOV1-DAG: movz $[[R2]], $7, $[[R0]] + +; 32-CMOV2-DAG: xori $[[R0:[0-9]+]], $4, 234 +; 32-CMOV2-DAG: lw $[[R1:2]], 16($sp) +; 32-CMOV2-DAG: lw $[[R2:3]], 20($sp) +; 32-CMOV2-DAG: movz $[[R1]], $6, $[[R0]] +; 32-CMOV2-DAG: movz $[[R2]], $7, $[[R0]] + +; 32-CMOV3-DAG: xori $[[R0:[0-9]+]], $4, 234 +; 32-CMOV3-DAG: lw $[[R1:2]], 16($sp) +; 32-CMOV3-DAG: lw $[[R2:3]], 20($sp) +; 32-CMOV3-DAG: movz $[[R1]], $6, $[[R0]] +; 32-CMOV3-DAG: movz $[[R2]], $7, $[[R0]] ; 32-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234 ; 32-CMP-DAG: lw $[[R1:[0-9]+]], 16($sp) @@ -171,8 +227,11 @@ entry: ; 32-CMP-DAG: or $2, $[[T0]], $[[T2]] ; 32-CMP-DAG: or $3, $[[T1]], $[[T3]] -; 64-CMOV: xori $[[R0:[0-9]+]], $4, 234 -; 64-CMOV: movz ${{[26]}}, $5, $[[R0]] +; 64-CMOV1: xori $[[R0:[0-9]+]], $4, 234 +; 64-CMOV1: movz ${{[26]}}, $5, $[[R0]] + +; 64-CMOV2: xori $[[R0:[0-9]+]], $4, 234 +; 64-CMOV2: movz ${{[26]}}, $5, $[[R0]] ; 64-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234 ; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $5, $[[R0]] @@ -193,12 +252,26 @@ entry: ; that. ; FIXME: Use xori instead of addiu+xor. -; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], $zero, 234 -; 32-CMOV-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]] -; 32-CMOV-DAG: lw $[[R2:2]], 16($sp) -; 32-CMOV-DAG: lw $[[R3:3]], 20($sp) -; 32-CMOV-DAG: movn $[[R2]], $6, $[[R1]] -; 32-CMOV-DAG: movn $[[R3]], $7, $[[R1]] +; 32-CMOV1-DAG: addiu $[[R0:[0-9]+]], $zero, 234 +; 32-CMOV1-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 32-CMOV1-DAG: lw $[[R2:2]], 16($sp) +; 32-CMOV1-DAG: lw $[[R3:3]], 20($sp) +; 32-CMOV1-DAG: movn $[[R2]], $6, $[[R1]] +; 32-CMOV1-DAG: movn $[[R3]], $7, $[[R1]] + +; 32-CMOV2-DAG: addiu $[[R0:[0-9]+]], $zero, 234 +; 32-CMOV2-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 32-CMOV2-DAG: lw $[[R2:2]], 16($sp) +; 32-CMOV2-DAG: lw $[[R3:3]], 20($sp) +; 32-CMOV2-DAG: movn $[[R2]], $6, $[[R1]] +; 32-CMOV2-DAG: movn $[[R3]], $7, $[[R1]] + +; 32-CMOV3-DAG: addiu $[[R0:[0-9]+]], $zero, 234 +; 32-CMOV3-DAG: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 32-CMOV3-DAG: lw $[[R2:2]], 16($sp) +; 32-CMOV3-DAG: lw $[[R3:3]], 20($sp) +; 32-CMOV3-DAG: movn $[[R2]], $6, $[[R1]] +; 32-CMOV3-DAG: movn $[[R3]], $7, $[[R1]] ; 32-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234 ; 32-CMP-DAG: lw $[[R1:[0-9]+]], 16($sp) @@ -211,9 +284,13 @@ entry: ; 32-CMP-DAG: or $3, $[[T1]], $[[T3]] ; FIXME: Use xori instead of addiu+xor. -; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234 -; 64-CMOV: xor $[[R1:[0-9]+]], $4, $[[R0]] -; 64-CMOV: movn ${{[26]}}, $5, $[[R1]] +; 64-CMOV1: addiu $[[R0:[0-9]+]], $zero, 234 +; 64-CMOV1: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 64-CMOV1: movn ${{[26]}}, $5, $[[R1]] + +; 64-CMOV2: addiu $[[R0:[0-9]+]], $zero, 234 +; 64-CMOV2: xor $[[R1:[0-9]+]], $4, $[[R0]] +; 64-CMOV2: movn ${{[26]}}, $5, $[[R1]] ; 64-CMP-DAG: xori $[[R0:[0-9]+]], $4, 234 ; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $5, $[[R0]] @@ -237,10 +314,20 @@ entry: ; ALL-LABEL: slti0: -; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767 -; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 32-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 32-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 32-CMOV3-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -250,10 +337,15 @@ entry: ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767 -; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 64-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 64-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -272,11 +364,23 @@ entry: ; ALL-LABEL: slti1: -; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 -; 32-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 -; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 32-CMOV1-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV1-DAG: movn $[[I5]], $[[I7]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 32-CMOV2-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV2-DAG: movn $[[I5]], $[[I7]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 32-CMOV3-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV3-DAG: movn $[[I5]], $[[I7]], $[[R0]] ; 32-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -287,11 +391,17 @@ entry: ; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 -; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 -; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 64-CMOV1-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV1-DAG: movn $[[I5]], $[[I7]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 64-CMOV2-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV2-DAG: movn $[[I5]], $[[I7]], $[[R0]] ; 64-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7 ; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5 @@ -311,10 +421,20 @@ entry: ; ALL-LABEL: slti2: -; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768 -; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 32-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 32-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 32-CMOV3-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -324,10 +444,15 @@ entry: ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768 -; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 64-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 64-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -346,12 +471,26 @@ entry: ; ALL-LABEL: slti3: -; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: lui $[[R1:[0-9]+]], 65535 -; 32-CMOV-DAG: ori $[[R1]], $[[R1]], 32766 -; 32-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 -; 32-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: lui $[[R1:[0-9]+]], 65535 +; 32-CMOV1-DAG: ori $[[R1]], $[[R1]], 32766 +; 32-CMOV1-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV1-DAG: movn $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: lui $[[R1:[0-9]+]], 65535 +; 32-CMOV2-DAG: ori $[[R1]], $[[R1]], 32766 +; 32-CMOV2-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV2-DAG: movn $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: lui $[[R1:[0-9]+]], 65535 +; 32-CMOV3-DAG: ori $[[R1]], $[[R1]], 32766 +; 32-CMOV3-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV3-DAG: movn $[[I5]], $[[I3]], $[[R0]] ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -363,12 +502,19 @@ entry: ; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535 -; 64-CMOV-DAG: ori $[[R1]], $[[R1]], 32766 -; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 -; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV1-DAG: ori $[[R1]], $[[R1]], 32766 +; 64-CMOV1-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV1-DAG: movn $[[I5]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV2-DAG: ori $[[R1]], $[[R1]], 32766 +; 64-CMOV2-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV2-DAG: movn $[[I5]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5 @@ -391,32 +537,55 @@ entry: ; ALL-LABEL: slti64_0: -; 32-CMOV-DAG: slt $[[CC:[0-9]+]], $zero, $4 -; 32-CMOV-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766 -; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 -; 32-CMOV-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 -; 32-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5 -; 32-CMOV-DAG: addiu $[[I4:3]], $zero, 4 -; 32-CMOV-DAG: movn $[[I4]], $[[I5]], $[[CC]] -; 32-CMOV-DAG: addiu $2, $zero, 0 +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 0 +; 32-CMOV1-DAG: slt $[[CC:[0-9]+]], $zero, $4 +; 32-CMOV1-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766 +; 32-CMOV1-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 +; 32-CMOV1-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 +; 32-CMOV1-DAG: addiu $[[I4:3]], $zero, 4 +; 32-CMOV1-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 32-CMOV1-DAG: movn $[[I4:[0-9]+]], $[[I5]], $[[CC]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 0 +; 32-CMOV2-DAG: slt $[[CC:[0-9]+]], $zero, $4 +; 32-CMOV2-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766 +; 32-CMOV2-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 +; 32-CMOV2-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 +; 32-CMOV2-DAG: addiu $[[I4:3]], $zero, 4 +; 32-CMOV2-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 32-CMOV2-DAG: movn $[[I4:[0-9]+]], $[[I5]], $[[CC]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 0 +; 32-CMOV3-DAG: slt $[[CC:[0-9]+]], $zero, $4 +; 32-CMOV3-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766 +; 32-CMOV3-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 +; 32-CMOV3-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 +; 32-CMOV3-DAG: addiu $[[I4:3]], $zero, 4 +; 32-CMOV3-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 32-CMOV3-DAG: movn $[[I4:[0-9]+]], $[[I5]], $[[CC]] +; 32-CMP-DAG: addiu $2, $zero, 0 ; 32-CMP-DAG: slt $[[CC0:[0-9]+]], $zero, $4 +; 32-CMP-DAG: selnez $[[CC2:[0-9]+]], $[[CC0]], $4 ; 32-CMP-DAG: addiu $[[I32766:[0-9]+]], $zero, 32766 ; 32-CMP-DAG: sltu $[[CC1:[0-9]+]], $[[I32766]], $5 -; 32-CMP-DAG: selnez $[[CC2:[0-9]+]], $[[CC0]], $4 ; 32-CMP-DAG: seleqz $[[CC3:[0-9]+]], $[[CC1]], $4 ; 32-CMP: or $[[CC:[0-9]+]], $[[CC3]], $[[CC2]] -; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 ; 32-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4 ; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]] +; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]] ; 32-CMP-DAG: or $3, $[[T1]], $[[T0]] -; 32-CMP-DAG: addiu $2, $zero, 0 -; 64-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5 -; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4 -; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, 32767 -; 64-CMOV-DAG: movz $[[I4]], $[[I5]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMOV1-DAG: addiu $[[I4:2]], $zero, 4 +; 64-CMOV1-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 64-CMOV1-DAG: movz $[[I4]], $[[I5]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMOV2-DAG: addiu $[[I4:2]], $zero, 4 +; 64-CMOV2-DAG: slti $[[R0:[0-9]+]], $4, 32767 +; 64-CMOV2-DAG: movz $[[I4]], $[[I5]], $[[R0]] ; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 ; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4 @@ -436,14 +605,32 @@ entry: ; ALL-LABEL: slti64_1: -; 32-CMOV-DAG: slt $[[CC:[0-9]+]], $zero, $4 -; 32-CMOV-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767 -; 32-CMOV-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 -; 32-CMOV-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 -; 32-CMOV-DAG: addiu $[[I5:[0-9]+]], $zero, 5 -; 32-CMOV-DAG: addiu $[[I4:3]], $zero, 4 -; 32-CMOV-DAG: movn $[[I4]], $[[I5]], $[[CC]] -; 32-CMOV-DAG: addiu $2, $zero, 0 +; 32-CMOV1-DAG: slt $[[CC:[0-9]+]], $zero, $4 +; 32-CMOV1-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767 +; 32-CMOV1-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 +; 32-CMOV1-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 +; 32-CMOV1-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 32-CMOV1-DAG: addiu $[[I4:3]], $zero, 4 +; 32-CMOV1-DAG: movn $[[I4]], $[[I5]], $[[CC]] +; 32-CMOV1-DAG: addiu $2, $zero, 0 + +; 32-CMOV2-DAG: addiu $6, $zero, 0 +; 32-CMOV2-DAG: slt $[[CC:[0-9]+]], $zero, $4 +; 32-CMOV2-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767 +; 32-CMOV2-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 +; 32-CMOV2-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 +; 32-CMOV2-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 32-CMOV2-DAG: addiu $[[I4:3]], $zero, 4 +; 32-CMOV2-DAG: movn $[[I4]], $[[I5]], $[[CC]] + +; 32-CMOV3-DAG: slt $[[CC:[0-9]+]], $zero, $4 +; 32-CMOV3-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767 +; 32-CMOV3-DAG: sltu $[[R1:[0-9]+]], $[[I32766]], $5 +; 32-CMOV3-DAG: movz $[[CC:[0-9]+]], $[[R1]], $4 +; 32-CMOV3-DAG: addiu $[[I5:[0-9]+]], $zero, 5 +; 32-CMOV3-DAG: addiu $[[I4:3]], $zero, 4 +; 32-CMOV3-DAG: movn $[[I4]], $[[I5]], $[[CC]] +; 32-CMOV3-DAG: addiu $2, $zero, 0 ; 32-CMP-DAG: slt $[[CC0:[0-9]+]], $zero, $4 ; 32-CMP-DAG: addiu $[[I32766:[0-9]+]], $zero, 32767 @@ -456,13 +643,18 @@ entry: ; 32-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[CC]] ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[CC]] ; 32-CMP-DAG: or $3, $[[T1]], $[[T0]] -; 32-CMP-DAG: addiu $2, $zero, 0 -; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 -; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4 -; 64-CMOV-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767 -; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 -; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]] +; 64-CMOV1-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMOV1-DAG: daddiu $[[I4:2]], $zero, 4 +; 64-CMOV1-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767 +; 64-CMOV1-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV1-DAG: movn $[[I4]], $[[I5]], $[[R0]] + +; 64-CMOV2-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMOV2-DAG: daddiu $[[I4:2]], $zero, 4 +; 64-CMOV2-DAG: daddiu $[[R1:[0-9]+]], $zero, 32767 +; 64-CMOV2-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV2-DAG: movn $[[I4]], $[[I5]], $[[R0]] ; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 ; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4 @@ -487,10 +679,15 @@ entry: ; such as: ; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c) -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I4:2]], $zero, 4 -; 64-CMOV-DAG: slti $[[R0:[0-9]+]], $4, -32768 -; 64-CMOV-DAG: movz $[[I4]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I4:2]], $zero, 4 +; 64-CMOV1-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 64-CMOV1-DAG: movz $[[I4]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I4:2]], $zero, 4 +; 64-CMOV2-DAG: slti $[[R0:[0-9]+]], $4, -32768 +; 64-CMOV2-DAG: movz $[[I4]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I4:[0-9]+]], $zero, 4 @@ -515,14 +712,22 @@ entry: ; such as: ; (movz $a, $b, (neg $c)) -> (movn $a, $b, $c) -; 64-CMOV-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 -; 64-CMOV-DAG: daddiu $[[I4:2]], $zero, 4 +; 64-CMOV1-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMOV1-DAG: daddiu $[[I4:2]], $zero, 4 + +; 64-CMOV2-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 +; 64-CMOV2-DAG: daddiu $[[I4:2]], $zero, 4 + +; 64-CMOV1-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV1-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766 +; 64-CMOV1-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4 +; 64-CMOV1-DAG: movn $[[I4]], $[[I5]], $[[R3]] -; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535 -; 64-CMOV-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766 -; 64-CMOV-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4 -; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R3]] +; 64-CMOV2-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV2-DAG: ori $[[R2:[0-9]+]], $[[R1]], 32766 +; 64-CMOV2-DAG: slt $[[R3:[0-9]+]], $[[R2]], $4 +; 64-CMOV2-DAG: movn $[[I4]], $[[I5]], $[[R3]] ; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 ; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4 @@ -546,10 +751,20 @@ entry: ; ALL-LABEL: sltiu0: -; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 -; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 +; 32-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 +; 32-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 +; 32-CMOV3-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -559,10 +774,15 @@ entry: ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 -; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 +; 64-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: sltiu $[[R0:[0-9]+]], $4, 32767 +; 64-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -581,11 +801,23 @@ entry: ; ALL-LABEL: sltiu1: -; 32-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 -; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 -; 32-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 32-CMOV1-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV1-DAG: movn $[[I5]], $[[I7]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 32-CMOV2-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV2-DAG: movn $[[I5]], $[[I7]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 32-CMOV3-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV3-DAG: movn $[[I5]], $[[I7]], $[[R0]] ; 32-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -596,11 +828,17 @@ entry: ; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I7:[0-9]+]], $zero, 7 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 -; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 -; 64-CMOV-DAG: movn $[[I5]], $[[I7]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 64-CMOV1-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV1-DAG: movn $[[I5]], $[[I7]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I7:[0-9]+]], $zero, 7 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: addiu $[[R1:[0-9]+]], $zero, 32767 +; 64-CMOV2-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV2-DAG: movn $[[I5]], $[[I7]], $[[R0]] ; 64-CMP-DAG: addiu $[[I7:[0-9]+]], $zero, 7 ; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5 @@ -620,10 +858,20 @@ entry: ; ALL-LABEL: sltiu2: -; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 -; 32-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 +; 32-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 +; 32-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 +; 32-CMOV3-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -633,10 +881,15 @@ entry: ; 32-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 -; 64-CMOV-DAG: movz $[[I5]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 +; 64-CMOV1-DAG: movz $[[I5]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: sltiu $[[R0:[0-9]+]], $4, -32768 +; 64-CMOV2-DAG: movz $[[I5]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -655,12 +908,26 @@ entry: ; ALL-LABEL: sltiu3: -; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 32-CMOV-DAG: lui $[[R1:[0-9]+]], 65535 -; 32-CMOV-DAG: ori $[[R1]], $[[R1]], 32766 -; 32-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 -; 32-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]] +; 32-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV1-DAG: lui $[[R1:[0-9]+]], 65535 +; 32-CMOV1-DAG: ori $[[R1]], $[[R1]], 32766 +; 32-CMOV1-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV1-DAG: movn $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV2-DAG: lui $[[R1:[0-9]+]], 65535 +; 32-CMOV2-DAG: ori $[[R1]], $[[R1]], 32766 +; 32-CMOV2-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV2-DAG: movn $[[I5]], $[[I3]], $[[R0]] + +; 32-CMOV3-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 32-CMOV3-DAG: addiu $[[I5:2]], $zero, 5 +; 32-CMOV3-DAG: lui $[[R1:[0-9]+]], 65535 +; 32-CMOV3-DAG: ori $[[R1]], $[[R1]], 32766 +; 32-CMOV3-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 32-CMOV3-DAG: movn $[[I5]], $[[I3]], $[[R0]] ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5 @@ -672,12 +939,19 @@ entry: ; 32-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I5]], $[[R0]] ; 32-CMP-DAG: or $2, $[[T0]], $[[T1]] -; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3 -; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5 -; 64-CMOV-DAG: lui $[[R1:[0-9]+]], 65535 -; 64-CMOV-DAG: ori $[[R1]], $[[R1]], 32766 -; 64-CMOV-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 -; 64-CMOV-DAG: movn $[[I5]], $[[I3]], $[[R0]] +; 64-CMOV1-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV1-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV1-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV1-DAG: ori $[[R1]], $[[R1]], 32766 +; 64-CMOV1-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV1-DAG: movn $[[I5]], $[[I3]], $[[R0]] + +; 64-CMOV2-DAG: addiu $[[I3:[0-9]+]], $zero, 3 +; 64-CMOV2-DAG: addiu $[[I5:2]], $zero, 5 +; 64-CMOV2-DAG: lui $[[R1:[0-9]+]], 65535 +; 64-CMOV2-DAG: ori $[[R1]], $[[R1]], 32766 +; 64-CMOV2-DAG: sltu $[[R0:[0-9]+]], $[[R1]], $4 +; 64-CMOV2-DAG: movn $[[I5]], $[[I3]], $[[R0]] ; 64-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3 ; 64-CMP-DAG: addiu $[[I5:2]], $zero, 5 @@ -710,18 +984,30 @@ define i32 @slti4(i32 signext %a) nounwind readnone { ; ALL-LABEL: slti4: -; 32-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 32-CMOV-DAG: addiu $2, [[R1]], 3 -; 32-CMOV-NOT: movn +; 32-CMOV1-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 32-CMOV1-DAG: addiu $2, [[R1]], 3 +; 32-CMOV1-NOT: movn + +; 32-CMOV2-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 32-CMOV2-DAG: addiu $2, [[R1]], 3 +; 32-CMOV2-NOT: movn + +; 32-CMOV3-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 32-CMOV3-DAG: addiu $2, [[R1]], 3 +; 32-CMOV3-NOT: movn ; 32-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7 ; 32-CMP-DAG: addiu $2, [[R1]], 3 ; 32-CMP-NOT: seleqz ; 32-CMP-NOT: selnez -; 64-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 64-CMOV-DAG: addiu $2, [[R1]], 3 -; 64-CMOV-NOT: movn +; 64-CMOV1-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 64-CMOV1-DAG: addiu $2, [[R1]], 3 +; 64-CMOV1-NOT: movn + +; 64-CMOV2-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 64-CMOV2-DAG: addiu $2, [[R1]], 3 +; 64-CMOV2-NOT: movn ; 64-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7 ; 64-CMP-DAG: addiu $2, [[R1]], 3 @@ -736,18 +1022,30 @@ define i32 @slti5(i32 signext %a) nounwind readnone { ; ALL-LABEL: slti5: -; 32-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 32-CMOV-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 -; 32-CMOV-NOT: movn +; 32-CMOV1-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 32-CMOV1-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 +; 32-CMOV1-NOT: movn + +; 32-CMOV2-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 32-CMOV2-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 +; 32-CMOV2-NOT: movn + +; 32-CMOV3-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 32-CMOV3-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 +; 32-CMOV3-NOT: movn ; 32-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7 ; 32-CMP-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 ; 32-CMP-NOT: seleqz ; 32-CMP-NOT: selnez -; 64-CMOV-DAG: slti [[R1:\$[0-9]+]], $4, 7 -; 64-CMOV-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 -; 64-CMOV-NOT: movn +; 64-CMOV1-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 64-CMOV1-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 +; 64-CMOV1-NOT: movn + +; 64-CMOV2-DAG: slti [[R1:\$[0-9]+]], $4, 7 +; 64-CMOV2-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 +; 64-CMOV2-NOT: movn ; 64-CMP-DAG: slti [[R1:\$[0-9]+]], $4, 7 ; 64-CMP-DAG: addiu [[R3:\$[0-9]+]], [[R2:\$[a-z0-9]+]], -4 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/and.ll b/llvm/test/CodeGen/Mips/llvm-ir/and.ll index 87f7edb2b7132..9df803c52d19f 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/and.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/and.ll @@ -591,26 +591,26 @@ define signext i128 @and_i128_4(i128 signext %b) { ; MIPS-LABEL: and_i128_4: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: andi $5, $7, 4 -; MIPS-NEXT: addiu $2, $zero, 0 -; MIPS-NEXT: addiu $3, $zero, 0 -; MIPS-NEXT: jr $ra ; MIPS-NEXT: addiu $4, $zero, 0 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $3, $4 ; ; MIPS32R2-LABEL: and_i128_4: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: andi $5, $7, 4 -; MIPS32R2-NEXT: addiu $2, $zero, 0 -; MIPS32R2-NEXT: addiu $3, $zero, 0 -; MIPS32R2-NEXT: jr $ra ; MIPS32R2-NEXT: addiu $4, $zero, 0 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $3, $4 ; ; MIPS32R6-LABEL: and_i128_4: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: andi $5, $7, 4 -; MIPS32R6-NEXT: addiu $2, $zero, 0 -; MIPS32R6-NEXT: addiu $3, $zero, 0 -; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: addiu $4, $zero, 0 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $3, $4 ; ; MIPS64-LABEL: and_i128_4: ; MIPS64: # %bb.0: # %entry @@ -633,17 +633,17 @@ define signext i128 @and_i128_4(i128 signext %b) { ; MM32R3-LABEL: and_i128_4: ; MM32R3: # %bb.0: # %entry ; MM32R3-NEXT: andi16 $5, $7, 4 -; MM32R3-NEXT: li16 $2, 0 -; MM32R3-NEXT: li16 $3, 0 ; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $4 ; MM32R3-NEXT: jrc $ra ; ; MM32R6-LABEL: and_i128_4: ; MM32R6: # %bb.0: # %entry ; MM32R6-NEXT: andi16 $5, $7, 4 -; MM32R6-NEXT: li16 $2, 0 -; MM32R6-NEXT: li16 $3, 0 ; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $4 ; MM32R6-NEXT: jrc $ra entry: %r = and i128 4, %b @@ -884,26 +884,26 @@ define signext i128 @and_i128_31(i128 signext %b) { ; MIPS-LABEL: and_i128_31: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: andi $5, $7, 31 -; MIPS-NEXT: addiu $2, $zero, 0 -; MIPS-NEXT: addiu $3, $zero, 0 -; MIPS-NEXT: jr $ra ; MIPS-NEXT: addiu $4, $zero, 0 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $3, $4 ; ; MIPS32R2-LABEL: and_i128_31: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: andi $5, $7, 31 -; MIPS32R2-NEXT: addiu $2, $zero, 0 -; MIPS32R2-NEXT: addiu $3, $zero, 0 -; MIPS32R2-NEXT: jr $ra ; MIPS32R2-NEXT: addiu $4, $zero, 0 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $3, $4 ; ; MIPS32R6-LABEL: and_i128_31: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: andi $5, $7, 31 -; MIPS32R6-NEXT: addiu $2, $zero, 0 -; MIPS32R6-NEXT: addiu $3, $zero, 0 -; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: addiu $4, $zero, 0 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $3, $4 ; ; MIPS64-LABEL: and_i128_31: ; MIPS64: # %bb.0: # %entry @@ -926,17 +926,17 @@ define signext i128 @and_i128_31(i128 signext %b) { ; MM32R3-LABEL: and_i128_31: ; MM32R3: # %bb.0: # %entry ; MM32R3-NEXT: andi16 $5, $7, 31 -; MM32R3-NEXT: li16 $2, 0 -; MM32R3-NEXT: li16 $3, 0 ; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $4 ; MM32R3-NEXT: jrc $ra ; ; MM32R6-LABEL: and_i128_31: ; MM32R6: # %bb.0: # %entry ; MM32R6-NEXT: andi16 $5, $7, 31 -; MM32R6-NEXT: li16 $2, 0 -; MM32R6-NEXT: li16 $3, 0 ; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $4 ; MM32R6-NEXT: jrc $ra entry: %r = and i128 31, %b @@ -1177,26 +1177,26 @@ define signext i128 @and_i128_255(i128 signext %b) { ; MIPS-LABEL: and_i128_255: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: andi $5, $7, 255 -; MIPS-NEXT: addiu $2, $zero, 0 -; MIPS-NEXT: addiu $3, $zero, 0 -; MIPS-NEXT: jr $ra ; MIPS-NEXT: addiu $4, $zero, 0 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $3, $4 ; ; MIPS32R2-LABEL: and_i128_255: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: andi $5, $7, 255 -; MIPS32R2-NEXT: addiu $2, $zero, 0 -; MIPS32R2-NEXT: addiu $3, $zero, 0 -; MIPS32R2-NEXT: jr $ra ; MIPS32R2-NEXT: addiu $4, $zero, 0 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $3, $4 ; ; MIPS32R6-LABEL: and_i128_255: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: andi $5, $7, 255 -; MIPS32R6-NEXT: addiu $2, $zero, 0 -; MIPS32R6-NEXT: addiu $3, $zero, 0 -; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: addiu $4, $zero, 0 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $3, $4 ; ; MIPS64-LABEL: and_i128_255: ; MIPS64: # %bb.0: # %entry @@ -1219,17 +1219,17 @@ define signext i128 @and_i128_255(i128 signext %b) { ; MM32R3-LABEL: and_i128_255: ; MM32R3: # %bb.0: # %entry ; MM32R3-NEXT: andi16 $5, $7, 255 -; MM32R3-NEXT: li16 $2, 0 -; MM32R3-NEXT: li16 $3, 0 ; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $4 ; MM32R3-NEXT: jrc $ra ; ; MM32R6-LABEL: and_i128_255: ; MM32R6: # %bb.0: # %entry ; MM32R6-NEXT: andi16 $5, $7, 255 -; MM32R6-NEXT: li16 $2, 0 -; MM32R6-NEXT: li16 $3, 0 ; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $4 ; MM32R6-NEXT: jrc $ra entry: %r = and i128 255, %b @@ -1479,26 +1479,26 @@ define signext i128 @and_i128_32768(i128 signext %b) { ; MIPS-LABEL: and_i128_32768: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: andi $5, $7, 32768 -; MIPS-NEXT: addiu $2, $zero, 0 -; MIPS-NEXT: addiu $3, $zero, 0 -; MIPS-NEXT: jr $ra ; MIPS-NEXT: addiu $4, $zero, 0 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $3, $4 ; ; MIPS32R2-LABEL: and_i128_32768: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: andi $5, $7, 32768 -; MIPS32R2-NEXT: addiu $2, $zero, 0 -; MIPS32R2-NEXT: addiu $3, $zero, 0 -; MIPS32R2-NEXT: jr $ra ; MIPS32R2-NEXT: addiu $4, $zero, 0 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $3, $4 ; ; MIPS32R6-LABEL: and_i128_32768: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: andi $5, $7, 32768 -; MIPS32R6-NEXT: addiu $2, $zero, 0 -; MIPS32R6-NEXT: addiu $3, $zero, 0 -; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: addiu $4, $zero, 0 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $3, $4 ; ; MIPS64-LABEL: and_i128_32768: ; MIPS64: # %bb.0: # %entry @@ -1521,17 +1521,17 @@ define signext i128 @and_i128_32768(i128 signext %b) { ; MM32R3-LABEL: and_i128_32768: ; MM32R3: # %bb.0: # %entry ; MM32R3-NEXT: andi16 $5, $7, 32768 -; MM32R3-NEXT: li16 $2, 0 -; MM32R3-NEXT: li16 $3, 0 ; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $4 ; MM32R3-NEXT: jrc $ra ; ; MM32R6-LABEL: and_i128_32768: ; MM32R6: # %bb.0: # %entry ; MM32R6-NEXT: andi16 $5, $7, 32768 -; MM32R6-NEXT: li16 $2, 0 -; MM32R6-NEXT: li16 $3, 0 ; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $4 ; MM32R6-NEXT: jrc $ra entry: %r = and i128 32768, %b @@ -1772,26 +1772,26 @@ define signext i128 @and_i128_65(i128 signext %b) { ; MIPS-LABEL: and_i128_65: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: andi $5, $7, 65 -; MIPS-NEXT: addiu $2, $zero, 0 -; MIPS-NEXT: addiu $3, $zero, 0 -; MIPS-NEXT: jr $ra ; MIPS-NEXT: addiu $4, $zero, 0 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $3, $4 ; ; MIPS32R2-LABEL: and_i128_65: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: andi $5, $7, 65 -; MIPS32R2-NEXT: addiu $2, $zero, 0 -; MIPS32R2-NEXT: addiu $3, $zero, 0 -; MIPS32R2-NEXT: jr $ra ; MIPS32R2-NEXT: addiu $4, $zero, 0 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $3, $4 ; ; MIPS32R6-LABEL: and_i128_65: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: andi $5, $7, 65 -; MIPS32R6-NEXT: addiu $2, $zero, 0 -; MIPS32R6-NEXT: addiu $3, $zero, 0 -; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: addiu $4, $zero, 0 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $3, $4 ; ; MIPS64-LABEL: and_i128_65: ; MIPS64: # %bb.0: # %entry @@ -1813,18 +1813,18 @@ define signext i128 @and_i128_65(i128 signext %b) { ; ; MM32R3-LABEL: and_i128_65: ; MM32R3: # %bb.0: # %entry -; MM32R3-NEXT: li16 $2, 0 -; MM32R3-NEXT: li16 $3, 0 -; MM32R3-NEXT: li16 $4, 0 -; MM32R3-NEXT: jr $ra ; MM32R3-NEXT: andi $5, $7, 65 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $4 +; MM32R3-NEXT: jrc $ra ; ; MM32R6-LABEL: and_i128_65: ; MM32R6: # %bb.0: # %entry ; MM32R6-NEXT: andi $5, $7, 65 -; MM32R6-NEXT: li16 $2, 0 -; MM32R6-NEXT: li16 $3, 0 ; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $4 ; MM32R6-NEXT: jrc $ra entry: %r = and i128 65, %b @@ -2065,26 +2065,26 @@ define signext i128 @and_i128_256(i128 signext %b) { ; MIPS-LABEL: and_i128_256: ; MIPS: # %bb.0: # %entry ; MIPS-NEXT: andi $5, $7, 256 -; MIPS-NEXT: addiu $2, $zero, 0 -; MIPS-NEXT: addiu $3, $zero, 0 -; MIPS-NEXT: jr $ra ; MIPS-NEXT: addiu $4, $zero, 0 +; MIPS-NEXT: move $2, $4 +; MIPS-NEXT: jr $ra +; MIPS-NEXT: move $3, $4 ; ; MIPS32R2-LABEL: and_i128_256: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: andi $5, $7, 256 -; MIPS32R2-NEXT: addiu $2, $zero, 0 -; MIPS32R2-NEXT: addiu $3, $zero, 0 -; MIPS32R2-NEXT: jr $ra ; MIPS32R2-NEXT: addiu $4, $zero, 0 +; MIPS32R2-NEXT: move $2, $4 +; MIPS32R2-NEXT: jr $ra +; MIPS32R2-NEXT: move $3, $4 ; ; MIPS32R6-LABEL: and_i128_256: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: andi $5, $7, 256 -; MIPS32R6-NEXT: addiu $2, $zero, 0 -; MIPS32R6-NEXT: addiu $3, $zero, 0 -; MIPS32R6-NEXT: jr $ra ; MIPS32R6-NEXT: addiu $4, $zero, 0 +; MIPS32R6-NEXT: move $2, $4 +; MIPS32R6-NEXT: jr $ra +; MIPS32R6-NEXT: move $3, $4 ; ; MIPS64-LABEL: and_i128_256: ; MIPS64: # %bb.0: # %entry @@ -2106,18 +2106,18 @@ define signext i128 @and_i128_256(i128 signext %b) { ; ; MM32R3-LABEL: and_i128_256: ; MM32R3: # %bb.0: # %entry -; MM32R3-NEXT: li16 $2, 0 -; MM32R3-NEXT: li16 $3, 0 -; MM32R3-NEXT: li16 $4, 0 -; MM32R3-NEXT: jr $ra ; MM32R3-NEXT: andi $5, $7, 256 +; MM32R3-NEXT: li16 $4, 0 +; MM32R3-NEXT: move $2, $4 +; MM32R3-NEXT: move $3, $4 +; MM32R3-NEXT: jrc $ra ; ; MM32R6-LABEL: and_i128_256: ; MM32R6: # %bb.0: # %entry ; MM32R6-NEXT: andi $5, $7, 256 -; MM32R6-NEXT: li16 $2, 0 -; MM32R6-NEXT: li16 $3, 0 ; MM32R6-NEXT: li16 $4, 0 +; MM32R6-NEXT: move $2, $4 +; MM32R6-NEXT: move $3, $4 ; MM32R6-NEXT: jrc $ra entry: %r = and i128 256, %b diff --git a/llvm/test/CodeGen/Mips/mips64-f128.ll b/llvm/test/CodeGen/Mips/mips64-f128.ll index 04bed7d42bf96..10e4d464a5ae0 100644 --- a/llvm/test/CodeGen/Mips/mips64-f128.ll +++ b/llvm/test/CodeGen/Mips/mips64-f128.ll @@ -2938,8 +2938,8 @@ define fp128 @call_structure_without_fp128() nounwind { ; C_CC_FMT-NEXT: .Ltmp51: ; C_CC_FMT-NEXT: jalr $25 ; C_CC_FMT-NEXT: nop -; C_CC_FMT-NEXT: daddiu $2, $zero, 0 ; C_CC_FMT-NEXT: daddiu $4, $zero, 0 +; C_CC_FMT-NEXT: move $2, $4 ; C_CC_FMT-NEXT: ld $gp, 32($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: daddiu $sp, $sp, 48 @@ -2959,8 +2959,8 @@ define fp128 @call_structure_without_fp128() nounwind { ; CMP_CC_FMT-NEXT: .reloc .Ltmp51, R_MIPS_JALR, bar_structure_without_fp128 ; CMP_CC_FMT-NEXT: .Ltmp51: ; CMP_CC_FMT-NEXT: jalrc $25 -; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0 ; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0 +; CMP_CC_FMT-NEXT: move $2, $4 ; CMP_CC_FMT-NEXT: ld $gp, 32($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 48 @@ -2973,15 +2973,15 @@ entry: define { fp128 } @bar_structure_fp128() nounwind { ; C_CC_FMT-LABEL: bar_structure_fp128: ; C_CC_FMT: # %bb.0: # %entry -; C_CC_FMT-NEXT: daddiu $2, $zero, 0 ; C_CC_FMT-NEXT: daddiu $4, $zero, 0 +; C_CC_FMT-NEXT: move $2, $4 ; C_CC_FMT-NEXT: jr $ra ; C_CC_FMT-NEXT: nop ; ; CMP_CC_FMT-LABEL: bar_structure_fp128: ; CMP_CC_FMT: # %bb.0: # %entry -; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0 ; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0 +; CMP_CC_FMT-NEXT: move $2, $4 ; CMP_CC_FMT-NEXT: jrc $ra entry: ret { fp128 } zeroinitializer @@ -3001,8 +3001,8 @@ define fp128 @tail_call_structure_fp128() nounwind { ; C_CC_FMT-NEXT: .Ltmp52: ; C_CC_FMT-NEXT: jalr $25 ; C_CC_FMT-NEXT: nop -; C_CC_FMT-NEXT: daddiu $2, $zero, 0 ; C_CC_FMT-NEXT: daddiu $4, $zero, 0 +; C_CC_FMT-NEXT: move $2, $4 ; C_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: daddiu $sp, $sp, 16 @@ -3021,8 +3021,8 @@ define fp128 @tail_call_structure_fp128() nounwind { ; CMP_CC_FMT-NEXT: .reloc .Ltmp52, R_MIPS_JALR, bar_structure_fp128 ; CMP_CC_FMT-NEXT: .Ltmp52: ; CMP_CC_FMT-NEXT: jalrc $25 -; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0 ; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0 +; CMP_CC_FMT-NEXT: move $2, $4 ; CMP_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 16 @@ -3035,15 +3035,15 @@ entry: define fp128 @bar_fp128() nounwind { ; C_CC_FMT-LABEL: bar_fp128: ; C_CC_FMT: # %bb.0: # %entry -; C_CC_FMT-NEXT: daddiu $2, $zero, 0 ; C_CC_FMT-NEXT: daddiu $4, $zero, 0 +; C_CC_FMT-NEXT: move $2, $4 ; C_CC_FMT-NEXT: jr $ra ; C_CC_FMT-NEXT: nop ; ; CMP_CC_FMT-LABEL: bar_fp128: ; CMP_CC_FMT: # %bb.0: # %entry -; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0 ; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0 +; CMP_CC_FMT-NEXT: move $2, $4 ; CMP_CC_FMT-NEXT: jrc $ra entry: ret fp128 zeroinitializer @@ -3063,8 +3063,8 @@ define fp128 @call_fp128() nounwind { ; C_CC_FMT-NEXT: .Ltmp53: ; C_CC_FMT-NEXT: jalr $25 ; C_CC_FMT-NEXT: nop -; C_CC_FMT-NEXT: daddiu $2, $zero, 0 ; C_CC_FMT-NEXT: daddiu $4, $zero, 0 +; C_CC_FMT-NEXT: move $2, $4 ; C_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: daddiu $sp, $sp, 16 @@ -3083,8 +3083,8 @@ define fp128 @call_fp128() nounwind { ; CMP_CC_FMT-NEXT: .reloc .Ltmp53, R_MIPS_JALR, bar_fp128 ; CMP_CC_FMT-NEXT: .Ltmp53: ; CMP_CC_FMT-NEXT: jalrc $25 -; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0 ; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0 +; CMP_CC_FMT-NEXT: move $2, $4 ; CMP_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 16 @@ -3108,8 +3108,8 @@ define fp128 @call_structure_fp128() nounwind { ; C_CC_FMT-NEXT: .Ltmp54: ; C_CC_FMT-NEXT: jalr $25 ; C_CC_FMT-NEXT: nop -; C_CC_FMT-NEXT: daddiu $2, $zero, 0 ; C_CC_FMT-NEXT: daddiu $4, $zero, 0 +; C_CC_FMT-NEXT: move $2, $4 ; C_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload ; C_CC_FMT-NEXT: daddiu $sp, $sp, 16 @@ -3128,8 +3128,8 @@ define fp128 @call_structure_fp128() nounwind { ; CMP_CC_FMT-NEXT: .reloc .Ltmp54, R_MIPS_JALR, bar_structure_fp128 ; CMP_CC_FMT-NEXT: .Ltmp54: ; CMP_CC_FMT-NEXT: jalrc $25 -; CMP_CC_FMT-NEXT: daddiu $2, $zero, 0 ; CMP_CC_FMT-NEXT: daddiu $4, $zero, 0 +; CMP_CC_FMT-NEXT: move $2, $4 ; CMP_CC_FMT-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload ; CMP_CC_FMT-NEXT: daddiu $sp, $sp, 16 diff --git a/llvm/test/CodeGen/Mips/readcyclecounter.ll b/llvm/test/CodeGen/Mips/readcyclecounter.ll index 467dd92884b3d..ce7e32ff96261 100644 --- a/llvm/test/CodeGen/Mips/readcyclecounter.ll +++ b/llvm/test/CodeGen/Mips/readcyclecounter.ll @@ -23,7 +23,7 @@ define i64 @test_readcyclecounter() nounwind { ; MIPSEL_NOT_SUPPORTED: # %bb.0: # %entry ; MIPSEL_NOT_SUPPORTED-NEXT: addiu $2, $zero, 0 ; MIPSEL_NOT_SUPPORTED-NEXT: jr $ra -; MIPSEL_NOT_SUPPORTED-NEXT: addiu $3, $zero, 0 +; MIPSEL_NOT_SUPPORTED-NEXT: move $3, $2 ; ; MIPS64EL-LABEL: test_readcyclecounter: ; MIPS64EL: # %bb.0: # %entry diff --git a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll index a14ef4f93c701..ac6f1504199a6 100644 --- a/llvm/test/CodeGen/PowerPC/aix-dwarf.ll +++ b/llvm/test/CodeGen/PowerPC/aix-dwarf.ll @@ -46,7 +46,8 @@ entry: ; SEC-NEXT: Name: .text ; SEC-NEXT: PhysicalAddress: 0x0 ; SEC-NEXT: VirtualAddress: 0x0 -; SEC-NEXT: Size: 0x28 +; SEC32-NEXT: Size: 0x24 +; SEC64-NEXT: Size: 0x24 ; SEC32-NEXT: RawDataOffset: 0xDC ; SEC64-NEXT: RawDataOffset: 0x180 ; SEC-NEXT: RelocationPointer: 0x0 @@ -58,14 +59,16 @@ entry: ; SEC-NEXT: Section { ; SEC-NEXT: Index: 2 ; SEC-NEXT: Name: .data -; SEC-NEXT: PhysicalAddress: 0x28 -; SEC-NEXT: VirtualAddress: 0x28 +; SEC32-NEXT: PhysicalAddress: 0x24 +; SEC64-NEXT: PhysicalAddress: 0x28 +; SEC32-NEXT: VirtualAddress: 0x24 +; SEC64-NEXT: VirtualAddress: 0x28 ; SEC32-NEXT: Size: 0xC -; SEC32-NEXT: RawDataOffset: 0x104 +; SEC32-NEXT: RawDataOffset: 0x100 ; SEC32-NEXT: RelocationPointer: 0x1F4 ; SEC64-NEXT: Size: 0x18 -; SEC64-NEXT: RawDataOffset: 0x1A8 -; SEC64-NEXT: RelocationPointer: 0x2C8 +; SEC64-NEXT: RawDataOffset: 0x1A4 +; SEC64-NEXT: RelocationPointer: 0x2C4 ; SEC-NEXT: LineNumberPointer: 0x0 ; SEC-NEXT: NumberOfRelocations: 2 ; SEC-NEXT: NumberOfLineNumbers: 0 @@ -78,7 +81,7 @@ entry: ; SEC-NEXT: VirtualAddress: 0x0 ; SEC-NEXT: Size: 0x36 ; SEC32-NEXT: RawDataOffset: 0x11C -; SEC64-NEXT: RawDataOffset: 0x1C0 +; SEC64-NEXT: RawDataOffset: 0x1BC ; SEC-NEXT: RelocationPointer: 0x0 ; SEC-NEXT: LineNumberPointer: 0x0 ; SEC-NEXT: NumberOfRelocations: 0 @@ -95,8 +98,8 @@ entry: ; SEC32-NEXT: RawDataOffset: 0x15C ; SEC32-NEXT: RelocationPointer: 0x208 ; SEC64-NEXT: Size: 0x6F -; SEC64-NEXT: RawDataOffset: 0x200 -; SEC64-NEXT: RelocationPointer: 0x2E4 +; SEC64-NEXT: RawDataOffset: 0x1FC +; SEC64-NEXT: RelocationPointer: 0x2E0 ; SEC-NEXT: LineNumberPointer: 0x0 ; SEC-NEXT: NumberOfRelocations: 4 ; SEC-NEXT: NumberOfLineNumbers: 0 @@ -112,8 +115,8 @@ entry: ; SEC32-NEXT: RawDataOffset: 0x1BC ; SEC32-NEXT: RelocationPointer: 0x230 ; SEC64-NEXT: Size: 0x46 -; SEC64-NEXT: RawDataOffset: 0x280 -; SEC64-NEXT: RelocationPointer: 0x31C +; SEC64-NEXT: RawDataOffset: 0x27C +; SEC64-NEXT: RelocationPointer: 0x318 ; SEC-NEXT: LineNumberPointer: 0x0 ; SEC-NEXT: NumberOfRelocations: 1 ; SEC-NEXT: NumberOfLineNumbers: 0 @@ -125,12 +128,12 @@ entry: ; RELO: RELOCATION RECORDS FOR [.dwinfo]: ; RELO-NEXT: OFFSET TYPE VALUE ; RELO-NEXT: 00000006 R_POS .dwabrev -; RELO-NEXT: 00000027 R_POS .dwline -; RELO-NEXT: 00000009 R_POS +; RELO-NEXT: 00000003 R_POS .dwline +; RELO-NEXT: 00000031 R_POS ; RELO-NEXT: 0000003a R_POS ; RELO: RELOCATION RECORDS FOR [.dwline]: ; RELO-NEXT: OFFSET TYPE VALUE -; RELO-NEXT: 00000000 R_POS +; RELO-NEXT: 00000004 R_POS ; RELO64: RELOCATION RECORDS FOR [.dwinfo]: ; RELO64-NEXT: OFFSET TYPE VALUE diff --git a/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll b/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll index 21d880ec47534..8bbbb7a04ec92 100644 --- a/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll +++ b/llvm/test/CodeGen/PowerPC/llc_default_cpu.ll @@ -32,9 +32,8 @@ entry: ; LNX-COM-NEXT: .cfi_offset r31, -8 ; LNX-COM-NEXT: mr 31, 1 ; LNX-COM-NEXT: .cfi_def_cfa_register r31 -; LNX-COM-NEXT: li 4, 0 ; LNX-COM-NEXT: li 3, 0 -; LNX-COM-NEXT: stw 4, 60(31) +; LNX-COM-NEXT: stw 3, 60(31) ; LNX-COM-NEXT: ld 1, 0(1) ; LNX-COM-NEXT: ld 31, -8(1) ; LNX-COM-NEXT: blr @@ -47,9 +46,8 @@ entry: ; AIX-COM-NEXT: lis 0, -1 ; AIX-COM-NEXT: ori 0, 0, 32736 ; AIX-COM-NEXT: stwux 1, 1, 0 -; AIX-PPC-NEXT: li 4, 0 ; AIX-COM-NEXT: li 3, 0 -; AIX-PPC-NEXT: stw 4, 36(1) +; AIX-PPC-NEXT: stw 3, 36(1) ; AIX-PWR7-NEXT: stw 3, 36(1) ; AIX-COM-NEXT: lwz 1, 0(1) ; AIX-COM-NEXT: blr @@ -59,9 +57,8 @@ entry: ; AIX64-COM-NEXT: lis 0, -1 ; AIX64-COM-NEXT: ori 0, 0, 32720 ; AIX64-COM-NEXT: stdux 1, 1, 0 -; AIX64-PPC-NEXT: li 4, 0 ; AIX64-COM-NEXT: li 3, 0 -; AIX64-PPC-NEXT: stw 4, 52(1) +; AIX64-PPC-NEXT: stw 3, 52(1) ; AIX64-PWR7-NEXT: stw 3, 52(1) ; AIX64-COM-NEXT: ld 1, 0(1) ; AIX64-COM-NEXT: blr diff --git a/llvm/test/CodeGen/PowerPC/register-pressure.ll b/llvm/test/CodeGen/PowerPC/register-pressure.ll index 40ee849c6c2b3..7d8eac30aee8b 100644 --- a/llvm/test/CodeGen/PowerPC/register-pressure.ll +++ b/llvm/test/CodeGen/PowerPC/register-pressure.ll @@ -12,41 +12,44 @@ define dso_local i32 @main() #0 { ; CHECK-LABEL: main: ; CHECK: # %bb.0: ; CHECK-NEXT: mflr 0 -; CHECK-NEXT: stwu 1, -48(1) -; CHECK-NEXT: stw 31, 44(1) -; CHECK-NEXT: stw 0, 52(1) -; CHECK-NEXT: .cfi_def_cfa_offset 48 +; CHECK-NEXT: stwu 1, -64(1) +; CHECK-NEXT: stw 31, 60(1) +; CHECK-NEXT: stw 0, 68(1) +; CHECK-NEXT: .cfi_def_cfa_offset 64 ; CHECK-NEXT: .cfi_offset r31, -4 ; CHECK-NEXT: .cfi_offset lr, 4 ; CHECK-NEXT: mr 31, 1 ; CHECK-NEXT: .cfi_def_cfa_register r31 +; CHECK-NEXT: .cfi_offset r30, -8 +; CHECK-NEXT: stw 30, 56(31) # 4-byte Folded Spill ; CHECK-NEXT: li 3, 10 -; CHECK-NEXT: stw 3, 40(31) -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: stw 3, 28(31) -; CHECK-NEXT: lis 4, 16404 -; CHECK-NEXT: stw 4, 24(31) -; CHECK-NEXT: stw 3, 36(31) -; CHECK-NEXT: lis 3, 16420 +; CHECK-NEXT: stw 3, 52(31) +; CHECK-NEXT: li 30, 0 +; CHECK-NEXT: stw 30, 36(31) +; CHECK-NEXT: lis 3, 16404 ; CHECK-NEXT: stw 3, 32(31) -; CHECK-NEXT: lwz 3, 40(31) +; CHECK-NEXT: stw 30, 44(31) +; CHECK-NEXT: lis 3, 16420 +; CHECK-NEXT: stw 3, 40(31) +; CHECK-NEXT: lwz 3, 52(31) ; CHECK-NEXT: slwi 3, 3, 4 ; CHECK-NEXT: bl malloc +; CHECK-NEXT: stw 3, 28(31) +; CHECK-NEXT: addi 7, 31, 32 +; CHECK-NEXT: stw 7, 24(31) +; CHECK-NEXT: lwz 3, 28(31) ; CHECK-NEXT: stw 3, 20(31) -; CHECK-NEXT: addi 7, 31, 24 -; CHECK-NEXT: stw 7, 16(31) -; CHECK-NEXT: lwz 3, 20(31) -; CHECK-NEXT: stw 3, 12(31) -; CHECK-NEXT: lwz 5, 16(31) -; CHECK-NEXT: lwz 6, 12(31) +; CHECK-NEXT: lwz 5, 24(31) +; CHECK-NEXT: lwz 6, 20(31) ; CHECK-NEXT: li 3, 5 ; CHECK-NEXT: li 4, 1 ; CHECK-NEXT: li 8, 1 ; CHECK-NEXT: bl pass11 -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: lwz 0, 52(1) -; CHECK-NEXT: lwz 31, 44(1) -; CHECK-NEXT: addi 1, 1, 48 +; CHECK-NEXT: mr 3, 30 +; CHECK-NEXT: lwz 30, 56(31) # 4-byte Folded Reload +; CHECK-NEXT: lwz 0, 68(1) +; CHECK-NEXT: lwz 31, 60(1) +; CHECK-NEXT: addi 1, 1, 64 ; CHECK-NEXT: mtlr 0 ; CHECK-NEXT: blr %1 = alloca i32, align 4 diff --git a/llvm/test/CodeGen/RISCV/float-imm.ll b/llvm/test/CodeGen/RISCV/float-imm.ll index 610c72b5f932e..f06acc0a3aa01 100644 --- a/llvm/test/CodeGen/RISCV/float-imm.ll +++ b/llvm/test/CodeGen/RISCV/float-imm.ll @@ -65,6 +65,7 @@ define float @float_negative_zero(ptr %pf) nounwind { ; CHECKZFINX-LABEL: float_negative_zero: ; CHECKZFINX: # %bb.0: ; CHECKZFINX-NEXT: lui a0, 524288 +; CHECKZFINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10 ; CHECKZFINX-NEXT: ret ret float -0.0 } diff --git a/llvm/test/CodeGen/RISCV/half-imm.ll b/llvm/test/CodeGen/RISCV/half-imm.ll index ec1a7a4dfc4f0..f92efa17b460e 100644 --- a/llvm/test/CodeGen/RISCV/half-imm.ll +++ b/llvm/test/CodeGen/RISCV/half-imm.ll @@ -120,6 +120,7 @@ define half @half_negative_zero(ptr %pf) nounwind { ; CHECKIZHINX-LABEL: half_negative_zero: ; CHECKIZHINX: # %bb.0: ; CHECKIZHINX-NEXT: lui a0, 1048568 +; CHECKIZHINX-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; CHECKIZHINX-NEXT: ret ; ; CHECKIZFHMIN-LABEL: half_negative_zero: @@ -131,6 +132,7 @@ define half @half_negative_zero(ptr %pf) nounwind { ; CHECKIZHINXMIN-LABEL: half_negative_zero: ; CHECKIZHINXMIN: # %bb.0: ; CHECKIZHINXMIN-NEXT: lui a0, 1048568 +; CHECKIZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; CHECKIZHINXMIN-NEXT: ret ret half -0.0 } diff --git a/llvm/test/CodeGen/RISCV/ret-remat.ll b/llvm/test/CodeGen/RISCV/ret-remat.ll new file mode 100644 index 0000000000000..c4381e235bbfd --- /dev/null +++ b/llvm/test/CodeGen/RISCV/ret-remat.ll @@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=riscv64 -mattr=+m,+a,+f,+d,+c < %s | FileCheck %s + +@bytes1 = external hidden global i32 + +define i8 @cast_and_load_1() { +; CHECK-LABEL: cast_and_load_1: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a1, %hi(bytes1) +; CHECK-NEXT: li a0, 42 +; CHECK-NEXT: sw a0, %lo(bytes1)(a1) +; CHECK-NEXT: ret + store i32 42, ptr @bytes1, align 4 + %l = load i8, ptr @bytes1, align 1 + ret i8 %l +} diff --git a/llvm/test/CodeGen/RISCV/zfhmin-imm.ll b/llvm/test/CodeGen/RISCV/zfhmin-imm.ll index 7b3efd6fb8f2b..5be46f78491e2 100644 --- a/llvm/test/CodeGen/RISCV/zfhmin-imm.ll +++ b/llvm/test/CodeGen/RISCV/zfhmin-imm.ll @@ -75,11 +75,13 @@ define half @f16_negative_zero(ptr %pf) nounwind { ; RV32IZHINXMIN-LABEL: f16_negative_zero: ; RV32IZHINXMIN: # %bb.0: ; RV32IZHINXMIN-NEXT: lui a0, 1048568 +; RV32IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV32IZHINXMIN-NEXT: ret ; ; RV32IZDINXZHINXMIN-LABEL: f16_negative_zero: ; RV32IZDINXZHINXMIN: # %bb.0: ; RV32IZDINXZHINXMIN-NEXT: lui a0, 1048568 +; RV32IZDINXZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV32IZDINXZHINXMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: f16_negative_zero: @@ -97,11 +99,13 @@ define half @f16_negative_zero(ptr %pf) nounwind { ; RV64IZHINXMIN-LABEL: f16_negative_zero: ; RV64IZHINXMIN: # %bb.0: ; RV64IZHINXMIN-NEXT: lui a0, 1048568 +; RV64IZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV64IZHINXMIN-NEXT: ret ; ; RV64IZDINXZHINXMIN-LABEL: f16_negative_zero: ; RV64IZDINXZHINXMIN: # %bb.0: ; RV64IZDINXZHINXMIN-NEXT: lui a0, 1048568 +; RV64IZDINXZHINXMIN-NEXT: # kill: def $x10_h killed $x10_h killed $x10 ; RV64IZDINXZHINXMIN-NEXT: ret ret half -0.0 } diff --git a/llvm/test/CodeGen/X86/all-ones-vector.ll b/llvm/test/CodeGen/X86/all-ones-vector.ll index d624f6c13e367..f4ceb79026c33 100644 --- a/llvm/test/CodeGen/X86/all-ones-vector.ll +++ b/llvm/test/CodeGen/X86/all-ones-vector.ll @@ -92,7 +92,7 @@ define <32 x i8> @allones_v32i8() nounwind { ; SSE-LABEL: allones_v32i8: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v32i8: @@ -112,7 +112,7 @@ define <16 x i16> @allones_v16i16() nounwind { ; SSE-LABEL: allones_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v16i16: @@ -132,7 +132,7 @@ define <8 x i32> @allones_v8i32() nounwind { ; SSE-LABEL: allones_v8i32: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v8i32: @@ -152,7 +152,7 @@ define <4 x i64> @allones_v4i64() nounwind { ; SSE-LABEL: allones_v4i64: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v4i64: @@ -172,7 +172,7 @@ define <4 x double> @allones_v4f64() nounwind { ; SSE-LABEL: allones_v4f64: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v4f64: @@ -192,7 +192,7 @@ define <4 x double> @allones_v4f64_optsize() nounwind optsize { ; SSE-LABEL: allones_v4f64_optsize: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v4f64_optsize: @@ -212,7 +212,7 @@ define <8 x float> @allones_v8f32() nounwind { ; SSE-LABEL: allones_v8f32: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v8f32: @@ -232,7 +232,7 @@ define <8 x float> @allones_v8f32_optsize() nounwind optsize { ; SSE-LABEL: allones_v8f32_optsize: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v8f32_optsize: @@ -252,9 +252,9 @@ define <64 x i8> @allones_v64i8() nounwind { ; SSE-LABEL: allones_v64i8: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v64i8: @@ -267,12 +267,12 @@ define <64 x i8> @allones_v64i8() nounwind { ; AVX2-LABEL: allones_v64i8: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa %ymm0, %ymm1 ; AVX2-NEXT: ret{{[l|q]}} ; ; AVX512-LABEL: allones_v64i8: ; AVX512: # %bb.0: -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1 ; AVX512-NEXT: ret{{[l|q]}} ret <64 x i8> } @@ -281,9 +281,9 @@ define <32 x i16> @allones_v32i16() nounwind { ; SSE-LABEL: allones_v32i16: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v32i16: @@ -296,12 +296,12 @@ define <32 x i16> @allones_v32i16() nounwind { ; AVX2-LABEL: allones_v32i16: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa %ymm0, %ymm1 ; AVX2-NEXT: ret{{[l|q]}} ; ; AVX512-LABEL: allones_v32i16: ; AVX512: # %bb.0: -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1 ; AVX512-NEXT: ret{{[l|q]}} ret <32 x i16> } @@ -310,9 +310,9 @@ define <16 x i32> @allones_v16i32() nounwind { ; SSE-LABEL: allones_v16i32: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v16i32: @@ -325,12 +325,12 @@ define <16 x i32> @allones_v16i32() nounwind { ; AVX2-LABEL: allones_v16i32: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa %ymm0, %ymm1 ; AVX2-NEXT: ret{{[l|q]}} ; ; AVX512-LABEL: allones_v16i32: ; AVX512: # %bb.0: -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1 ; AVX512-NEXT: ret{{[l|q]}} ret <16 x i32> } @@ -339,9 +339,9 @@ define <8 x i64> @allones_v8i64() nounwind { ; SSE-LABEL: allones_v8i64: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v8i64: @@ -354,12 +354,12 @@ define <8 x i64> @allones_v8i64() nounwind { ; AVX2-LABEL: allones_v8i64: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa %ymm0, %ymm1 ; AVX2-NEXT: ret{{[l|q]}} ; ; AVX512-LABEL: allones_v8i64: ; AVX512: # %bb.0: -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1 ; AVX512-NEXT: ret{{[l|q]}} ret <8 x i64> } @@ -368,9 +368,9 @@ define <8 x double> @allones_v8f64() nounwind { ; SSE-LABEL: allones_v8f64: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v8f64: @@ -383,12 +383,12 @@ define <8 x double> @allones_v8f64() nounwind { ; AVX2-LABEL: allones_v8f64: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa %ymm0, %ymm1 ; AVX2-NEXT: ret{{[l|q]}} ; ; AVX512-LABEL: allones_v8f64: ; AVX512: # %bb.0: -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1 ; AVX512-NEXT: ret{{[l|q]}} ret <8 x double> } @@ -397,9 +397,9 @@ define <16 x float> @allones_v16f32() nounwind { ; SSE-LABEL: allones_v16f32: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE-NEXT: pcmpeqd %xmm2, %xmm2 -; SSE-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE-NEXT: movdqa %xmm0, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: movdqa %xmm0, %xmm3 ; SSE-NEXT: ret{{[l|q]}} ; ; AVX1-LABEL: allones_v16f32: @@ -412,12 +412,12 @@ define <16 x float> @allones_v16f32() nounwind { ; AVX2-LABEL: allones_v16f32: ; AVX2: # %bb.0: ; AVX2-NEXT: vpcmpeqd %ymm0, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; AVX2-NEXT: vmovdqa %ymm0, %ymm1 ; AVX2-NEXT: ret{{[l|q]}} ; ; AVX512-LABEL: allones_v16f32: ; AVX512: # %bb.0: -; AVX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 +; AVX512-NEXT: vpternlogd {{.*#+}} zmm0 = -1 ; AVX512-NEXT: ret{{[l|q]}} ret <16 x float> } diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll index 684e2921b789e..170774b3612a0 100644 --- a/llvm/test/CodeGen/X86/bfloat.ll +++ b/llvm/test/CodeGen/X86/bfloat.ll @@ -815,9 +815,9 @@ define <32 x bfloat> @pr63017() { ; SSE2-LABEL: pr63017: ; SSE2: # %bb.0: ; SSE2-NEXT: xorps %xmm0, %xmm0 -; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: xorps %xmm2, %xmm2 -; SSE2-NEXT: xorps %xmm3, %xmm3 +; SSE2-NEXT: movaps %xmm0, %xmm1 +; SSE2-NEXT: movaps %xmm0, %xmm2 +; SSE2-NEXT: movaps %xmm0, %xmm3 ; SSE2-NEXT: retq ; ; F16-LABEL: pr63017: @@ -828,7 +828,7 @@ define <32 x bfloat> @pr63017() { ; AVXNC-LABEL: pr63017: ; AVXNC: # %bb.0: ; AVXNC-NEXT: vxorps %xmm0, %xmm0, %xmm0 -; AVXNC-NEXT: vxorps %xmm1, %xmm1, %xmm1 +; AVXNC-NEXT: vmovaps %ymm0, %ymm1 ; AVXNC-NEXT: retq ret <32 x bfloat> zeroinitializer } diff --git a/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll b/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll index 98d315ad14e68..87c1ccbe891f5 100644 --- a/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll +++ b/llvm/test/CodeGen/X86/cet_endbr_imm_enhance.ll @@ -74,10 +74,10 @@ define dso_local nonnull ptr @foo3() local_unnamed_addr #0 { ; CHECK-LABEL: foo3: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: endbr64 -; CHECK-NEXT: movl $217112837, %eax # imm = 0xCF0E105 -; CHECK-NEXT: notl %eax -; CHECK-NEXT: andl %eax, czx(%rip) ; CHECK-NEXT: movl $czx, %eax +; CHECK-NEXT: movl $217112837, %ecx # imm = 0xCF0E105 +; CHECK-NEXT: notl %ecx +; CHECK-NEXT: andl %ecx, czx(%rip) ; CHECK-NEXT: retq entry: %0 = load i32, ptr @czx, align 4 diff --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll index 1ce10c3708d58..9e42d4afdcc70 100644 --- a/llvm/test/CodeGen/X86/combine-shl.ll +++ b/llvm/test/CodeGen/X86/combine-shl.ll @@ -285,7 +285,7 @@ define <8 x i32> @combine_vec_shl_ext_shl1(<8 x i16> %x) { ; SSE-LABEL: combine_vec_shl_ext_shl1: ; SSE: # %bb.0: ; SSE-NEXT: xorps %xmm0, %xmm0 -; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_shl_ext_shl1: diff --git a/llvm/test/CodeGen/X86/combine-subo.ll b/llvm/test/CodeGen/X86/combine-subo.ll index 5e4bba6e0fd35..68ba746584d76 100644 --- a/llvm/test/CodeGen/X86/combine-subo.ll +++ b/llvm/test/CodeGen/X86/combine-subo.ll @@ -202,13 +202,13 @@ define { <4 x i8>, <4 x i1> } @always_usub_const_vector() nounwind { ; SSE-LABEL: always_usub_const_vector: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: retq ; ; AVX-LABEL: always_usub_const_vector: ; AVX: # %bb.0: ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 +; AVX-NEXT: vmovdqa %xmm0, %xmm1 ; AVX-NEXT: retq %x = call { <4 x i8>, <4 x i1> } @llvm.usub.with.overflow.v4i8(<4 x i8> , <4 x i8> ) ret { <4 x i8>, <4 x i1> } %x diff --git a/llvm/test/CodeGen/X86/oddshuffles.ll b/llvm/test/CodeGen/X86/oddshuffles.ll index 4b0f75df83a76..c42ffa27185f7 100644 --- a/llvm/test/CodeGen/X86/oddshuffles.ll +++ b/llvm/test/CodeGen/X86/oddshuffles.ll @@ -2190,11 +2190,11 @@ define <16 x i32> @splat_v3i32(ptr %ptr) { ; SSE2: # %bb.0: ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] -; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,0,1] +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,0,1] ; SSE2-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: xorps %xmm1, %xmm1 -; SSE2-NEXT: xorps %xmm3, %xmm3 +; SSE2-NEXT: movaps %xmm1, %xmm3 ; SSE2-NEXT: retq ; ; SSE42-LABEL: splat_v3i32: @@ -2205,7 +2205,7 @@ define <16 x i32> @splat_v3i32(ptr %ptr) { ; SSE42-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1],xmm2[2,3,4,5,6,7] ; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7] ; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,0,1] -; SSE42-NEXT: xorps %xmm3, %xmm3 +; SSE42-NEXT: movdqa %xmm1, %xmm3 ; SSE42-NEXT: retq ; ; AVX1-LABEL: splat_v3i32: diff --git a/llvm/test/CodeGen/X86/oddsubvector.ll b/llvm/test/CodeGen/X86/oddsubvector.ll index 5df1867f73c8e..458ddbba14744 100644 --- a/llvm/test/CodeGen/X86/oddsubvector.ll +++ b/llvm/test/CodeGen/X86/oddsubvector.ll @@ -123,17 +123,16 @@ define <16 x i32> @PR42819(ptr %a0) { ; SSE-NEXT: movdqu (%rdi), %xmm3 ; SSE-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,xmm3[0,1,2,3,4,5,6,7,8,9,10,11] ; SSE-NEXT: xorps %xmm0, %xmm0 -; SSE-NEXT: xorps %xmm1, %xmm1 -; SSE-NEXT: xorps %xmm2, %xmm2 +; SSE-NEXT: movaps %xmm0, %xmm1 +; SSE-NEXT: movaps %xmm0, %xmm2 ; SSE-NEXT: retq ; ; AVX-LABEL: PR42819: ; AVX: # %bb.0: ; AVX-NEXT: vpermilps {{.*#+}} xmm0 = mem[0,0,1,2] -; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 -; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 -; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1,2,3,4],ymm0[5,6,7] +; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm1 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3,4],ymm1[5,6,7] ; AVX-NEXT: retq ; ; AVX512-LABEL: PR42819: diff --git a/llvm/test/CodeGen/X86/pmulh.ll b/llvm/test/CodeGen/X86/pmulh.ll index ead7110ae5790..1827682092819 100644 --- a/llvm/test/CodeGen/X86/pmulh.ll +++ b/llvm/test/CodeGen/X86/pmulh.ll @@ -2857,7 +2857,7 @@ define <16 x i16> @and_mulhuw_v16i16_shift31(<16 x i32> %a, <16 x i32> %b) { ; SSE-LABEL: and_mulhuw_v16i16_shift31: ; SSE: # %bb.0: ; SSE-NEXT: xorps %xmm0, %xmm0 -; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: retq ; ; AVX-LABEL: and_mulhuw_v16i16_shift31: diff --git a/llvm/test/CodeGen/X86/regcoalesce-zeroidiom.ll b/llvm/test/CodeGen/X86/regcoalesce-zeroidiom.ll new file mode 100644 index 0000000000000..7bbdcbb0da67c --- /dev/null +++ b/llvm/test/CodeGen/X86/regcoalesce-zeroidiom.ll @@ -0,0 +1,12 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 | FileCheck %s + + +define { i64, i64 } @test_xor_int_two_returns() { +; CHECK-LABEL: test_xor_int_two_returns: +; CHECK: # %bb.0: +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: xorl %edx, %edx +; CHECK-NEXT: retq + ret { i64, i64 } { i64 0, i64 0 } +} diff --git a/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll b/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll index c449ec5d3f10b..1f209495d8366 100644 --- a/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll +++ b/llvm/test/CodeGen/X86/shuffle-combine-crash-2.ll @@ -6,13 +6,13 @@ define <4 x i64> @fold_movsd_zero() { ; X86-LABEL: fold_movsd_zero: ; X86: # %bb.0: ; X86-NEXT: xorps %xmm0, %xmm0 -; X86-NEXT: xorps %xmm1, %xmm1 +; X86-NEXT: movaps %xmm0, %xmm1 ; X86-NEXT: retl ; ; X64-LABEL: fold_movsd_zero: ; X64: # %bb.0: ; X64-NEXT: xorps %xmm0, %xmm0 -; X64-NEXT: xorps %xmm1, %xmm1 +; X64-NEXT: movaps %xmm0, %xmm1 ; X64-NEXT: retq %insert = insertelement <4 x i64> zeroinitializer, i64 0, i32 0 %shuffle = shufflevector <4 x i64> %insert, <4 x i64> zeroinitializer, <4 x i32> diff --git a/llvm/test/CodeGen/X86/vec_minmax_sint.ll b/llvm/test/CodeGen/X86/vec_minmax_sint.ll index 853e29b8acfcd..214e536e17e6d 100644 --- a/llvm/test/CodeGen/X86/vec_minmax_sint.ll +++ b/llvm/test/CodeGen/X86/vec_minmax_sint.ll @@ -1565,8 +1565,8 @@ define <2 x i64> @max_gt_v2i64c() { define <4 x i64> @max_gt_v4i64c() { ; SSE-LABEL: max_gt_v4i64c: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: retq ; ; AVX1-LABEL: max_gt_v4i64c: @@ -1727,8 +1727,8 @@ define <2 x i64> @max_ge_v2i64c() { define <4 x i64> @max_ge_v4i64c() { ; SSE-LABEL: max_ge_v4i64c: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: retq ; ; AVX1-LABEL: max_ge_v4i64c: diff --git a/llvm/test/CodeGen/X86/vec_minmax_uint.ll b/llvm/test/CodeGen/X86/vec_minmax_uint.ll index 9b4da3f9b817f..7a5fb11286251 100644 --- a/llvm/test/CodeGen/X86/vec_minmax_uint.ll +++ b/llvm/test/CodeGen/X86/vec_minmax_uint.ll @@ -1677,8 +1677,8 @@ define <2 x i64> @max_gt_v2i64c() { define <4 x i64> @max_gt_v4i64c() { ; SSE-LABEL: max_gt_v4i64c: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: retq ; ; AVX1-LABEL: max_gt_v4i64c: @@ -1839,8 +1839,8 @@ define <2 x i64> @max_ge_v2i64c() { define <4 x i64> @max_ge_v4i64c() { ; SSE-LABEL: max_ge_v4i64c: ; SSE: # %bb.0: -; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 +; SSE-NEXT: movaps {{.*#+}} xmm1 = [7,7] ; SSE-NEXT: retq ; ; AVX1-LABEL: max_ge_v4i64c: diff --git a/llvm/test/CodeGen/X86/vec_umulo.ll b/llvm/test/CodeGen/X86/vec_umulo.ll index 62db6d234d301..131317595a4c7 100644 --- a/llvm/test/CodeGen/X86/vec_umulo.ll +++ b/llvm/test/CodeGen/X86/vec_umulo.ll @@ -2857,8 +2857,8 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; SSE-NEXT: pand %xmm1, %xmm0 ; SSE-NEXT: pslld $31, %xmm0 ; SSE-NEXT: movmskps %xmm0, %eax -; SSE-NEXT: movb %al, (%rdi) ; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: movb %al, (%rdi) ; SSE-NEXT: retq ; ; AVX-LABEL: umulo_v4i1: @@ -2866,8 +2866,8 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX-NEXT: vmovmskps %xmm0, %eax -; AVX-NEXT: movb %al, (%rdi) ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: movb %al, (%rdi) ; AVX-NEXT: retq ; ; AVX512F-LABEL: umulo_v4i1: @@ -2875,9 +2875,9 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; AVX512F-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512F-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512F-NEXT: vptestmd %xmm0, %xmm0, %k0 +; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: movb %al, (%rdi) -; AVX512F-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; AVX512F-NEXT: retq ; ; AVX512BW-LABEL: umulo_v4i1: @@ -2885,9 +2885,9 @@ define <4 x i32> @umulo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; AVX512BW-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512BW-NEXT: vpslld $31, %xmm0, %xmm0 ; AVX512BW-NEXT: vptestmd %xmm0, %xmm0, %k0 +; AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; AVX512BW-NEXT: kmovd %k0, %eax ; AVX512BW-NEXT: movb %al, (%rdi) -; AVX512BW-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; AVX512BW-NEXT: retq %t = call {<4 x i1>, <4 x i1>} @llvm.umul.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1) %val = extractvalue {<4 x i1>, <4 x i1>} %t, 0 diff --git a/llvm/test/CodeGen/X86/vector-partial-undef.ll b/llvm/test/CodeGen/X86/vector-partial-undef.ll index 7c12e5295257c..dd6afa65ed203 100644 --- a/llvm/test/CodeGen/X86/vector-partial-undef.ll +++ b/llvm/test/CodeGen/X86/vector-partial-undef.ll @@ -80,7 +80,7 @@ define <4 x i64> @and_undef_elts(<2 x i64> %x) { ; SSE-LABEL: and_undef_elts: ; SSE: # %bb.0: ; SSE-NEXT: xorps %xmm0, %xmm0 -; SSE-NEXT: xorps %xmm1, %xmm1 +; SSE-NEXT: movaps %xmm0, %xmm1 ; SSE-NEXT: retq ; ; AVX-LABEL: and_undef_elts: @@ -99,7 +99,7 @@ define <4 x i64> @or_undef_elts(<2 x i64> %x) { ; SSE-LABEL: or_undef_elts: ; SSE: # %bb.0: ; SSE-NEXT: pcmpeqd %xmm0, %xmm0 -; SSE-NEXT: pcmpeqd %xmm1, %xmm1 +; SSE-NEXT: movdqa %xmm0, %xmm1 ; SSE-NEXT: retq ; ; AVX-LABEL: or_undef_elts: diff --git a/llvm/test/CodeGen/X86/vector-shift-lut.ll b/llvm/test/CodeGen/X86/vector-shift-lut.ll index 0bf2006090893..cd98553514c97 100644 --- a/llvm/test/CodeGen/X86/vector-shift-lut.ll +++ b/llvm/test/CodeGen/X86/vector-shift-lut.ll @@ -1358,98 +1358,98 @@ define <32 x i8> @perlane_ashr_v32i8(<32 x i8> %a) nounwind { define <64 x i8> @perlane_shl_v64i8(<64 x i8> %a) nounwind { ; SSE2-LABEL: perlane_shl_v64i8: ; SSE2: # %bb.0: -; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psllw $5, %xmm1 -; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm0 +; SSE2-NEXT: movdqa %xmm0, %xmm4 +; SSE2-NEXT: psllw $5, %xmm4 +; SSE2-NEXT: xorps %xmm1, %xmm1 +; SSE2-NEXT: pxor %xmm6, %xmm6 +; SSE2-NEXT: pcmpgtb %xmm4, %xmm6 +; SSE2-NEXT: movdqa %xmm6, %xmm0 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 -; SSE2-NEXT: por %xmm0, %xmm4 -; SSE2-NEXT: paddb %xmm1, %xmm1 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 +; SSE2-NEXT: por %xmm0, %xmm6 +; SSE2-NEXT: paddb %xmm4, %xmm4 ; SSE2-NEXT: pxor %xmm0, %xmm0 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE2-NEXT: pcmpgtb %xmm4, %xmm0 ; SSE2-NEXT: movdqa %xmm0, %xmm7 -; SSE2-NEXT: pandn %xmm4, %xmm7 -; SSE2-NEXT: psllw $2, %xmm4 -; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] +; SSE2-NEXT: pandn %xmm6, %xmm7 +; SSE2-NEXT: psllw $2, %xmm6 +; SSE2-NEXT: movdqa {{.*#+}} xmm5 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252] +; SSE2-NEXT: pand %xmm5, %xmm0 ; SSE2-NEXT: pand %xmm6, %xmm0 -; SSE2-NEXT: pand %xmm4, %xmm0 ; SSE2-NEXT: por %xmm7, %xmm0 -; SSE2-NEXT: paddb %xmm1, %xmm1 -; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm1 -; SSE2-NEXT: pandn %xmm0, %xmm1 +; SSE2-NEXT: paddb %xmm4, %xmm4 +; SSE2-NEXT: pxor %xmm6, %xmm6 +; SSE2-NEXT: pcmpgtb %xmm4, %xmm6 +; SSE2-NEXT: movdqa %xmm6, %xmm4 +; SSE2-NEXT: pandn %xmm0, %xmm4 ; SSE2-NEXT: paddb %xmm0, %xmm0 -; SSE2-NEXT: pand %xmm4, %xmm0 -; SSE2-NEXT: por %xmm1, %xmm0 +; SSE2-NEXT: pand %xmm6, %xmm0 +; SSE2-NEXT: por %xmm4, %xmm0 ; SSE2-NEXT: psllw $5, %xmm3 -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm3, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: pxor %xmm6, %xmm6 +; SSE2-NEXT: pcmpgtb %xmm3, %xmm6 +; SSE2-NEXT: movdqa %xmm6, %xmm4 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 -; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; SSE2-NEXT: por %xmm4, %xmm1 +; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 +; SSE2-NEXT: por %xmm4, %xmm6 ; SSE2-NEXT: paddb %xmm3, %xmm3 ; SSE2-NEXT: pxor %xmm4, %xmm4 ; SSE2-NEXT: pcmpgtb %xmm3, %xmm4 ; SSE2-NEXT: movdqa %xmm4, %xmm7 -; SSE2-NEXT: pandn %xmm1, %xmm7 -; SSE2-NEXT: psllw $2, %xmm1 +; SSE2-NEXT: pandn %xmm6, %xmm7 +; SSE2-NEXT: psllw $2, %xmm6 +; SSE2-NEXT: pand %xmm5, %xmm4 ; SSE2-NEXT: pand %xmm6, %xmm4 -; SSE2-NEXT: pand %xmm1, %xmm4 ; SSE2-NEXT: por %xmm7, %xmm4 ; SSE2-NEXT: paddb %xmm3, %xmm3 -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm3, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm3 +; SSE2-NEXT: pxor %xmm6, %xmm6 +; SSE2-NEXT: pcmpgtb %xmm3, %xmm6 +; SSE2-NEXT: movdqa %xmm6, %xmm3 ; SSE2-NEXT: pandn %xmm4, %xmm3 ; SSE2-NEXT: paddb %xmm4, %xmm4 -; SSE2-NEXT: pand %xmm1, %xmm4 +; SSE2-NEXT: pand %xmm6, %xmm4 ; SSE2-NEXT: por %xmm3, %xmm4 ; SSE2-NEXT: psllw $5, %xmm2 -; SSE2-NEXT: pxor %xmm1, %xmm1 -; SSE2-NEXT: pcmpgtb %xmm2, %xmm1 -; SSE2-NEXT: movdqa {{.*#+}} xmm7 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] -; SSE2-NEXT: pand %xmm1, %xmm7 -; SSE2-NEXT: paddb %xmm1, %xmm7 -; SSE2-NEXT: pcmpeqd %xmm1, %xmm1 -; SSE2-NEXT: psubb %xmm1, %xmm7 +; SSE2-NEXT: pxor %xmm3, %xmm3 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 +; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] +; SSE2-NEXT: pand %xmm3, %xmm6 +; SSE2-NEXT: paddb %xmm3, %xmm6 +; SSE2-NEXT: pcmpeqd %xmm3, %xmm3 +; SSE2-NEXT: psubb %xmm3, %xmm6 ; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm3, %xmm3 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm3 -; SSE2-NEXT: movdqa %xmm3, %xmm1 -; SSE2-NEXT: pandn %xmm7, %xmm1 -; SSE2-NEXT: psllw $2, %xmm7 +; SSE2-NEXT: movdqa %xmm3, %xmm7 +; SSE2-NEXT: pandn %xmm6, %xmm7 +; SSE2-NEXT: psllw $2, %xmm6 +; SSE2-NEXT: pand %xmm5, %xmm3 ; SSE2-NEXT: pand %xmm6, %xmm3 -; SSE2-NEXT: pand %xmm7, %xmm3 -; SSE2-NEXT: por %xmm1, %xmm3 +; SSE2-NEXT: por %xmm7, %xmm3 ; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm5, %xmm5 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm5 -; SSE2-NEXT: movdqa %xmm5, %xmm1 -; SSE2-NEXT: pandn %xmm3, %xmm1 +; SSE2-NEXT: movdqa %xmm5, %xmm2 +; SSE2-NEXT: pandn %xmm3, %xmm2 ; SSE2-NEXT: paddb %xmm3, %xmm3 ; SSE2-NEXT: pand %xmm5, %xmm3 -; SSE2-NEXT: por %xmm1, %xmm3 -; SSE2-NEXT: pxor %xmm1, %xmm1 +; SSE2-NEXT: por %xmm2, %xmm3 ; SSE2-NEXT: movdqa %xmm3, %xmm2 ; SSE2-NEXT: movdqa %xmm4, %xmm3 ; SSE2-NEXT: retq ; ; SSE41-LABEL: perlane_shl_v64i8: ; SSE41: # %bb.0: -; SSE41-NEXT: movq {{.*#+}} xmm4 = [7,14,28,56,112,224,192,128,0,0,0,0,0,0,0,0] -; SSE41-NEXT: pshufb %xmm0, %xmm4 -; SSE41-NEXT: movq {{.*#+}} xmm5 = [1,2,4,8,16,32,64,128,0,0,0,0,0,0,0,0] -; SSE41-NEXT: pshufb %xmm2, %xmm5 -; SSE41-NEXT: movq {{.*#+}} xmm6 = [2,4,8,16,32,64,128,0,0,0,0,0,0,0,0,0] -; SSE41-NEXT: pshufb %xmm3, %xmm6 +; SSE41-NEXT: movq {{.*#+}} xmm6 = [7,14,28,56,112,224,192,128,0,0,0,0,0,0,0,0] +; SSE41-NEXT: pshufb %xmm0, %xmm6 +; SSE41-NEXT: movq {{.*#+}} xmm4 = [1,2,4,8,16,32,64,128,0,0,0,0,0,0,0,0] +; SSE41-NEXT: pshufb %xmm2, %xmm4 +; SSE41-NEXT: movq {{.*#+}} xmm5 = [2,4,8,16,32,64,128,0,0,0,0,0,0,0,0,0] +; SSE41-NEXT: pshufb %xmm3, %xmm5 ; SSE41-NEXT: xorps %xmm1, %xmm1 -; SSE41-NEXT: movdqa %xmm4, %xmm0 -; SSE41-NEXT: movdqa %xmm5, %xmm2 -; SSE41-NEXT: movdqa %xmm6, %xmm3 +; SSE41-NEXT: movdqa %xmm6, %xmm0 +; SSE41-NEXT: movdqa %xmm4, %xmm2 +; SSE41-NEXT: movdqa %xmm5, %xmm3 ; SSE41-NEXT: retq ; ; AVX1-LABEL: perlane_shl_v64i8: @@ -1690,61 +1690,61 @@ define <64 x i8> @perlane_ashr_v64i8(<64 x i8> %a) nounwind { ; SSE2-LABEL: perlane_ashr_v64i8: ; SSE2: # %bb.0: ; SSE2-NEXT: psllw $5, %xmm1 -; SSE2-NEXT: pxor %xmm0, %xmm0 -; SSE2-NEXT: pcmpgtb %xmm1, %xmm0 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtb %xmm1, %xmm4 ; SSE2-NEXT: movdqa %xmm1, %xmm5 ; SSE2-NEXT: paddb %xmm1, %xmm5 -; SSE2-NEXT: pxor %xmm4, %xmm4 -; SSE2-NEXT: pxor %xmm6, %xmm6 -; SSE2-NEXT: pcmpgtb %xmm5, %xmm6 -; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE2-NEXT: pandn %xmm0, %xmm6 +; SSE2-NEXT: xorps %xmm0, %xmm0 +; SSE2-NEXT: pxor %xmm7, %xmm7 +; SSE2-NEXT: pcmpgtb %xmm5, %xmm7 +; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 +; SSE2-NEXT: pandn %xmm4, %xmm7 ; SSE2-NEXT: paddb %xmm5, %xmm5 ; SSE2-NEXT: pxor %xmm1, %xmm1 ; SSE2-NEXT: pcmpgtb %xmm5, %xmm1 -; SSE2-NEXT: movdqa %xmm1, %xmm5 -; SSE2-NEXT: pandn %xmm6, %xmm5 -; SSE2-NEXT: psrlw $1, %xmm6 -; SSE2-NEXT: movdqa {{.*#+}} xmm0 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; SSE2-NEXT: pand %xmm0, %xmm1 +; SSE2-NEXT: movdqa %xmm1, %xmm4 +; SSE2-NEXT: pandn %xmm7, %xmm4 +; SSE2-NEXT: psrlw $1, %xmm7 +; SSE2-NEXT: movdqa {{.*#+}} xmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] ; SSE2-NEXT: pand %xmm6, %xmm1 -; SSE2-NEXT: por %xmm5, %xmm1 +; SSE2-NEXT: pand %xmm7, %xmm1 +; SSE2-NEXT: por %xmm4, %xmm1 ; SSE2-NEXT: psllw $5, %xmm2 -; SSE2-NEXT: pxor %xmm5, %xmm5 -; SSE2-NEXT: pcmpgtb %xmm2, %xmm5 -; SSE2-NEXT: paddb %xmm2, %xmm2 -; SSE2-NEXT: pxor %xmm6, %xmm6 -; SSE2-NEXT: pcmpgtb %xmm2, %xmm6 -; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm5 -; SSE2-NEXT: pandn %xmm5, %xmm6 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm4 ; SSE2-NEXT: paddb %xmm2, %xmm2 ; SSE2-NEXT: pxor %xmm5, %xmm5 ; SSE2-NEXT: pcmpgtb %xmm2, %xmm5 -; SSE2-NEXT: movdqa %xmm5, %xmm2 -; SSE2-NEXT: pandn %xmm6, %xmm2 -; SSE2-NEXT: psrlw $1, %xmm6 -; SSE2-NEXT: pand %xmm0, %xmm5 -; SSE2-NEXT: pand %xmm6, %xmm5 -; SSE2-NEXT: por %xmm2, %xmm5 +; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm4 +; SSE2-NEXT: pandn %xmm4, %xmm5 +; SSE2-NEXT: paddb %xmm2, %xmm2 +; SSE2-NEXT: pxor %xmm4, %xmm4 +; SSE2-NEXT: pcmpgtb %xmm2, %xmm4 +; SSE2-NEXT: movdqa %xmm4, %xmm2 +; SSE2-NEXT: pandn %xmm5, %xmm2 +; SSE2-NEXT: psrlw $1, %xmm5 +; SSE2-NEXT: pand %xmm6, %xmm4 +; SSE2-NEXT: pand %xmm5, %xmm4 +; SSE2-NEXT: por %xmm2, %xmm4 ; SSE2-NEXT: psllw $5, %xmm3 ; SSE2-NEXT: pxor %xmm2, %xmm2 ; SSE2-NEXT: pcmpgtb %xmm3, %xmm2 ; SSE2-NEXT: paddb %xmm3, %xmm3 -; SSE2-NEXT: pxor %xmm6, %xmm6 -; SSE2-NEXT: pcmpgtb %xmm3, %xmm6 +; SSE2-NEXT: pxor %xmm7, %xmm7 +; SSE2-NEXT: pcmpgtb %xmm3, %xmm7 ; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 -; SSE2-NEXT: pandn %xmm2, %xmm6 +; SSE2-NEXT: pandn %xmm2, %xmm7 ; SSE2-NEXT: paddb %xmm3, %xmm3 -; SSE2-NEXT: pcmpgtb %xmm3, %xmm4 -; SSE2-NEXT: movdqa %xmm4, %xmm2 -; SSE2-NEXT: pandn %xmm6, %xmm2 -; SSE2-NEXT: psrlw $1, %xmm6 -; SSE2-NEXT: pand %xmm0, %xmm4 -; SSE2-NEXT: pand %xmm6, %xmm4 -; SSE2-NEXT: por %xmm2, %xmm4 -; SSE2-NEXT: pxor %xmm0, %xmm0 +; SSE2-NEXT: pxor %xmm5, %xmm5 +; SSE2-NEXT: pcmpgtb %xmm3, %xmm5 ; SSE2-NEXT: movdqa %xmm5, %xmm2 -; SSE2-NEXT: movdqa %xmm4, %xmm3 +; SSE2-NEXT: pandn %xmm7, %xmm2 +; SSE2-NEXT: psrlw $1, %xmm7 +; SSE2-NEXT: pand %xmm6, %xmm5 +; SSE2-NEXT: pand %xmm7, %xmm5 +; SSE2-NEXT: por %xmm2, %xmm5 +; SSE2-NEXT: movdqa %xmm4, %xmm2 +; SSE2-NEXT: movdqa %xmm5, %xmm3 ; SSE2-NEXT: retq ; ; SSE41-LABEL: perlane_ashr_v64i8: diff --git a/llvm/test/CodeGen/X86/vectorcall.ll b/llvm/test/CodeGen/X86/vectorcall.ll index 07446c6a7bfa4..14bd4ee4c9024 100644 --- a/llvm/test/CodeGen/X86/vectorcall.ll +++ b/llvm/test/CodeGen/X86/vectorcall.ll @@ -54,9 +54,9 @@ define x86_vectorcallcc double @test_fp_2(double, double, double, double, double define x86_vectorcallcc {double, double, double, double} @test_fp_3() { ; CHECK-LABEL: {{^}}test_fp_3@@0: ; CHECK: xorps %xmm0 -; CHECK: xorps %xmm1 -; CHECK: xorps %xmm2 -; CHECK: xorps %xmm3 +; CHECK: movaps %xmm0, %xmm1 +; CHECK: movaps %xmm0, %xmm2 +; CHECK: movaps %xmm0, %xmm3 ret {double, double, double, double} { double 0.0, double 0.0, double 0.0, double 0.0 } } @@ -65,11 +65,11 @@ define x86_vectorcallcc {double, double, double, double} @test_fp_3() { ; tablegen any other way. define x86_vectorcallcc {double, double, double, double, double} @test_fp_4() { ; CHECK-LABEL: {{^}}test_fp_4@@0: +; CHECK: xorps %xmm0, %xmm0 ; CHECK: fldz -; CHECK: xorps %xmm0 -; CHECK: xorps %xmm1 -; CHECK: xorps %xmm2 -; CHECK: xorps %xmm3 +; CHECK: movaps %xmm0, %xmm1 +; CHECK: movaps %xmm0, %xmm2 +; CHECK: movaps %xmm0, %xmm3 ret {double, double, double, double, double} { double 0.0, double 0.0, double 0.0, double 0.0, double 0.0 } } diff --git a/llvm/test/DebugInfo/XCOFF/empty.ll b/llvm/test/DebugInfo/XCOFF/empty.ll index af2f74fb82b8f..30d831f052378 100644 --- a/llvm/test/DebugInfo/XCOFF/empty.ll +++ b/llvm/test/DebugInfo/XCOFF/empty.ll @@ -50,11 +50,10 @@ entry: ; ASM32-NEXT: L..func_begin0: ; ASM32-NEXT: # %bb.0: # %entry ; ASM32-NEXT: L..tmp0: -; ASM32-NEXT: li 4, 0 +; ASM32-NEXT: li 3, 0 +; ASM32-NEXT: stw 3, -4(1) ; ASM32-NEXT: L..tmp1: ; ASM32-NEXT: L..tmp2: -; ASM32-NEXT: li 3, 0 -; ASM32-NEXT: stw 4, -4(1) ; ASM32-NEXT: blr ; ASM32-NEXT: L..tmp3: ; ASM32-NEXT: L..main0: @@ -253,11 +252,10 @@ entry: ; ASM64-NEXT: L..func_begin0: ; ASM64-NEXT: # %bb.0: # %entry ; ASM64-NEXT: L..tmp0: -; ASM64-NEXT: li 4, 0 +; ASM64-NEXT: li 3, 0 +; ASM64-NEXT: stw 3, -4(1) ; ASM64-NEXT: L..tmp1: ; ASM64-NEXT: L..tmp2: -; ASM64-NEXT: li 3, 0 -; ASM64-NEXT: stw 4, -4(1) ; ASM64-NEXT: blr ; ASM64-NEXT: L..tmp3: ; ASM64-NEXT: L..main0: @@ -474,10 +472,10 @@ entry: ; DWARF32-NEXT: DW_AT_stmt_list (0x00000000) ; DWARF32-NEXT: DW_AT_comp_dir ("debug") ; DWARF32-NEXT: DW_AT_low_pc (0x00000000) -; DWARF32-NEXT: DW_AT_high_pc (0x00000026) +; DWARF32-NEXT: DW_AT_high_pc (0x00000022) ; DWARF32: 0x00000039: DW_TAG_subprogram ; DWARF32-NEXT: DW_AT_low_pc (0x00000000) -; DWARF32-NEXT: DW_AT_high_pc (0x00000026) +; DWARF32-NEXT: DW_AT_high_pc (0x00000022) ; DWARF32-NEXT: DW_AT_frame_base (DW_OP_reg1 R1) ; DWARF32-NEXT: DW_AT_name ("main") ; DWARF32-NEXT: DW_AT_decl_file ("debug{{[/\\]}}1.c") @@ -523,5 +521,5 @@ entry: ; DWARF32: Address Line Column File ISA Discriminator OpIndex Flags ; DWARF32-NEXT: ------------------ ------ ------ ------ --- ------------- ------- ------------- ; DWARF32-NEXT: 0x0000000000000000 2 0 1 0 0 0 is_stmt -; DWARF32-NEXT: 0x0000000000000004 3 3 1 0 0 0 is_stmt prologue_end -; DWARF32-NEXT: 0x0000000000000024 3 3 1 0 0 0 is_stmt end_sequence +; DWARF32-NEXT: 0x0000000000000008 3 3 1 0 0 0 is_stmt prologue_end +; DWARF32-NEXT: 0x0000000000000020 3 3 1 0 0 0 is_stmt end_sequence diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected index 429bee4195fa9..cdadba1325e34 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.generated.expected @@ -119,25 +119,24 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, x@rel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, x@rel32@hi+12 -; CHECK-NEXT: v_mov_b32_e32 v2, 1 -; CHECK-NEXT: v_mov_b32_e32 v3, 2 -; CHECK-NEXT: v_mov_b32_e32 v4, 3 -; CHECK-NEXT: v_mov_b32_e32 v5, 4 +; CHECK-NEXT: v_mov_b32_e32 v3, 1 +; CHECK-NEXT: v_mov_b32_e32 v4, 2 +; CHECK-NEXT: v_mov_b32_e32 v5, 3 +; CHECK-NEXT: v_mov_b32_e32 v6, 4 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 -; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 -; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8 -; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12 -; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16 -; CHECK-NEXT: v_mov_b32_e32 v0, s4 -; CHECK-NEXT: v_mov_b32_e32 v1, s5 -; CHECK-NEXT: flat_store_dword v[0:1], v2 +; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4 +; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8 +; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12 +; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16 +; CHECK-NEXT: v_mov_b32_e32 v1, s4 +; CHECK-NEXT: v_mov_b32_e32 v2, s5 +; CHECK-NEXT: flat_store_dword v[1:2], v3 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 -; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8 -; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12 -; CHECK-NEXT: v_mov_b32_e32 v0, 0 -; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16 +; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4 +; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8 +; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12 +; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: s_mov_b32 s33, s6 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected index 842fd8836da7e..875cc85be8f04 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_generated_funcs.ll.nogenerated.expected @@ -96,25 +96,24 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, x@rel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, x@rel32@hi+12 -; CHECK-NEXT: v_mov_b32_e32 v2, 1 -; CHECK-NEXT: v_mov_b32_e32 v3, 2 -; CHECK-NEXT: v_mov_b32_e32 v4, 3 -; CHECK-NEXT: v_mov_b32_e32 v5, 4 +; CHECK-NEXT: v_mov_b32_e32 v3, 1 +; CHECK-NEXT: v_mov_b32_e32 v4, 2 +; CHECK-NEXT: v_mov_b32_e32 v5, 3 +; CHECK-NEXT: v_mov_b32_e32 v6, 4 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33 -; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 -; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8 -; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12 -; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16 -; CHECK-NEXT: v_mov_b32_e32 v0, s4 -; CHECK-NEXT: v_mov_b32_e32 v1, s5 -; CHECK-NEXT: flat_store_dword v[0:1], v2 +; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4 +; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8 +; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12 +; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16 +; CHECK-NEXT: v_mov_b32_e32 v1, s4 +; CHECK-NEXT: v_mov_b32_e32 v2, s5 +; CHECK-NEXT: flat_store_dword v[1:2], v3 ; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMEND -; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 offset:4 -; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:8 -; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:12 -; CHECK-NEXT: v_mov_b32_e32 v0, 0 -; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:16 +; CHECK-NEXT: buffer_store_dword v3, off, s[0:3], s33 offset:4 +; CHECK-NEXT: buffer_store_dword v4, off, s[0:3], s33 offset:8 +; CHECK-NEXT: buffer_store_dword v5, off, s[0:3], s33 offset:12 +; CHECK-NEXT: buffer_store_dword v6, off, s[0:3], s33 offset:16 ; CHECK-NEXT: s_mov_b32 s32, s33 ; CHECK-NEXT: s_mov_b32 s33, s6 ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected index 2dfb725f55665..91bb79f19ca5b 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.generated.expected @@ -100,23 +100,20 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="none" } ; CHECK-NEXT: sub sp, sp, #20 ; CHECK-NEXT: ldr r0, .LCPI1_0 ; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: mov r2, #3 -; CHECK-NEXT: mov r3, #4 +; CHECK-NEXT: mov r12, #2 +; CHECK-NEXT: mov r3, #3 +; CHECK-NEXT: mov r2, #4 ; CHECK-NEXT: str r1, [sp, #12] ; CHECK-NEXT: str r1, [r0] ; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: str r0, [sp, #16] -; CHECK-NEXT: mov r0, #2 -; CHECK-NEXT: str r0, [sp, #8] -; CHECK-NEXT: str r2, [sp, #4] -; CHECK-NEXT: str r3, [sp] +; CHECK-NEXT: str r12, [sp, #8] +; CHECK-NEXT: str r3, [sp, #4] +; CHECK-NEXT: str r2, [sp] ; CHECK-NEXT: @APP ; CHECK-NEXT: @NO_APP -; CHECK-NEXT: str r0, [sp, #8] -; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: str r1, [sp, #12] -; CHECK-NEXT: str r2, [sp, #4] -; CHECK-NEXT: str r3, [sp] +; CHECK-NEXT: stm sp, {r2, r3, r12} ; CHECK-NEXT: add sp, sp, #20 ; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: .p2align 2 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected index 85d3389cdaaf9..a5e76707c02eb 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/arm_generated_funcs.ll.nogenerated.expected @@ -77,23 +77,20 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: sub sp, sp, #20 ; CHECK-NEXT: ldr r0, .LCPI1_0 ; CHECK-NEXT: mov r1, #1 -; CHECK-NEXT: mov r2, #3 -; CHECK-NEXT: mov r3, #4 +; CHECK-NEXT: mov r12, #2 +; CHECK-NEXT: mov r3, #3 +; CHECK-NEXT: mov r2, #4 ; CHECK-NEXT: str r1, [sp, #12] ; CHECK-NEXT: str r1, [r0] ; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: str r0, [sp, #16] -; CHECK-NEXT: mov r0, #2 -; CHECK-NEXT: str r0, [sp, #8] -; CHECK-NEXT: str r2, [sp, #4] -; CHECK-NEXT: str r3, [sp] +; CHECK-NEXT: str r12, [sp, #8] +; CHECK-NEXT: str r3, [sp, #4] +; CHECK-NEXT: str r2, [sp] ; CHECK-NEXT: @APP ; CHECK-NEXT: @NO_APP -; CHECK-NEXT: str r0, [sp, #8] -; CHECK-NEXT: mov r0, #0 ; CHECK-NEXT: str r1, [sp, #12] -; CHECK-NEXT: str r2, [sp, #4] -; CHECK-NEXT: str r3, [sp] +; CHECK-NEXT: stm sp, {r2, r3, r12} ; CHECK-NEXT: add sp, sp, #20 ; CHECK-NEXT: mov pc, lr ; CHECK-NEXT: .p2align 2 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected index 36519299c1ffb..abd1c955f88ef 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.generated.expected @@ -113,7 +113,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: mov #4, -20(r4) ; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: clr r12 -; CHECK-NEXT: clr r13 +; CHECK-NEXT: mov r12, r13 ; CHECK-NEXT: add #20, r1 ; CHECK-NEXT: pop r4 ; CHECK-NEXT: .cfi_def_cfa r1, 2 @@ -151,7 +151,7 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: clr -18(r4) ; CHECK-NEXT: mov #4, -20(r4) ; CHECK-NEXT: clr r12 -; CHECK-NEXT: clr r13 +; CHECK-NEXT: mov r12, r13 ; CHECK-NEXT: add #20, r1 ; CHECK-NEXT: pop r4 ; CHECK-NEXT: .cfi_def_cfa r1, 2 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected index ffe417b9d618b..ad7447db37500 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/msp430_generated_funcs.ll.nogenerated.expected @@ -54,7 +54,7 @@ define dso_local i32 @check_boundaries() #0 { ; CHECK-NEXT: mov #4, -20(r4) ; CHECK-NEXT: .LBB0_6: ; CHECK-NEXT: clr r12 -; CHECK-NEXT: clr r13 +; CHECK-NEXT: mov r12, r13 ; CHECK-NEXT: add #20, r1 ; CHECK-NEXT: pop r4 ; CHECK-NEXT: .cfi_def_cfa r1, 2 @@ -128,7 +128,7 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: clr -18(r4) ; CHECK-NEXT: mov #4, -20(r4) ; CHECK-NEXT: clr r12 -; CHECK-NEXT: clr r13 +; CHECK-NEXT: mov r12, r13 ; CHECK-NEXT: add #20, r1 ; CHECK-NEXT: pop r4 ; CHECK-NEXT: .cfi_def_cfa r1, 2 diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected index 2b4c8025af30e..9e2d367b50bf4 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.generated.expected @@ -108,24 +108,23 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; CHECK-NEXT: mr 31, 1 ; CHECK-NEXT: .cfi_def_cfa_register r31 ; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: li 4, 1 +; CHECK-NEXT: li 5, 2 +; CHECK-NEXT: li 6, 3 +; CHECK-NEXT: li 7, 4 +; CHECK-NEXT: lis 8, x@ha ; CHECK-NEXT: stw 3, 24(31) -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: li 4, 2 -; CHECK-NEXT: li 5, 3 -; CHECK-NEXT: li 6, 4 -; CHECK-NEXT: lis 7, x@ha -; CHECK-NEXT: stw 3, 20(31) -; CHECK-NEXT: stw 4, 16(31) -; CHECK-NEXT: stw 5, 12(31) -; CHECK-NEXT: stw 6, 8(31) -; CHECK-NEXT: stw 3, x@l(7) +; CHECK-NEXT: stw 4, 20(31) +; CHECK-NEXT: stw 5, 16(31) +; CHECK-NEXT: stw 6, 12(31) +; CHECK-NEXT: stw 7, 8(31) +; CHECK-NEXT: stw 4, x@l(8) ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: stw 3, 20(31) -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: stw 4, 16(31) -; CHECK-NEXT: stw 5, 12(31) -; CHECK-NEXT: stw 6, 8(31) +; CHECK-NEXT: stw 4, 20(31) +; CHECK-NEXT: stw 5, 16(31) +; CHECK-NEXT: stw 6, 12(31) +; CHECK-NEXT: stw 7, 8(31) ; CHECK-NEXT: lwz 31, 28(1) ; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: blr @@ -168,23 +167,22 @@ attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" } ; AIX-NEXT: lwz 4, L..C0(2) # @x ; AIX-NEXT: mr 31, 1 ; AIX-NEXT: li 3, 0 +; AIX-NEXT: li 5, 1 +; AIX-NEXT: li 6, 2 +; AIX-NEXT: li 7, 3 +; AIX-NEXT: li 8, 4 ; AIX-NEXT: stw 3, 40(31) -; AIX-NEXT: li 3, 1 -; AIX-NEXT: li 5, 2 -; AIX-NEXT: li 6, 3 -; AIX-NEXT: li 7, 4 -; AIX-NEXT: stw 3, 36(31) -; AIX-NEXT: stw 5, 32(31) -; AIX-NEXT: stw 6, 28(31) -; AIX-NEXT: stw 7, 24(31) -; AIX-NEXT: stw 3, 0(4) +; AIX-NEXT: stw 5, 36(31) +; AIX-NEXT: stw 6, 32(31) +; AIX-NEXT: stw 7, 28(31) +; AIX-NEXT: stw 8, 24(31) +; AIX-NEXT: stw 5, 0(4) ; AIX-NEXT: #APP ; AIX-NEXT: #NO_APP -; AIX-NEXT: stw 3, 36(31) -; AIX-NEXT: li 3, 0 -; AIX-NEXT: stw 5, 32(31) -; AIX-NEXT: stw 6, 28(31) -; AIX-NEXT: stw 7, 24(31) +; AIX-NEXT: stw 5, 36(31) +; AIX-NEXT: stw 6, 32(31) +; AIX-NEXT: stw 7, 28(31) +; AIX-NEXT: stw 8, 24(31) ; AIX-NEXT: addi 1, 1, 48 ; AIX-NEXT: lwz 31, -4(1) ; AIX-NEXT: blr diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected index 601abc548a45e..ee87feec40151 100644 --- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected +++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ppc_generated_funcs.ll.nogenerated.expected @@ -116,24 +116,23 @@ define dso_local i32 @main() #0 { ; CHECK-NEXT: mr 31, 1 ; CHECK-NEXT: .cfi_def_cfa_register r31 ; CHECK-NEXT: li 3, 0 +; CHECK-NEXT: li 4, 1 +; CHECK-NEXT: li 5, 2 +; CHECK-NEXT: li 6, 3 +; CHECK-NEXT: li 7, 4 +; CHECK-NEXT: lis 8, x@ha ; CHECK-NEXT: stw 3, 24(31) -; CHECK-NEXT: li 3, 1 -; CHECK-NEXT: li 4, 2 -; CHECK-NEXT: li 5, 3 -; CHECK-NEXT: li 6, 4 -; CHECK-NEXT: lis 7, x@ha -; CHECK-NEXT: stw 3, 20(31) -; CHECK-NEXT: stw 4, 16(31) -; CHECK-NEXT: stw 5, 12(31) -; CHECK-NEXT: stw 6, 8(31) -; CHECK-NEXT: stw 3, x@l(7) +; CHECK-NEXT: stw 4, 20(31) +; CHECK-NEXT: stw 5, 16(31) +; CHECK-NEXT: stw 6, 12(31) +; CHECK-NEXT: stw 7, 8(31) +; CHECK-NEXT: stw 4, x@l(8) ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: stw 3, 20(31) -; CHECK-NEXT: li 3, 0 -; CHECK-NEXT: stw 4, 16(31) -; CHECK-NEXT: stw 5, 12(31) -; CHECK-NEXT: stw 6, 8(31) +; CHECK-NEXT: stw 4, 20(31) +; CHECK-NEXT: stw 5, 16(31) +; CHECK-NEXT: stw 6, 12(31) +; CHECK-NEXT: stw 7, 8(31) ; CHECK-NEXT: lwz 31, 28(1) ; CHECK-NEXT: addi 1, 1, 32 ; CHECK-NEXT: blr @@ -145,23 +144,22 @@ define dso_local i32 @main() #0 { ; AIX-NEXT: lwz 4, L..C0(2) # @x ; AIX-NEXT: mr 31, 1 ; AIX-NEXT: li 3, 0 +; AIX-NEXT: li 5, 1 +; AIX-NEXT: li 6, 2 +; AIX-NEXT: li 7, 3 +; AIX-NEXT: li 8, 4 ; AIX-NEXT: stw 3, 40(31) -; AIX-NEXT: li 3, 1 -; AIX-NEXT: li 5, 2 -; AIX-NEXT: li 6, 3 -; AIX-NEXT: li 7, 4 -; AIX-NEXT: stw 3, 36(31) -; AIX-NEXT: stw 5, 32(31) -; AIX-NEXT: stw 6, 28(31) -; AIX-NEXT: stw 7, 24(31) -; AIX-NEXT: stw 3, 0(4) +; AIX-NEXT: stw 5, 36(31) +; AIX-NEXT: stw 6, 32(31) +; AIX-NEXT: stw 7, 28(31) +; AIX-NEXT: stw 8, 24(31) +; AIX-NEXT: stw 5, 0(4) ; AIX-NEXT: #APP ; AIX-NEXT: #NO_APP -; AIX-NEXT: stw 3, 36(31) -; AIX-NEXT: li 3, 0 -; AIX-NEXT: stw 5, 32(31) -; AIX-NEXT: stw 6, 28(31) -; AIX-NEXT: stw 7, 24(31) +; AIX-NEXT: stw 5, 36(31) +; AIX-NEXT: stw 6, 32(31) +; AIX-NEXT: stw 7, 28(31) +; AIX-NEXT: stw 8, 24(31) ; AIX-NEXT: addi 1, 1, 48 ; AIX-NEXT: lwz 31, -4(1) ; AIX-NEXT: blr