From 28c8a6c4ea55d96d929da5cd3c76bb09305d7071 Mon Sep 17 00:00:00 2001 From: tomershafir Date: Sun, 12 Oct 2025 14:48:37 +0300 Subject: [PATCH 1/3] [AArch64] Improve lowering of GPR zeroing in copyPhysReg This patch pivots GPR32 and GPR64 zeroing into distinct branches to simplify the code an improve the lowering. Zeroing GPR moves are now handled differently than non-zeroing ones. Zero source registers WZR and XZR do not require register annotations of undef, implicit and kill. The non-zeroing source now cannot process WZR removing the ternary expression. This patch also moves GPR64 logic right after GPR32 for better organization. --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 79 +++++++++++-------- .../AArch64/arm64-copy-phys-zero-reg.mir | 4 +- 2 files changed, 50 insertions(+), 33 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 12c600f0f2661..84b54b3c707af 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -5063,7 +5063,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, bool RenamableDest, bool RenamableSrc) const { if (AArch64::GPR32spRegClass.contains(DestReg) && - (AArch64::GPR32spRegClass.contains(SrcReg) || SrcReg == AArch64::WZR)) { + AArch64::GPR32spRegClass.contains(SrcReg)) { if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { // If either operand is WSP, expand to ADD #0. if (Subtarget.hasZeroCycleRegMoveGPR64() && @@ -5088,21 +5088,14 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, .addImm(0) .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); } - } else if (SrcReg == AArch64::WZR && Subtarget.hasZeroCycleZeroingGPR32()) { - BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg) - .addImm(0) - .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); } else if (Subtarget.hasZeroCycleRegMoveGPR64() && !Subtarget.hasZeroCycleRegMoveGPR32()) { // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move. MCRegister DestRegX = RI.getMatchingSuperReg(DestReg, AArch64::sub_32, &AArch64::GPR64spRegClass); assert(DestRegX.isValid() && "Destination super-reg not valid"); - MCRegister SrcRegX = - SrcReg == AArch64::WZR - ? AArch64::XZR - : RI.getMatchingSuperReg(SrcReg, AArch64::sub_32, - &AArch64::GPR64spRegClass); + MCRegister SrcRegX = RI.getMatchingSuperReg(SrcReg, AArch64::sub_32, + &AArch64::GPR64spRegClass); assert(SrcRegX.isValid() && "Source super-reg not valid"); // This instruction is reading and writing X registers. This may upset // the register scavenger and machine verifier, so we need to indicate @@ -5121,6 +5114,51 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } + // GPR32 zeroing + if (AArch64::GPR32spRegClass.contains(DestReg) && SrcReg == AArch64::WZR) { + if (Subtarget.hasZeroCycleZeroingGPR32()) { + BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } else { + BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg) + .addReg(AArch64::WZR) + .addReg(AArch64::WZR); + } + return; + } + + if (AArch64::GPR64spRegClass.contains(DestReg) && + AArch64::GPR64spRegClass.contains(SrcReg)) { + if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { + // If either operand is SP, expand to ADD #0. + BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } else { + // Otherwise, expand to ORR XZR. + BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) + .addReg(AArch64::XZR) + .addReg(SrcReg, getKillRegState(KillSrc)); + } + return; + } + + // GPR64 zeroing + if (AArch64::GPR64spRegClass.contains(DestReg) && SrcReg == AArch64::XZR) { + if (Subtarget.hasZeroCycleZeroingGPR64()) { + BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg) + .addImm(0) + .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); + } else { + BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) + .addReg(AArch64::XZR) + .addReg(AArch64::XZR); + } + return; + } + // Copy a Predicate register by ORRing with itself. if (AArch64::PPRRegClass.contains(DestReg) && AArch64::PPRRegClass.contains(SrcReg)) { @@ -5205,27 +5243,6 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB, return; } - if (AArch64::GPR64spRegClass.contains(DestReg) && - (AArch64::GPR64spRegClass.contains(SrcReg) || SrcReg == AArch64::XZR)) { - if (DestReg == AArch64::SP || SrcReg == AArch64::SP) { - // If either operand is SP, expand to ADD #0. - BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg) - .addReg(SrcReg, getKillRegState(KillSrc)) - .addImm(0) - .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); - } else if (SrcReg == AArch64::XZR && Subtarget.hasZeroCycleZeroingGPR64()) { - BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg) - .addImm(0) - .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0)); - } else { - // Otherwise, expand to ORR XZR. - BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg) - .addReg(AArch64::XZR) - .addReg(SrcReg, getKillRegState(KillSrc)); - } - return; - } - // Copy a DDDD register quad by copying the individual sub-registers. if (AArch64::DDDDRegClass.contains(DestReg) && AArch64::DDDDRegClass.contains(SrcReg)) { diff --git a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir index 284d624a4e68f..dc9eaad2c9834 100644 --- a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir +++ b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir @@ -39,7 +39,7 @@ body: | ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f0 ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, undef $xzr, implicit $wzr + ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f0 @@ -103,7 +103,7 @@ body: | ; CHECK-ZCM-ZCZ: liveins: $x0, $lr ; CHECK-ZCM-ZCZ-NEXT: {{ $}} ; CHECK-ZCM-ZCZ-NEXT: $x0 = MOVZXi 0, 0 - ; CHECK-ZCM-ZCZ-NEXT:BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 $x0 = COPY $xzr BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ... From 60a63f4c4efb13b85867e442dd9e5754b8c1c0c7 Mon Sep 17 00:00:00 2001 From: tomershafir Date: Fri, 17 Oct 2025 17:26:11 +0300 Subject: [PATCH 2/3] Check all ZCZ combos and remove ZCM dependency --- .../AArch64/arm64-copy-phys-zero-reg.mir | 126 +++++++----------- 1 file changed, 49 insertions(+), 77 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir index dc9eaad2c9834..614e5a8ae11f3 100644 --- a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir +++ b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir @@ -1,16 +1,12 @@ -# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 -# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcm-gpr32,-zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ %s -# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcm-gpr32,-zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ %s -# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcm-gpr32,+zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ %s -# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcm-gpr32,+zcm-gpr64,-zcz-gpr32,-zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ %s -# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcm-gpr32,-zcm-gpr64,+zcz-gpr32,+zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-NO-ZCM-ZCZ %s -# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcm-gpr32,+zcm-gpr64,+zcz-gpr32,+zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-ZCM-ZCZ %s +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcz-gpr32,-zcz-gpr64" %s \ +# RUN: | FileCheck --check-prefix=CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64 %s +# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcz-gpr32,-zcz-gpr64" %s \ +# RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-NO-ZCZ-GPR64 %s +# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcz-gpr32,+zcz-gpr64" %s \ +# RUN: | FileCheck --check-prefix=CHECK-NO-ZCZ-GPR32-ZCZ-GPR64 %s +# RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcz-gpr32,+zcz-gpr64" %s \ +# RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-ZCZ-GPR64 %s --- | define void @f0(i64 noundef %x) { ret void } @@ -24,41 +20,29 @@ liveins: body: | bb.0: liveins: $x0, $lr - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f0 - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f0 + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f0 - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f0 + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $w0 = MOVZWi 0, 0 + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f0 - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f0 - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $w0 = ORRWrr $wzr, $wzr - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 - ; - ; CHECK-NO-ZCM-ZCZ-LABEL: name: f0 - ; CHECK-NO-ZCM-ZCZ: liveins: $x0, $lr - ; CHECK-NO-ZCM-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-ZCZ-NEXT: $w0 = MOVZWi 0, 0 - ; CHECK-NO-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 - ; - ; CHECK-ZCM-ZCZ-LABEL: name: f0 - ; CHECK-ZCM-ZCZ: liveins: $x0, $lr - ; CHECK-ZCM-ZCZ-NEXT: {{ $}} - ; CHECK-ZCM-ZCZ-NEXT: $w0 = MOVZWi 0, 0 - ; CHECK-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 + ; CHECK-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = MOVZWi 0, 0 + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 $w0 = COPY $wzr BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ... @@ -69,41 +53,29 @@ liveins: body: | bb.0: liveins: $x0, $lr - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f1 - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr - ; CHECK-NO-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 - ; - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-LABEL: name: f1 - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr - ; CHECK-ZCM-GPR32-NO-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 - ; - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f1 - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr - ; CHECK-NO-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f1 + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr + ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-LABEL: name: f1 - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ: liveins: $x0, $lr - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: {{ $}} - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: $x0 = ORRXrr $xzr, $xzr - ; CHECK-ZCM-GPR32-ZCM-GPR64-NO-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f1 + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr + ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-NO-ZCM-ZCZ-LABEL: name: f1 - ; CHECK-NO-ZCM-ZCZ: liveins: $x0, $lr - ; CHECK-NO-ZCM-ZCZ-NEXT: {{ $}} - ; CHECK-NO-ZCM-ZCZ-NEXT: $x0 = MOVZXi 0, 0 - ; CHECK-NO-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1 + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0 + ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-ZCM-ZCZ-LABEL: name: f1 - ; CHECK-ZCM-ZCZ: liveins: $x0, $lr - ; CHECK-ZCM-ZCZ-NEXT: {{ $}} - ; CHECK-ZCM-ZCZ-NEXT: $x0 = MOVZXi 0, 0 - ; CHECK-ZCM-ZCZ-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1 + ; CHECK-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0 + ; CHECK-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 $x0 = COPY $xzr BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ... From b65c92cbae2e14bbf2f660097bce5999defa8128 Mon Sep 17 00:00:00 2001 From: tomershafir Date: Mon, 20 Oct 2025 10:46:35 +0300 Subject: [PATCH 3/3] Rename NO-ZCZ to simpler NOZCZ --- .../AArch64/arm64-copy-phys-zero-reg.mir | 66 +++++++++---------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir index 614e5a8ae11f3..f34d3ed510a97 100644 --- a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir +++ b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir @@ -1,10 +1,10 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcz-gpr32,-zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64 %s +# RUN: | FileCheck --check-prefix=CHECK-NOZCZ-GPR32-NOZCZ-GPR64 %s # RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcz-gpr32,-zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-NO-ZCZ-GPR64 %s +# RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-NOZCZ-GPR64 %s # RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="-zcz-gpr32,+zcz-gpr64" %s \ -# RUN: | FileCheck --check-prefix=CHECK-NO-ZCZ-GPR32-ZCZ-GPR64 %s +# RUN: | FileCheck --check-prefix=CHECK-NOZCZ-GPR32-ZCZ-GPR64 %s # RUN: llc -o - -mtriple=arm64-apple-ios -run-pass=postrapseudos -simplify-mir -verify-machineinstrs -mattr="+zcz-gpr32,+zcz-gpr64" %s \ # RUN: | FileCheck --check-prefix=CHECK-ZCZ-GPR32-ZCZ-GPR64 %s @@ -20,23 +20,23 @@ liveins: body: | bb.0: liveins: $x0, $lr - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f0 - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f0 + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f0 - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $w0 = MOVZWi 0, 0 - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f0 + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}} + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: $w0 = MOVZWi 0, 0 + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; ; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 ; CHECK-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr @@ -53,23 +53,23 @@ liveins: body: | bb.0: liveins: $x0, $lr - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f1 - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr - ; CHECK-NO-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f1 + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr + ; CHECK-NOZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-LABEL: name: f1 - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64: liveins: $x0, $lr - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr - ; CHECK-ZCZ-GPR32-NO-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-LABEL: name: f1 + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64: liveins: $x0, $lr + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: {{ $}} + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: $x0 = ORRXrr $xzr, $xzr + ; CHECK-ZCZ-GPR32-NOZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1 - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0 - ; CHECK-NO-ZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1 + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0 + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; ; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f1 ; CHECK-ZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr