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[DAGCombiner] Remove NoNaNsFPMath uses #163504

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Merged
merged 1 commit into from
Oct 15, 2025
Merged

[DAGCombiner] Remove NoNaNsFPMath uses #163504

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10 changes: 3 additions & 7 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17759,7 +17759,6 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
bool N1CFP = DAG.isConstantFPBuildVectorOrConstantFP(N1);
EVT VT = N->getValueType(0);
SDLoc DL(N);
const TargetOptions &Options = DAG.getTarget().Options;
SDNodeFlags Flags = N->getFlags();
SelectionDAG::FlagInserter FlagsInserter(DAG, N);

Expand Down Expand Up @@ -17825,7 +17824,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) {
bool AllowNewConst = (Level < AfterLegalizeDAG);

// If nnan is enabled, fold lots of things.
if ((Options.NoNaNsFPMath || Flags.hasNoNaNs()) && AllowNewConst) {
if (Flags.hasNoNaNs() && AllowNewConst) {
// If allowed, fold (fadd (fneg x), x) -> 0.0
if (N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
return DAG.getConstantFP(0.0, DL, VT);
Expand Down Expand Up @@ -17974,7 +17973,6 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1, true);
EVT VT = N->getValueType(0);
SDLoc DL(N);
const TargetOptions &Options = DAG.getTarget().Options;
const SDNodeFlags Flags = N->getFlags();
SelectionDAG::FlagInserter FlagsInserter(DAG, N);

Expand Down Expand Up @@ -18002,7 +18000,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {

if (N0 == N1) {
// (fsub x, x) -> 0.0
if (Options.NoNaNsFPMath || Flags.hasNoNaNs())
if (Flags.hasNoNaNs())
return DAG.getConstantFP(0.0f, DL, VT);
}

Expand Down Expand Up @@ -18313,7 +18311,6 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
EVT VT = N->getValueType(0);
SDLoc DL(N);
const TargetOptions &Options = DAG.getTarget().Options;
// FMA nodes have flags that propagate to the created nodes.
SelectionDAG::FlagInserter FlagsInserter(DAG, N);
MatchContextClass matcher(DAG, TLI, N);
Expand All @@ -18339,8 +18336,7 @@ template <class MatchContextClass> SDValue DAGCombiner::visitFMA(SDNode *N) {
return matcher.getNode(ISD::FMA, DL, VT, NegN0, NegN1, N2);
}

if ((Options.NoNaNsFPMath && N->getFlags().hasNoInfs()) ||
(N->getFlags().hasNoNaNs() && N->getFlags().hasNoInfs())) {
if (N->getFlags().hasNoNaNs() && N->getFlags().hasNoInfs()) {
if (N->getFlags().hasNoSignedZeros() ||
(N2CFP && !N2CFP->isExactlyValue(-0.0))) {
if (N0CFP && N0CFP->isZero())
Expand Down
20 changes: 12 additions & 8 deletions llvm/test/CodeGen/ARM/nnan-fsub.ll
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Original file line number Diff line number Diff line change
@@ -1,18 +1,22 @@
; RUN: llc -mcpu=cortex-a9 < %s | FileCheck -check-prefix=SAFE %s
; RUN: llc -mcpu=cortex-a9 --enable-no-nans-fp-math < %s | FileCheck -check-prefix=FAST %s
; RUN: llc -mcpu=cortex-a9 < %s | FileCheck %s

target triple = "armv7-apple-ios"

; SAFE: test
; FAST: test
; CHECK-LABEL: test
define float @test(float %x, float %y) {
entry:
; SAFE: vmul.f32
; SAFE: vsub.f32
; FAST: mov r0, #0
; CHECK: vmul.f32
; CHECK-NEXT: vsub.f32
%0 = fmul float %x, %y
%1 = fsub float %0, %0
ret float %1
}


; CHECK-LABEL: test_nnan
define float @test_nnan(float %x, float %y) {
entry:
; CHECK: mov r0, #0
%0 = fmul float %x, %y
%1 = fsub nnan float %0, %0
ret float %1
}