diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 50447f48a628c..5e3eb8175ab16 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -845,6 +845,14 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
     }
   }
 
+  if (AMDGPU::APERTURE_ClassRegClass.contains(DestReg)) {
+    if (SrcReg == AMDGPU::VCC) {
+      BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
+          .addReg(SrcReg, getKillRegState(KillSrc));
+      return;
+    }
+  }
+
   if (RC == &AMDGPU::VGPR_32RegClass) {
     assert(AMDGPU::VGPR_32RegClass.contains(SrcReg) ||
            AMDGPU::SReg_32RegClass.contains(SrcReg) ||
diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
index f11fe4aa6e00e..78e8788c7f0f0 100644
--- a/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
+++ b/llvm/test/CodeGen/AMDGPU/sgpr-phys-copy.mir
@@ -67,6 +67,15 @@ body:             |
     $vcc = COPY $src_shared_base
 ...
 
+---
+name: vcc_to_src_shared_base
+body:             |
+  bb.0:
+    ; GFX9-LABEL: name: vcc_to_src_shared_base
+    ; GFX9: $src_shared_base = S_MOV_B64 $vcc
+    $src_shared_base = COPY $vcc
+...
+
 ---
 name: sgpr96_aligned_src_dst
 body:             |