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@llvmbot llvmbot added clang Clang issues not falling into any other category backend:RISC-V backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang:codegen IR generation bugs: mangling, exceptions, etc. llvm:ir labels Oct 23, 2025
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llvmbot commented Oct 23, 2025

@llvm/pr-subscribers-clang-codegen
@llvm/pr-subscribers-backend-risc-v
@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-llvm-ir

Author: None (t-baydyusenov)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/164822.diff

8 Files Affected:

  • (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+7)
  • (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+6)
  • (modified) clang/lib/Headers/CMakeLists.txt (+1)
  • (added) clang/lib/Headers/riscv_cmo.h (+30)
  • (added) clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-invalid.c (+12)
  • (added) clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-valid.c (+13)
  • (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+9-2)
  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td (+1)
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 2dad5ede2d64b..91a2fea8a8a03 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -153,6 +153,13 @@ def ntl_store : RISCVBuiltin<"void(...)">;
 let Features = "zihintpause", Attributes = [NoThrow] in
 def pause : RISCVBuiltin<"void()">;
 
+//===----------------------------------------------------------------------===//
+// Zicboz extension.
+//===----------------------------------------------------------------------===//
+let Features = "zicboz" in {
+def cbo_zero : RISCVBuiltin<"void(void *)">;
+} // Features = "zicboz"
+
 //===----------------------------------------------------------------------===//
 // XCV extensions.
 //===----------------------------------------------------------------------===//
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index 920d28561fc2a..acf04fe0ec2a2 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1296,6 +1296,12 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned BuiltinID,
     return Builder.CreateCall(Fn, {});
   }
 
+  // Zicboz
+  case RISCV::BI__builtin_riscv_cbo_zero:
+    ID = Intrinsic::riscv_cbo_zero;
+    IntrinsicTypes = {Int8PtrTy};
+    break;
+
   // XCValu
   case RISCV::BI__builtin_riscv_cv_alu_addN:
     ID = Intrinsic::riscv_cv_alu_addN;
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index 32a6be88abc20..dcad17e8f5979 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -125,6 +125,7 @@ set(ppc_htm_files
 
 set(riscv_files
   riscv_bitmanip.h
+  riscv_cmo.h
   riscv_corev_alu.h
   riscv_crypto.h
   riscv_nds.h
diff --git a/clang/lib/Headers/riscv_cmo.h b/clang/lib/Headers/riscv_cmo.h
new file mode 100644
index 0000000000000..26810c4c7c19d
--- /dev/null
+++ b/clang/lib/Headers/riscv_cmo.h
@@ -0,0 +1,30 @@
+/*===---- riscv_cmo.h - RISC-V CMO intrinsics ----------------------------===
+ *
+ * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ * See https://llvm.org/LICENSE.txt for license information.
+ * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __RISCV_CMO_H
+#define __RISCV_CMO_H
+
+#include <stdint.h>
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if defined(__riscv_zicboz)
+static __inline__ void __attribute__((__always_inline__, __nodebug__))
+__riscv_cbo_zero(void *__x) {
+  return __builtin_riscv_cbo_zero(__x);
+}
+#endif // defined(__riscv_zicboz)
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // define __RISCV_CMO_H
diff --git a/clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-invalid.c b/clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-invalid.c
new file mode 100644
index 0000000000000..358c005e6fdd3
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-invalid.c
@@ -0,0 +1,12 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zicboz \
+// RUN:   -Wall -Wno-unused -Werror -fsyntax-only -verify %s
+
+#include <riscv_cmo.h>
+
+void test(void *x) {
+	__riscv_cbo_zero(x, 0); // expected-error{{too many arguments to function call, expected single argument '__x', have 2 arguments}} expected-note@riscv_cmo.h:* {{'__riscv_cbo_zero' declared here}}
+	int res = __riscv_cbo_zero(x); // expected-error{{initializing 'int' with an expression of incompatible type 'void'}}
+	__riscv_cbo_zero(42); // expected-error{{incompatible integer to pointer conversion passing 'int' to parameter of type 'void *'}} expected-note@riscv_cmo.h:* {{passing argument to parameter '__x' here}}
+}
+
diff --git a/clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-valid.c b/clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-valid.c
new file mode 100644
index 0000000000000..a73e4eabd850f
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/riscv-zicbo-intrinsics/cbo-zero-valid.c
@@ -0,0 +1,13 @@
+
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zicboz -O2 -S -o - %s | FileCheck %s
+
+#include <riscv_cmo.h>
+
+void test(void *x) {
+// CHECK-LABEL: test:
+// CHECK:       cbo.zero (a0)
+// CHECK:       ret
+  __riscv_cbo_zero(x);
+}
+
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 77fcc46ea5a89..1a62608cea61e 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1953,13 +1953,20 @@ let TargetPrefix = "riscv" in {
 } // TargetPrefix = "riscv"
 
 
-// Zihintpause extensions
 //===----------------------------------------------------------------------===//
+// Zihintpause extensions
 let TargetPrefix = "riscv" in
 def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
 
-// Vendor extensions
 //===----------------------------------------------------------------------===//
+// Cache Management
+let TargetPrefix = "riscv" in {
+// Zicboz
+def int_riscv_cbo_zero : Intrinsic<[], [llvm_anyptr_ty], [IntrWriteMem]>;
+} // TargetPrefix = "riscv"
+
+//===----------------------------------------------------------------------===//
+// Vendor extensions
 include "llvm/IR/IntrinsicsRISCVXTHead.td"
 include "llvm/IR/IntrinsicsRISCVXsf.td"
 include "llvm/IR/IntrinsicsRISCVXCV.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
index 3ddcb1d615dbb..cea2a90ba0675 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZicbo.td
@@ -56,6 +56,7 @@ def CBO_INVAL : CBO_r<0b000000000000, "cbo.inval">, Sched<[]>;
 
 let Predicates = [HasStdExtZicboz] in {
 def CBO_ZERO : CBO_r<0b000000000100, "cbo.zero">, Sched<[]>;
+def : Pat<(int_riscv_cbo_zero GPR:$rs1), (CBO_ZERO GPR:$rs1)>;
 } // Predicates = [HasStdExtZicboz]
 
 let Predicates = [HasStdExtZicbop, NoVendorXMIPSCBOP] in {

@t-baydyusenov t-baydyusenov force-pushed the t.baydyusenov/add-intrinsic-support-for-cbo.zero branch from a4a7401 to f4e5019 Compare October 23, 2025 14:06
@t-baydyusenov t-baydyusenov changed the title [LLVM][clang] Add intrinsic support for cbo.zero instruction (Zicboz ISA extension) [llvm][clang] Add intrinsic support for cbo.zero instruction (Zicboz ISA extension) Oct 23, 2025
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@ukalappa-mips @tclin914 @lenary could you please review

#ifndef __RISCV_CMO_H
#define __RISCV_CMO_H

#include <stdint.h>
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Is this header needed?

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Addressed

@t-baydyusenov t-baydyusenov force-pushed the t.baydyusenov/add-intrinsic-support-for-cbo.zero branch from f4e5019 to 11e34be Compare October 23, 2025 16:00
@t-baydyusenov t-baydyusenov force-pushed the t.baydyusenov/add-intrinsic-support-for-cbo.zero branch from 11e34be to a6a9b13 Compare October 23, 2025 16:01
@jrtc27
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jrtc27 commented Oct 23, 2025

AFAIK other architectures don't bother to expose their equivalents as intrinsics. Why should RISC-V? (e.g. there's no DC ZVA intrinsic that I know of for AArch64)

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@jrtc27 I think there is no direct equivalent for this intrinsic in backend, which would be automatically generated. Now, without using inline assembler, we can't get cbo.zero.

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lenary commented Oct 23, 2025

Is there a proposal for this on the C API Doc? Without it we shouldn't land this.

Maybe we shouldn't have this at all (instead of making people use inline asm)? What optimisations would we expect with this instruction, that means we couldn't use inline asm?

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I agree with others, I can't image many scenarios that this intrinsics can be useful. We can use it in the implementation of memset 0 but you still need to handle the memory alignment. I tried to generate cbo.zero during ISel last year, but it didn't make any big difference. Inline assembly should be fine.

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6 participants