diff --git a/llvm/test/CodeGen/RISCV/machine-licm-loop-inv-loads.mir b/llvm/test/CodeGen/RISCV/machine-licm-loop-inv-loads.mir
new file mode 100644
index 0000000000000..e54ae162cca92
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/machine-licm-loop-inv-loads.mir
@@ -0,0 +1,119 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=riscv64 -x mir -run-pass=machinelicm -simplify-mir -verify-machineinstrs < %s | FileCheck  %s
+
+---
+name:            invariant_load
+tracksRegLiveness: true
+constants:
+  - id:              0
+    value:           i64 -1085102592571150096
+    alignment:       8
+    isTargetSpecific: false
+body:             |
+  ; CHECK-LABEL: name: invariant_load
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   liveins: $x10, $x11
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %base_addr:gpr = COPY $x10
+  ; CHECK-NEXT:   %n:gpr = COPY $x11
+  ; CHECK-NEXT:   %i_0:gpr = COPY $x0
+  ; CHECK-NEXT:   %const_pool_addr_upper:gpr = LUI target-flags(riscv-hi) %const.0
+  ; CHECK-NEXT:   %invariant_load:gpr = LD %const_pool_addr_upper, target-flags(riscv-lo) %const.0 :: (load (s64) from constant-pool)
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   %offset:gpr = PHI %i_inc, %bb.1, %i_0, %bb.0
+  ; CHECK-NEXT:   %addr:gpr = ADD %base_addr, %offset
+  ; CHECK-NEXT:   %x:gpr = LW %addr, 0
+  ; CHECK-NEXT:   %val:gpr = ADD %x, %invariant_load
+  ; CHECK-NEXT:   SW %val, %addr, 0
+  ; CHECK-NEXT:   %i_inc:gpr = ADDI %offset, 4
+  ; CHECK-NEXT:   BLT %i_inc, %n, %bb.1
+  ; CHECK-NEXT:   PseudoBR %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   PseudoRET
+  bb.0:
+    successors: %bb.1
+    liveins: $x10, $x11
+
+    %base_addr:gpr = COPY $x10
+    %n:gpr = COPY $x11
+    %i_0:gpr = COPY $x0
+    PseudoBR %bb.1
+
+  bb.1:
+    %offset:gpr = PHI %i_inc, %bb.1, %i_0, %bb.0
+    %addr:gpr = ADD %base_addr, %offset
+    %x:gpr = LW %addr, 0
+
+    %const_pool_addr_upper:gpr = LUI target-flags(riscv-hi) %const.0
+    %invariant_load:gpr = LD %const_pool_addr_upper, target-flags(riscv-lo) %const.0 :: (load (s64) from constant-pool)
+    %val:gpr = ADD %x, %invariant_load
+    SW %val, %addr, 0
+    %i_inc:gpr = ADDI %offset, 4
+    BLT %i_inc, %n, %bb.1
+    PseudoBR %bb.2
+
+  bb.2:
+    PseudoRET
+...
+
+# Do not hoist load out of the loop, because %other_addr may alias with %addr
+---
+name:            not_invariant_load
+tracksRegLiveness: true
+constants:
+  - id:              0
+    value:           i64 -1085102592571150096
+    alignment:       8
+    isTargetSpecific: false
+body:             |
+  ; CHECK-LABEL: name: not_invariant_load
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   liveins: $x10, $x11, $x12
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   %base_addr:gpr = COPY $x10
+  ; CHECK-NEXT:   %n:gpr = COPY $x11
+  ; CHECK-NEXT:   %other_addr:gpr = COPY $x12
+  ; CHECK-NEXT:   %i_0:gpr = COPY $x0
+  ; CHECK-NEXT:   PseudoBR %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   %offset:gpr = PHI %i_inc, %bb.1, %i_0, %bb.0
+  ; CHECK-NEXT:   %addr:gpr = ADD %base_addr, %offset
+  ; CHECK-NEXT:   %x:gpr = LW %addr, 0
+  ; CHECK-NEXT:   %load_may_alias:gpr = LD %other_addr, 0
+  ; CHECK-NEXT:   %val:gpr = ADD %x, %load_may_alias
+  ; CHECK-NEXT:   SW %val, %addr, 0
+  ; CHECK-NEXT:   %i_inc:gpr = ADDI %offset, 4
+  ; CHECK-NEXT:   BLT %i_inc, %n, %bb.1
+  ; CHECK-NEXT:   PseudoBR %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   PseudoRET
+  bb.0:
+    successors: %bb.1
+    liveins: $x10, $x11, $x12
+
+    %base_addr:gpr = COPY $x10
+    %n:gpr = COPY $x11
+    %other_addr:gpr = COPY $x12
+    %i_0:gpr = COPY $x0
+    PseudoBR %bb.1
+
+  bb.1:
+    %offset:gpr = PHI %i_inc, %bb.1, %i_0, %bb.0
+    %addr:gpr = ADD %base_addr, %offset
+    %x:gpr = LW %addr, 0
+
+    %load_may_alias:gpr = LD %other_addr, 0
+    %val:gpr = ADD %x, %load_may_alias
+    SW %val, %addr, 0
+    %i_inc:gpr = ADDI %offset, 4
+    BLT %i_inc, %n, %bb.1
+    PseudoBR %bb.2
+
+  bb.2:
+    PseudoRET
+...