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[X86] vector-reduce-or-cmp.ll - add v4i64 signbit test coverage #165588
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Missing fold to make use of VTESTPD
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@llvm/pr-subscribers-backend-x86 Author: Simon Pilgrim (RKSimon) ChangesMissing fold to make use of VTESTPD Full diff: https://github.com/llvm/llvm-project/pull/165588.diff 1 Files Affected:
diff --git a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
index ab1feba98b008..9816fa7c83560 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-or-cmp.ll
@@ -992,6 +992,51 @@ define i1 @signtest_v8i32(<8 x i32> %a0) {
ret i1 %2
}
+define i1 @signtest_v4i64(<4 x i64> %a0) {
+; SSE2-LABEL: signtest_v4i64:
+; SSE2: # %bb.0:
+; SSE2-NEXT: por %xmm1, %xmm0
+; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; SSE2-NEXT: por %xmm0, %xmm1
+; SSE2-NEXT: movq %xmm1, %rax
+; SSE2-NEXT: testq %rax, %rax
+; SSE2-NEXT: setns %al
+; SSE2-NEXT: retq
+;
+; SSE41-LABEL: signtest_v4i64:
+; SSE41: # %bb.0:
+; SSE41-NEXT: por %xmm1, %xmm0
+; SSE41-NEXT: ptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE41-NEXT: sete %al
+; SSE41-NEXT: retq
+;
+; AVX1-LABEL: signtest_v4i64:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vptest {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0
+; AVX1-NEXT: sete %al
+; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: signtest_v4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; AVX2-NEXT: vptest %ymm1, %ymm0
+; AVX2-NEXT: sete %al
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: signtest_v4i64:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpbroadcastq {{.*#+}} ymm1 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
+; AVX512-NEXT: vptest %ymm1, %ymm0
+; AVX512-NEXT: sete %al
+; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: retq
+ %1 = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %a0)
+ %2 = icmp sgt i64 %1, -1
+ ret i1 %2
+}
+
define i1 @trunc_v16i16(<16 x i16> %a0) {
; SSE2-LABEL: trunc_v16i16:
; SSE2: # %bb.0:
@@ -1162,11 +1207,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; SSE2-NEXT: movd %xmm0, %eax
; SSE2-NEXT: orl %ecx, %eax
; SSE2-NEXT: testb $1, %al
-; SSE2-NEXT: je .LBB29_2
+; SSE2-NEXT: je .LBB30_2
; SSE2-NEXT: # %bb.1:
; SSE2-NEXT: xorl %eax, %eax
; SSE2-NEXT: retq
-; SSE2-NEXT: .LBB29_2:
+; SSE2-NEXT: .LBB30_2:
; SSE2-NEXT: movl $1, %eax
; SSE2-NEXT: retq
;
@@ -1181,11 +1226,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; SSE41-NEXT: pextrd $2, %xmm1, %eax
; SSE41-NEXT: orl %ecx, %eax
; SSE41-NEXT: testb $1, %al
-; SSE41-NEXT: je .LBB29_2
+; SSE41-NEXT: je .LBB30_2
; SSE41-NEXT: # %bb.1:
; SSE41-NEXT: xorl %eax, %eax
; SSE41-NEXT: retq
-; SSE41-NEXT: .LBB29_2:
+; SSE41-NEXT: .LBB30_2:
; SSE41-NEXT: movl $1, %eax
; SSE41-NEXT: retq
;
@@ -1200,11 +1245,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX1OR2-NEXT: vpextrd $2, %xmm0, %eax
; AVX1OR2-NEXT: orl %ecx, %eax
; AVX1OR2-NEXT: testb $1, %al
-; AVX1OR2-NEXT: je .LBB29_2
+; AVX1OR2-NEXT: je .LBB30_2
; AVX1OR2-NEXT: # %bb.1:
; AVX1OR2-NEXT: xorl %eax, %eax
; AVX1OR2-NEXT: retq
-; AVX1OR2-NEXT: .LBB29_2:
+; AVX1OR2-NEXT: .LBB30_2:
; AVX1OR2-NEXT: movl $1, %eax
; AVX1OR2-NEXT: retq
;
@@ -1219,12 +1264,12 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512F-NEXT: korw %k0, %k1, %k0
; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: testb $1, %al
-; AVX512F-NEXT: je .LBB29_2
+; AVX512F-NEXT: je .LBB30_2
; AVX512F-NEXT: # %bb.1:
; AVX512F-NEXT: xorl %eax, %eax
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
-; AVX512F-NEXT: .LBB29_2:
+; AVX512F-NEXT: .LBB30_2:
; AVX512F-NEXT: movl $1, %eax
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
@@ -1240,12 +1285,12 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512BW-NEXT: korw %k0, %k1, %k0
; AVX512BW-NEXT: kmovd %k0, %eax
; AVX512BW-NEXT: testb $1, %al
-; AVX512BW-NEXT: je .LBB29_2
+; AVX512BW-NEXT: je .LBB30_2
; AVX512BW-NEXT: # %bb.1:
; AVX512BW-NEXT: xorl %eax, %eax
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
-; AVX512BW-NEXT: .LBB29_2:
+; AVX512BW-NEXT: .LBB30_2:
; AVX512BW-NEXT: movl $1, %eax
; AVX512BW-NEXT: vzeroupper
; AVX512BW-NEXT: retq
@@ -1259,11 +1304,11 @@ define i32 @mask_v3i1(<3 x i32> %a, <3 x i32> %b) {
; AVX512BWVL-NEXT: korw %k0, %k1, %k0
; AVX512BWVL-NEXT: kmovd %k0, %eax
; AVX512BWVL-NEXT: testb $1, %al
-; AVX512BWVL-NEXT: je .LBB29_2
+; AVX512BWVL-NEXT: je .LBB30_2
; AVX512BWVL-NEXT: # %bb.1:
; AVX512BWVL-NEXT: xorl %eax, %eax
; AVX512BWVL-NEXT: retq
-; AVX512BWVL-NEXT: .LBB29_2:
+; AVX512BWVL-NEXT: .LBB30_2:
; AVX512BWVL-NEXT: movl $1, %eax
; AVX512BWVL-NEXT: retq
%1 = icmp ne <3 x i32> %a, %b
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/23/builds/15097 Here is the relevant piece of the build log for the reference |
…#165588) Missing fold to make use of VTESTPD
…#165588) Missing fold to make use of VTESTPD
Missing fold to make use of VTESTPD