diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 2550c2bee5f71..cbd68f64059f0 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -5576,8 +5576,8 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
   /// \param N Node to expand
   /// \param IsNegative indicate negated abs
   /// \returns The expansion result or SDValue() if it fails.
-  SDValue expandABS(SDNode *N, SelectionDAG &DAG,
-                    bool IsNegative = false) const;
+  virtual SDValue expandABS(SDNode *N, SelectionDAG &DAG,
+                            bool IsNegative = false) const;
 
   /// Expand ABDS/ABDU nodes. Expands vector/scalar ABDS/ABDU nodes.
   /// \param N Node to expand
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index f5081a9d2dd56..e95dbcf2bf7b3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -5287,6 +5287,27 @@ SDValue AMDGPUTargetLowering::performRcpCombine(SDNode *N,
   return DCI.DAG.getConstantFP(One / Val, SDLoc(N), N->getValueType(0));
 }
 
+SDValue AMDGPUTargetLowering::expandABS(SDNode *N, SelectionDAG &DAG,
+                                        bool IsNegative) const {
+  if (N->isDivergent() ||
+      (N->getValueType(0) != MVT::i8 && N->getValueType(0) != MVT::i16))
+    return TargetLowering::expandABS(N, DAG, IsNegative);
+
+  //(abs i8/i16 (i8/i16 op1)) -> (trunc i8/i16 (abs i32 (sext i32 (i8/i16
+  // op1))))
+  SDValue Src = N->getOperand(0);
+  SDLoc DL(Src);
+  SDValue SExtSrc = DAG.getSExtOrTrunc(Src, DL, MVT::i32);
+  SDValue ExtAbs = DAG.getNode(ISD::ABS, DL, MVT::i32, SExtSrc);
+  SDValue TruncResult =
+      DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), ExtAbs);
+
+  if (!IsNegative)
+    return TruncResult;
+
+  return DAG.getNegative(TruncResult, DL, N->getValueType(0));
+}
+
 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
                                                 DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
index bdaf48652d107..57ce10b8b582f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
@@ -45,6 +45,9 @@ class AMDGPUTargetLowering : public TargetLowering {
   /// original size will not change the value.
   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
 
+  virtual SDValue expandABS(SDNode *N, SelectionDAG &DAG,
+                            bool IsNegative = false) const override;
+
 protected:
   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
deleted file mode 100644
index 6facdfdec64ae..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
+++ /dev/null
@@ -1,600 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -o - < %s | FileCheck %s --check-prefixes=GFX,GFX6
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -o - < %s | FileCheck %s --check-prefixes=GFX,GFX8
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX10
-; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX1250
-
-declare i16 @llvm.abs.i16(i16, i1)
-declare i32 @llvm.abs.i32(i32, i1)
-declare i64 @llvm.abs.i64(i64, i1)
-declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)
-declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)
-declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
-declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
-declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
-
-define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
-; GFX6-LABEL: abs_sgpr_i16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_sext_i32_i16 s0, s0
-; GFX6-NEXT:    s_abs_i32 s0, s0
-; GFX6-NEXT:    ; return to shader part epilog
-;
-; GFX8-LABEL: abs_sgpr_i16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_sext_i32_i16 s0, s0
-; GFX8-NEXT:    s_abs_i32 s0, s0
-; GFX8-NEXT:    ; return to shader part epilog
-;
-; GFX10-LABEL: abs_sgpr_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sext_i32_i16 s0, s0
-; GFX10-NEXT:    s_abs_i32 s0, s0
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX1250-LABEL: abs_sgpr_i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_sext_i32_i16 s0, s0
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_abs_i32 s0, s0
-; GFX1250-NEXT:    ; return to shader part epilog
-  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
-  ret i16 %res
-}
-
-define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
-; GFX-LABEL: abs_sgpr_i32:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_abs_i32 s0, s0
-; GFX-NEXT:    ; return to shader part epilog
-  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
-  ret i32 %res
-}
-
-define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
-; GFX6-LABEL: abs_sgpr_i64:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_ashr_i32 s2, s1, 31
-; GFX6-NEXT:    s_add_u32 s0, s0, s2
-; GFX6-NEXT:    s_mov_b32 s3, s2
-; GFX6-NEXT:    s_addc_u32 s1, s1, s2
-; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX6-NEXT:    ; return to shader part epilog
-;
-; GFX8-LABEL: abs_sgpr_i64:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_ashr_i32 s2, s1, 31
-; GFX8-NEXT:    s_add_u32 s0, s0, s2
-; GFX8-NEXT:    s_mov_b32 s3, s2
-; GFX8-NEXT:    s_addc_u32 s1, s1, s2
-; GFX8-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX8-NEXT:    ; return to shader part epilog
-;
-; GFX10-LABEL: abs_sgpr_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_ashr_i32 s2, s1, 31
-; GFX10-NEXT:    s_add_u32 s0, s0, s2
-; GFX10-NEXT:    s_mov_b32 s3, s2
-; GFX10-NEXT:    s_addc_u32 s1, s1, s2
-; GFX10-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX1250-LABEL: abs_sgpr_i64:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_ashr_i32 s2, s1, 31
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_mov_b32 s3, s2
-; GFX1250-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX1250-NEXT:    ; return to shader part epilog
-  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
-  ret i64 %res
-}
-
-define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {
-; GFX-LABEL: abs_sgpr_v4i32:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_abs_i32 s0, s0
-; GFX-NEXT:    s_abs_i32 s1, s1
-; GFX-NEXT:    s_abs_i32 s2, s2
-; GFX-NEXT:    s_abs_i32 s3, s3
-; GFX-NEXT:    ; return to shader part epilog
-  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
-  ret <4 x i32> %res
-}
-
-define i16 @abs_vgpr_i16(i16 %arg) {
-; GFX6-LABEL: abs_vgpr_i16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_i16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_sub_u16_e32 v1, 0, v0
-; GFX8-NEXT:    v_max_i16_e32 v0, v0, v1
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_sub_nc_u16 v1, 0, v0
-; GFX10-NEXT:    v_max_i16 v0, v0, v1
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_sub_nc_u16 v1, 0, v0
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT:    v_max_i16 v0, v0, v1
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
-  ret i16 %res
-}
-
-define i32 @abs_vgpr_i32(i32 %arg) {
-; GFX6-LABEL: abs_vgpr_i32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_i32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 0, v0
-; GFX8-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
-; GFX10-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_i32:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT:    v_max_i32_e32 v0, v0, v1
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
-  ret i32 %res
-}
-
-define i64 @abs_vgpr_i64(i64 %arg) {
-; GFX6-LABEL: abs_vgpr_i64:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
-; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
-; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
-; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX6-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_i64:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
-; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
-; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
-; GFX8-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX8-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_i64:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
-; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
-; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
-; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX10-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_i64:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT:    v_mov_b32_e32 v3, v2
-; GFX1250-NEXT:    v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT:    v_xor_b32_e32 v0, v0, v2
-; GFX1250-NEXT:    v_xor_b32_e32 v1, v1, v2
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
-  ret i64 %res
-}
-
-define <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
-; GFX6-LABEL: abs_vgpr_v4i32:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v4
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
-; GFX6-NEXT:    v_max_i32_e32 v1, v1, v4
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
-; GFX6-NEXT:    v_max_i32_e32 v2, v2, v4
-; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
-; GFX6-NEXT:    v_max_i32_e32 v3, v3, v4
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_v4i32:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
-; GFX8-NEXT:    v_max_i32_e32 v0, v0, v4
-; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
-; GFX8-NEXT:    v_max_i32_e32 v1, v1, v4
-; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v2
-; GFX8-NEXT:    v_max_i32_e32 v2, v2, v4
-; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
-; GFX8-NEXT:    v_max_i32_e32 v3, v3, v4
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_v4i32:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_sub_nc_u32_e32 v4, 0, v0
-; GFX10-NEXT:    v_sub_nc_u32_e32 v5, 0, v1
-; GFX10-NEXT:    v_sub_nc_u32_e32 v6, 0, v2
-; GFX10-NEXT:    v_sub_nc_u32_e32 v7, 0, v3
-; GFX10-NEXT:    v_max_i32_e32 v0, v0, v4
-; GFX10-NEXT:    v_max_i32_e32 v1, v1, v5
-; GFX10-NEXT:    v_max_i32_e32 v2, v2, v6
-; GFX10-NEXT:    v_max_i32_e32 v3, v3, v7
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_v4i32:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_dual_sub_nc_u32 v4, 0, v0 :: v_dual_sub_nc_u32 v5, 0, v1
-; GFX1250-NEXT:    v_dual_sub_nc_u32 v6, 0, v2 :: v_dual_sub_nc_u32 v7, 0, v3
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT:    v_max_i32_e32 v0, v0, v4
-; GFX1250-NEXT:    v_max_i32_e32 v1, v1, v5
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1250-NEXT:    v_max_i32_e32 v2, v2, v6
-; GFX1250-NEXT:    v_max_i32_e32 v3, v3, v7
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
-  ret <4 x i32> %res
-}
-
-define amdgpu_cs <2 x i8> @abs_sgpr_v2i8(<2 x i8> inreg %arg) {
-; GFX-LABEL: abs_sgpr_v2i8:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_sext_i32_i8 s0, s0
-; GFX-NEXT:    s_sext_i32_i8 s1, s1
-; GFX-NEXT:    s_abs_i32 s0, s0
-; GFX-NEXT:    s_abs_i32 s1, s1
-; GFX-NEXT:    ; return to shader part epilog
-  %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
-  ret <2 x i8> %res
-}
-
-define <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
-; GFX6-LABEL: abs_vgpr_v2i8:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
-; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v2
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
-; GFX6-NEXT:    v_max_i32_e32 v1, v1, v2
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_v2i8:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mov_b32_e32 v2, 0
-; GFX8-NEXT:    v_sub_u16_sdwa v3, v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT:    v_sub_u16_sdwa v2, v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT:    v_max_i16_sdwa v0, sext(v0), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_max_i16_sdwa v1, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_v2i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX10-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX10-NEXT:    v_sub_nc_u16 v2, 0, v0
-; GFX10-NEXT:    v_sub_nc_u16 v3, 0, v1
-; GFX10-NEXT:    v_max_i16 v0, v0, v2
-; GFX10-NEXT:    v_max_i16 v1, v1, v3
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_v2i8:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX1250-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT:    v_sub_nc_u16 v2, 0, v0
-; GFX1250-NEXT:    v_sub_nc_u16 v3, 0, v1
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT:    v_max_i16 v0, v0, v2
-; GFX1250-NEXT:    v_max_i16 v1, v1, v3
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
-  ret <2 x i8> %res
-}
-
-define amdgpu_cs <3 x i8> @abs_sgpr_v3i8(<3 x i8> inreg %arg) {
-; GFX-LABEL: abs_sgpr_v3i8:
-; GFX:       ; %bb.0:
-; GFX-NEXT:    s_sext_i32_i8 s0, s0
-; GFX-NEXT:    s_sext_i32_i8 s1, s1
-; GFX-NEXT:    s_sext_i32_i8 s2, s2
-; GFX-NEXT:    s_abs_i32 s0, s0
-; GFX-NEXT:    s_abs_i32 s1, s1
-; GFX-NEXT:    s_abs_i32 s2, s2
-; GFX-NEXT:    ; return to shader part epilog
-  %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
-  ret <3 x i8> %res
-}
-
-define <3 x i8> @abs_vgpr_v3i8(<3 x i8>  %arg) {
-; GFX6-LABEL: abs_vgpr_v3i8:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
-; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
-; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
-; GFX6-NEXT:    v_max_i32_e32 v2, v2, v3
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_v3i8:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mov_b32_e32 v3, 0
-; GFX8-NEXT:    v_sub_u16_sdwa v4, v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT:    v_max_i16_sdwa v0, sext(v0), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_sub_u16_sdwa v4, v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT:    v_sub_u16_sdwa v3, v3, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT:    v_max_i16_sdwa v1, sext(v1), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    v_max_i16_sdwa v2, sext(v2), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_v3i8:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX10-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX10-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX10-NEXT:    v_sub_nc_u16 v3, 0, v0
-; GFX10-NEXT:    v_sub_nc_u16 v4, 0, v1
-; GFX10-NEXT:    v_sub_nc_u16 v5, 0, v2
-; GFX10-NEXT:    v_max_i16 v0, v0, v3
-; GFX10-NEXT:    v_max_i16 v1, v1, v4
-; GFX10-NEXT:    v_max_i16 v2, v2, v5
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_v3i8:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX1250-NEXT:    v_bfe_i32 v1, v1, 0, 8
-; GFX1250-NEXT:    v_bfe_i32 v2, v2, 0, 8
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT:    v_sub_nc_u16 v3, 0, v0
-; GFX1250-NEXT:    v_sub_nc_u16 v4, 0, v1
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT:    v_sub_nc_u16 v5, 0, v2
-; GFX1250-NEXT:    v_max_i16 v0, v0, v3
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1250-NEXT:    v_max_i16 v1, v1, v4
-; GFX1250-NEXT:    v_max_i16 v2, v2, v5
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
-  ret <3 x i8> %res
-}
-
-define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
-; GFX6-LABEL: abs_sgpr_v2i16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_sext_i32_i16 s0, s0
-; GFX6-NEXT:    s_sext_i32_i16 s1, s1
-; GFX6-NEXT:    s_abs_i32 s0, s0
-; GFX6-NEXT:    s_abs_i32 s1, s1
-; GFX6-NEXT:    ; return to shader part epilog
-;
-; GFX8-LABEL: abs_sgpr_v2i16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
-; GFX8-NEXT:    s_sext_i32_i16 s1, s1
-; GFX8-NEXT:    s_sext_i32_i16 s0, s0
-; GFX8-NEXT:    s_abs_i32 s1, s1
-; GFX8-NEXT:    s_abs_i32 s0, s0
-; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
-; GFX8-NEXT:    s_or_b32 s0, s0, s1
-; GFX8-NEXT:    ; return to shader part epilog
-;
-; GFX10-LABEL: abs_sgpr_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sext_i32_i16 s1, s0
-; GFX10-NEXT:    s_ashr_i32 s0, s0, 16
-; GFX10-NEXT:    s_abs_i32 s1, s1
-; GFX10-NEXT:    s_abs_i32 s0, s0
-; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s1, s0
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX1250-LABEL: abs_sgpr_v2i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_sext_i32_i16 s1, s0
-; GFX1250-NEXT:    s_ashr_i32 s0, s0, 16
-; GFX1250-NEXT:    s_abs_i32 s1, s1
-; GFX1250-NEXT:    s_abs_i32 s0, s0
-; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT:    s_pack_ll_b32_b16 s0, s1, s0
-; GFX1250-NEXT:    ; return to shader part epilog
-  %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
-  ret <2 x i16> %res
-}
-
-define <2 x i16> @abs_vgpr_v2i16(<2 x i16> %arg) {
-; GFX6-LABEL: abs_vgpr_v2i16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
-; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v2
-; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
-; GFX6-NEXT:    v_max_i32_e32 v1, v1, v2
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_v2i16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mov_b32_e32 v2, 0
-; GFX8-NEXT:    v_sub_u16_e32 v1, 0, v0
-; GFX8-NEXT:    v_sub_u16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_max_i16_e32 v1, v0, v1
-; GFX8-NEXT:    v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_v2i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_pk_sub_i16 v1, 0, v0
-; GFX10-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_v2i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_pk_sub_i16 v1, 0, v0
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT:    v_pk_max_i16 v0, v0, v1
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
-  ret <2 x i16> %res
-}
-
-define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
-; GFX6-LABEL: abs_sgpr_v3i16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_sext_i32_i16 s0, s0
-; GFX6-NEXT:    s_sext_i32_i16 s1, s1
-; GFX6-NEXT:    s_sext_i32_i16 s2, s2
-; GFX6-NEXT:    s_abs_i32 s0, s0
-; GFX6-NEXT:    s_abs_i32 s1, s1
-; GFX6-NEXT:    s_abs_i32 s2, s2
-; GFX6-NEXT:    ; return to shader part epilog
-;
-; GFX8-LABEL: abs_sgpr_v3i16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
-; GFX8-NEXT:    s_sext_i32_i16 s2, s2
-; GFX8-NEXT:    s_sext_i32_i16 s0, s0
-; GFX8-NEXT:    s_abs_i32 s2, s2
-; GFX8-NEXT:    s_abs_i32 s0, s0
-; GFX8-NEXT:    s_sext_i32_i16 s1, s1
-; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
-; GFX8-NEXT:    s_abs_i32 s1, s1
-; GFX8-NEXT:    s_or_b32 s0, s0, s2
-; GFX8-NEXT:    ; return to shader part epilog
-;
-; GFX10-LABEL: abs_sgpr_v3i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_sext_i32_i16 s2, s0
-; GFX10-NEXT:    s_ashr_i32 s0, s0, 16
-; GFX10-NEXT:    s_abs_i32 s2, s2
-; GFX10-NEXT:    s_abs_i32 s0, s0
-; GFX10-NEXT:    s_sext_i32_i16 s1, s1
-; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s2, s0
-; GFX10-NEXT:    s_abs_i32 s1, s1
-; GFX10-NEXT:    ; return to shader part epilog
-;
-; GFX1250-LABEL: abs_sgpr_v3i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_sext_i32_i16 s2, s0
-; GFX1250-NEXT:    s_ashr_i32 s0, s0, 16
-; GFX1250-NEXT:    s_abs_i32 s2, s2
-; GFX1250-NEXT:    s_abs_i32 s0, s0
-; GFX1250-NEXT:    s_sext_i32_i16 s1, s1
-; GFX1250-NEXT:    s_pack_ll_b32_b16 s0, s2, s0
-; GFX1250-NEXT:    s_abs_i32 s1, s1
-; GFX1250-NEXT:    ; return to shader part epilog
-  %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
-  ret <3 x i16> %res
-}
-
-define <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {
-; GFX6-LABEL: abs_vgpr_v3i16:
-; GFX6:       ; %bb.0:
-; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
-; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
-; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
-; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
-; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
-; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
-; GFX6-NEXT:    v_max_i32_e32 v2, v2, v3
-; GFX6-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX8-LABEL: abs_vgpr_v3i16:
-; GFX8:       ; %bb.0:
-; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT:    v_mov_b32_e32 v3, 0
-; GFX8-NEXT:    v_sub_u16_e32 v2, 0, v0
-; GFX8-NEXT:    v_sub_u16_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT:    v_sub_u16_e32 v4, 0, v1
-; GFX8-NEXT:    v_max_i16_e32 v2, v0, v2
-; GFX8-NEXT:    v_max_i16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX8-NEXT:    v_max_i16_e32 v1, v1, v4
-; GFX8-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX10-LABEL: abs_vgpr_v3i16:
-; GFX10:       ; %bb.0:
-; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT:    v_pk_sub_i16 v2, 0, v0
-; GFX10-NEXT:    v_sub_nc_u16 v3, 0, v1
-; GFX10-NEXT:    v_pk_max_i16 v0, v0, v2
-; GFX10-NEXT:    v_max_i16 v1, v1, v3
-; GFX10-NEXT:    s_setpc_b64 s[30:31]
-;
-; GFX1250-LABEL: abs_vgpr_v3i16:
-; GFX1250:       ; %bb.0:
-; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
-; GFX1250-NEXT:    s_wait_kmcnt 0x0
-; GFX1250-NEXT:    v_pk_sub_i16 v2, 0, v0
-; GFX1250-NEXT:    v_sub_nc_u16 v3, 0, v1
-; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250-NEXT:    v_pk_max_i16 v0, v0, v2
-; GFX1250-NEXT:    v_max_i16 v1, v1, v3
-; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
-  %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
-  ret <3 x i16> %res
-}
diff --git a/llvm/test/CodeGen/AMDGPU/absdiff.ll b/llvm/test/CodeGen/AMDGPU/absdiff.ll
index 9cb397fb9d1c6..ee8241e355e26 100644
--- a/llvm/test/CodeGen/AMDGPU/absdiff.ll
+++ b/llvm/test/CodeGen/AMDGPU/absdiff.ll
@@ -5,10 +5,8 @@ define amdgpu_ps i16 @absdiff_i16_false(i16 inreg %arg0, i16 inreg %arg1) {
 ; CHECK-LABEL: absdiff_i16_false:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_sub_i32 s0, s0, s1
-; CHECK-NEXT:    s_sext_i32_i16 s1, s0
-; CHECK-NEXT:    s_sub_i32 s0, 0, s0
 ; CHECK-NEXT:    s_sext_i32_i16 s0, s0
-; CHECK-NEXT:    s_max_i32 s0, s1, s0
+; CHECK-NEXT:    s_abs_i32 s0, s0
 ; CHECK-NEXT:    ; return to shader part epilog
   %diff = sub i16 %arg0, %arg1
   %res = call i16 @llvm.abs.i16(i16 %diff, i1 false) ; INT_MIN input returns INT_MIN
@@ -19,10 +17,8 @@ define amdgpu_ps i16 @absdiff_i16_true(i16 inreg %arg0, i16 inreg %arg1) {
 ; CHECK-LABEL: absdiff_i16_true:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_sub_i32 s0, s0, s1
-; CHECK-NEXT:    s_sext_i32_i16 s1, s0
-; CHECK-NEXT:    s_sub_i32 s0, 0, s0
 ; CHECK-NEXT:    s_sext_i32_i16 s0, s0
-; CHECK-NEXT:    s_max_i32 s0, s1, s0
+; CHECK-NEXT:    s_abs_i32 s0, s0
 ; CHECK-NEXT:    ; return to shader part epilog
   %diff = sub i16 %arg0, %arg1
   %res = call i16 @llvm.abs.i16(i16 %diff, i1 true) ; INT_MIN input returns poison
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.abs.ll b/llvm/test/CodeGen/AMDGPU/llvm.abs.ll
new file mode 100644
index 0000000000000..dd7d2fbc931b6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/llvm.abs.ll
@@ -0,0 +1,1487 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn -mcpu=tahiti -o - < %s | FileCheck %s --check-prefixes=SDAG6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -o - < %s | FileCheck %s --check-prefixes=SDAG8
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -o - < %s | FileCheck %s --check-prefixes=SDAG10
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -o - < %s | FileCheck %s --check-prefixes=SDAG1250
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=tahiti -o - < %s | FileCheck %s --check-prefixes=GFX,GFX6
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -o - < %s | FileCheck %s --check-prefixes=GFX,GFX8
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX10
+; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1250 -o - < %s | FileCheck %s --check-prefixes=GFX,GFX1250
+
+declare i16 @llvm.abs.i16(i16, i1)
+declare i32 @llvm.abs.i32(i32, i1)
+declare i64 @llvm.abs.i64(i64, i1)
+declare <2 x i8> @llvm.abs.v2i8(<2 x i8>, i1)
+declare <3 x i8> @llvm.abs.v3i8(<3 x i8>, i1)
+declare <2 x i16> @llvm.abs.v2i16(<2 x i16>, i1)
+declare <3 x i16> @llvm.abs.v3i16(<3 x i16>, i1)
+declare <4 x i32> @llvm.abs.v4i32(<4 x i32>, i1)
+
+define amdgpu_cs i8 @abs_sgpr_i8(i8 inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_i8:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_i8:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_i8:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG10-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_i8:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; SDAG1250-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_i8:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i8 s0, s0
+; GFX6-NEXT:    s_abs_i32 s0, s0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_i8:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_sext_i32_i8 s0, s0
+; GFX8-NEXT:    s_abs_i32 s0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_i8:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_sext_i32_i8 s0, s0
+; GFX10-NEXT:    s_abs_i32 s0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_i8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_sext_i32_i8 s0, s0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_abs_i32 s0, s0
+; GFX1250-NEXT:    ; return to shader part epilog
+  %res = call i8 @llvm.abs.i8(i8 %arg, i1 false)
+  ret i8 %res
+}
+
+define amdgpu_cs i8 @abs_sgpr_i8_neg(i8 inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_i8_neg:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    s_sub_i32 s0, 0, s0
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_i8_neg:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    s_sub_i32 s0, 0, s0
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_i8_neg:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    s_sub_i32 s0, 0, s0
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_i8_neg:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    s_sub_co_i32 s0, 0, s0
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_i8_neg:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i8 s0, s0
+; GFX6-NEXT:    s_abs_i32 s0, s0
+; GFX6-NEXT:    s_sub_i32 s0, 0, s0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_i8_neg:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_sext_i32_i8 s0, s0
+; GFX8-NEXT:    s_abs_i32 s0, s0
+; GFX8-NEXT:    s_sub_i32 s0, 0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_i8_neg:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_sext_i32_i8 s0, s0
+; GFX10-NEXT:    s_abs_i32 s0, s0
+; GFX10-NEXT:    s_sub_i32 s0, 0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_i8_neg:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_sext_i32_i8 s0, s0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_abs_i32 s0, s0
+; GFX1250-NEXT:    s_sub_co_i32 s0, 0, s0
+; GFX1250-NEXT:    ; return to shader part epilog
+  %res1 = call i8 @llvm.abs.i8(i8 %arg, i1 false)
+  %res2 = sub i8 0, %res1
+  ret i8 %res2
+}
+
+define amdgpu_cs i16 @abs_sgpr_i16(i16 inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_i16:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_i16:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_i16:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_i16:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i16 s0, s0
+; GFX6-NEXT:    s_abs_i32 s0, s0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_sext_i32_i16 s0, s0
+; GFX8-NEXT:    s_abs_i32 s0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_sext_i32_i16 s0, s0
+; GFX10-NEXT:    s_abs_i32 s0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_i16:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_sext_i32_i16 s0, s0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_abs_i32 s0, s0
+; GFX1250-NEXT:    ; return to shader part epilog
+
+  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
+  ret i16 %res
+}
+
+define amdgpu_ps i16 @abs_sgpr_i16_neg(i16 inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_i16_neg:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    s_sub_i32 s0, 0, s0
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_i16_neg:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    s_sub_i32 s0, 0, s0
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_i16_neg:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    s_sub_i32 s0, 0, s0
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_i16_neg:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    s_sub_co_i32 s0, 0, s0
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_i16_neg:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i16 s0, s0
+; GFX6-NEXT:    s_abs_i32 s0, s0
+; GFX6-NEXT:    s_sub_i32 s0, 0, s0
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_i16_neg:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_sext_i32_i16 s0, s0
+; GFX8-NEXT:    s_abs_i32 s0, s0
+; GFX8-NEXT:    s_sub_i32 s0, 0, s0
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_i16_neg:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_sext_i32_i16 s0, s0
+; GFX10-NEXT:    s_abs_i32 s0, s0
+; GFX10-NEXT:    s_sub_i32 s0, 0, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_i16_neg:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_sext_i32_i16 s0, s0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_abs_i32 s0, s0
+; GFX1250-NEXT:    s_sub_co_i32 s0, 0, s0
+; GFX1250-NEXT:    ; return to shader part epilog
+  %res1 = call i16 @llvm.abs.i16(i16 %arg, i1 false)
+  %res2 = sub i16 0, %res1
+  ret i16 %res2
+}
+
+define amdgpu_cs i32 @abs_sgpr_i32(i32 inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_i32:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_i32:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_i32:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_i32:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX-LABEL: abs_sgpr_i32:
+; GFX:       ; %bb.0:
+; GFX-NEXT:    s_abs_i32 s0, s0
+; GFX-NEXT:    ; return to shader part epilog
+  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
+  ret i32 %res
+}
+
+define amdgpu_cs i64 @abs_sgpr_i64(i64 inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_i64:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_ashr_i32 s2, s1, 31
+; SDAG6-NEXT:    s_mov_b32 s3, s2
+; SDAG6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; SDAG6-NEXT:    s_sub_u32 s0, s0, s2
+; SDAG6-NEXT:    s_subb_u32 s1, s1, s2
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_i64:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_ashr_i32 s2, s1, 31
+; SDAG8-NEXT:    s_mov_b32 s3, s2
+; SDAG8-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; SDAG8-NEXT:    s_sub_u32 s0, s0, s2
+; SDAG8-NEXT:    s_subb_u32 s1, s1, s2
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_i64:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_ashr_i32 s2, s1, 31
+; SDAG10-NEXT:    s_mov_b32 s3, s2
+; SDAG10-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; SDAG10-NEXT:    s_sub_u32 s0, s0, s2
+; SDAG10-NEXT:    s_subb_u32 s1, s1, s2
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_i64:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_sub_nc_u64 s[2:3], 0, s[0:1]
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG1250-NEXT:    v_max_i64 v[0:1], s[0:1], s[2:3]
+; SDAG1250-NEXT:    v_readfirstlane_b32 s0, v0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2)
+; SDAG1250-NEXT:    v_readfirstlane_b32 s1, v1
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_i64:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_ashr_i32 s2, s1, 31
+; GFX6-NEXT:    s_add_u32 s0, s0, s2
+; GFX6-NEXT:    s_mov_b32 s3, s2
+; GFX6-NEXT:    s_addc_u32 s1, s1, s2
+; GFX6-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_ashr_i32 s2, s1, 31
+; GFX8-NEXT:    s_add_u32 s0, s0, s2
+; GFX8-NEXT:    s_mov_b32 s3, s2
+; GFX8-NEXT:    s_addc_u32 s1, s1, s2
+; GFX8-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_i64:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_ashr_i32 s2, s1, 31
+; GFX10-NEXT:    s_add_u32 s0, s0, s2
+; GFX10-NEXT:    s_mov_b32 s3, s2
+; GFX10-NEXT:    s_addc_u32 s1, s1, s2
+; GFX10-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_i64:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_ashr_i32 s2, s1, 31
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_mov_b32 s3, s2
+; GFX1250-NEXT:    s_add_nc_u64 s[0:1], s[0:1], s[2:3]
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
+; GFX1250-NEXT:    ; return to shader part epilog
+  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
+  ret i64 %res
+}
+
+define amdgpu_cs <4 x i32> @abs_sgpr_v4i32(<4 x i32> inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_v4i32:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_abs_i32 s3, s3
+; SDAG6-NEXT:    s_abs_i32 s2, s2
+; SDAG6-NEXT:    s_abs_i32 s1, s1
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_v4i32:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_abs_i32 s3, s3
+; SDAG8-NEXT:    s_abs_i32 s2, s2
+; SDAG8-NEXT:    s_abs_i32 s1, s1
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_v4i32:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_abs_i32 s3, s3
+; SDAG10-NEXT:    s_abs_i32 s2, s2
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s1, s1
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_v4i32:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_abs_i32 s3, s3
+; SDAG1250-NEXT:    s_abs_i32 s2, s2
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    s_abs_i32 s1, s1
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX-LABEL: abs_sgpr_v4i32:
+; GFX:       ; %bb.0:
+; GFX-NEXT:    s_abs_i32 s0, s0
+; GFX-NEXT:    s_abs_i32 s1, s1
+; GFX-NEXT:    s_abs_i32 s2, s2
+; GFX-NEXT:    s_abs_i32 s3, s3
+; GFX-NEXT:    ; return to shader part epilog
+  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
+  ret <4 x i32> %res
+}
+
+define i16 @abs_vgpr_i16(i16 %arg) {
+; SDAG6-LABEL: abs_vgpr_i16:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; SDAG6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
+; SDAG6-NEXT:    v_max_i32_e32 v0, v1, v0
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_i16:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_sub_u16_e32 v1, 0, v0
+; SDAG8-NEXT:    v_max_i16_e32 v0, v0, v1
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_i16:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_sub_nc_u16 v1, 0, v0
+; SDAG10-NEXT:    v_max_i16 v0, v0, v1
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_i16:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_sub_nc_u16 v1, 0, v0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG1250-NEXT:    v_max_i16 v0, v0, v1
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_sub_u16_e32 v1, 0, v0
+; GFX8-NEXT:    v_max_i16_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_sub_nc_u16 v1, 0, v0
+; GFX10-NEXT:    v_max_i16 v0, v0, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_i16:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_sub_nc_u16 v1, 0, v0
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT:    v_max_i16 v0, v0, v1
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)
+  ret i16 %res
+}
+
+define i32 @abs_vgpr_i32(i32 %arg) {
+; SDAG6-LABEL: abs_vgpr_i32:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
+; SDAG6-NEXT:    v_max_i32_e32 v0, v1, v0
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_i32:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_sub_u32_e32 v1, vcc, 0, v0
+; SDAG8-NEXT:    v_max_i32_e32 v0, v1, v0
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_i32:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; SDAG10-NEXT:    v_max_i32_e32 v0, v1, v0
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_i32:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG1250-NEXT:    v_max_i32_e32 v0, v1, v0
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v0
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v1
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, 0, v0
+; GFX8-NEXT:    v_max_i32_e32 v0, v0, v1
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; GFX10-NEXT:    v_max_i32_e32 v0, v0, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_i32:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_sub_nc_u32_e32 v1, 0, v0
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT:    v_max_i32_e32 v0, v0, v1
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
+  ret i32 %res
+}
+
+define i64 @abs_vgpr_i64(i64 %arg) {
+; SDAG6-LABEL: abs_vgpr_i64:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; SDAG6-NEXT:    v_xor_b32_e32 v0, v0, v2
+; SDAG6-NEXT:    v_xor_b32_e32 v1, v1, v2
+; SDAG6-NEXT:    v_sub_i32_e32 v0, vcc, v0, v2
+; SDAG6-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_i64:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; SDAG8-NEXT:    v_xor_b32_e32 v0, v0, v2
+; SDAG8-NEXT:    v_xor_b32_e32 v1, v1, v2
+; SDAG8-NEXT:    v_sub_u32_e32 v0, vcc, v0, v2
+; SDAG8-NEXT:    v_subb_u32_e32 v1, vcc, v1, v2, vcc
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_i64:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; SDAG10-NEXT:    v_xor_b32_e32 v0, v0, v2
+; SDAG10-NEXT:    v_xor_b32_e32 v1, v1, v2
+; SDAG10-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, v2
+; SDAG10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_i64:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_sub_nc_u64_e32 v[2:3], 0, v[0:1]
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG1250-NEXT:    v_max_i64 v[0:1], v[0:1], v[2:3]
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_i64:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v2
+; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GFX6-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX6-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_i64:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2
+; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc
+; GFX8-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX8-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_i64:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v2, vcc_lo
+; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX10-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_i64:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_ashrrev_i32_e32 v2, 31, v1
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-NEXT:    v_mov_b32_e32 v3, v2
+; GFX1250-NEXT:    v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_xor_b32_e32 v0, v0, v2
+; GFX1250-NEXT:    v_xor_b32_e32 v1, v1, v2
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call i64 @llvm.abs.i64(i64 %arg, i1 false)
+  ret i64 %res
+}
+
+define <4 x i32> @abs_vgpr_v4i32(<4 x i32> %arg) {
+; SDAG6-LABEL: abs_vgpr_v4i32:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
+; SDAG6-NEXT:    v_max_i32_e32 v0, v4, v0
+; SDAG6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
+; SDAG6-NEXT:    v_max_i32_e32 v1, v4, v1
+; SDAG6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
+; SDAG6-NEXT:    v_max_i32_e32 v2, v4, v2
+; SDAG6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
+; SDAG6-NEXT:    v_max_i32_e32 v3, v4, v3
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_v4i32:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
+; SDAG8-NEXT:    v_max_i32_e32 v0, v4, v0
+; SDAG8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
+; SDAG8-NEXT:    v_max_i32_e32 v1, v4, v1
+; SDAG8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v2
+; SDAG8-NEXT:    v_max_i32_e32 v2, v4, v2
+; SDAG8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
+; SDAG8-NEXT:    v_max_i32_e32 v3, v4, v3
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_v4i32:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_sub_nc_u32_e32 v4, 0, v0
+; SDAG10-NEXT:    v_sub_nc_u32_e32 v5, 0, v1
+; SDAG10-NEXT:    v_sub_nc_u32_e32 v6, 0, v2
+; SDAG10-NEXT:    v_sub_nc_u32_e32 v7, 0, v3
+; SDAG10-NEXT:    v_max_i32_e32 v0, v4, v0
+; SDAG10-NEXT:    v_max_i32_e32 v1, v5, v1
+; SDAG10-NEXT:    v_max_i32_e32 v2, v6, v2
+; SDAG10-NEXT:    v_max_i32_e32 v3, v7, v3
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_v4i32:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_dual_sub_nc_u32 v4, 0, v0 :: v_dual_sub_nc_u32 v5, 0, v1
+; SDAG1250-NEXT:    v_dual_sub_nc_u32 v6, 0, v2 :: v_dual_sub_nc_u32 v7, 0, v3
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; SDAG1250-NEXT:    v_max_i32_e32 v0, v4, v0
+; SDAG1250-NEXT:    v_max_i32_e32 v1, v5, v1
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; SDAG1250-NEXT:    v_max_i32_e32 v2, v6, v2
+; SDAG1250-NEXT:    v_max_i32_e32 v3, v7, v3
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_v4i32:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v0
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v4
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v1
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v4
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v2
+; GFX6-NEXT:    v_max_i32_e32 v2, v2, v4
+; GFX6-NEXT:    v_sub_i32_e32 v4, vcc, 0, v3
+; GFX6-NEXT:    v_max_i32_e32 v3, v3, v4
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_v4i32:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v0
+; GFX8-NEXT:    v_max_i32_e32 v0, v0, v4
+; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v1
+; GFX8-NEXT:    v_max_i32_e32 v1, v1, v4
+; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v2
+; GFX8-NEXT:    v_max_i32_e32 v2, v2, v4
+; GFX8-NEXT:    v_sub_u32_e32 v4, vcc, 0, v3
+; GFX8-NEXT:    v_max_i32_e32 v3, v3, v4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_v4i32:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_sub_nc_u32_e32 v4, 0, v0
+; GFX10-NEXT:    v_sub_nc_u32_e32 v5, 0, v1
+; GFX10-NEXT:    v_sub_nc_u32_e32 v6, 0, v2
+; GFX10-NEXT:    v_sub_nc_u32_e32 v7, 0, v3
+; GFX10-NEXT:    v_max_i32_e32 v0, v0, v4
+; GFX10-NEXT:    v_max_i32_e32 v1, v1, v5
+; GFX10-NEXT:    v_max_i32_e32 v2, v2, v6
+; GFX10-NEXT:    v_max_i32_e32 v3, v3, v7
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_v4i32:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_dual_sub_nc_u32 v4, 0, v0 :: v_dual_sub_nc_u32 v5, 0, v1
+; GFX1250-NEXT:    v_dual_sub_nc_u32 v6, 0, v2 :: v_dual_sub_nc_u32 v7, 0, v3
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT:    v_max_i32_e32 v0, v0, v4
+; GFX1250-NEXT:    v_max_i32_e32 v1, v1, v5
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1250-NEXT:    v_max_i32_e32 v2, v2, v6
+; GFX1250-NEXT:    v_max_i32_e32 v3, v3, v7
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %arg, i1 false)
+  ret <4 x i32> %res
+}
+
+define amdgpu_cs <2 x i8> @abs_sgpr_v2i8(<2 x i8> inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_v2i8:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i8 s1, s1
+; SDAG6-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG6-NEXT:    s_abs_i32 s1, s1
+; SDAG6-NEXT:    s_lshl_b32 s2, s1, 8
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    s_or_b32 s0, s0, s2
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_v2i8:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; SDAG8-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG8-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_abs_i32 s1, s1
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    s_lshl_b32 s2, s1, 8
+; SDAG8-NEXT:    s_or_b32 s0, s0, s2
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_v2i8:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; SDAG10-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG10-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG10-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s1, s1
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    s_lshl_b32 s2, s1, 8
+; SDAG10-NEXT:    s_or_b32 s0, s0, s2
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_v2i8:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; SDAG1250-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG1250-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG1250-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG1250-NEXT:    s_abs_i32 s1, s1
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    s_lshl_b32 s2, s1, 8
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; SDAG1250-NEXT:    s_or_b32 s0, s0, s2
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX-LABEL: abs_sgpr_v2i8:
+; GFX:       ; %bb.0:
+; GFX-NEXT:    s_sext_i32_i8 s0, s0
+; GFX-NEXT:    s_sext_i32_i8 s1, s1
+; GFX-NEXT:    s_abs_i32 s0, s0
+; GFX-NEXT:    s_abs_i32 s1, s1
+; GFX-NEXT:    ; return to shader part epilog
+  %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
+  ret <2 x i8> %res
+}
+
+define <2 x i8> @abs_vgpr_v2i8(<2 x i8> %arg) {
+; SDAG6-LABEL: abs_vgpr_v2i8:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; SDAG6-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; SDAG6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
+; SDAG6-NEXT:    v_max_i32_e32 v0, v2, v0
+; SDAG6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
+; SDAG6-NEXT:    v_max_i32_e32 v1, v2, v1
+; SDAG6-NEXT:    v_lshlrev_b32_e32 v2, 8, v1
+; SDAG6-NEXT:    v_or_b32_e32 v0, v0, v2
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_v2i8:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_mov_b32_e32 v2, 0
+; SDAG8-NEXT:    v_sub_u16_sdwa v3, v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; SDAG8-NEXT:    v_sub_u16_sdwa v2, v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; SDAG8-NEXT:    v_max_i16_sdwa v1, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; SDAG8-NEXT:    v_max_i16_sdwa v0, sext(v0), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; SDAG8-NEXT:    v_lshlrev_b16_e32 v2, 8, v1
+; SDAG8-NEXT:    v_or_b32_e32 v0, v0, v2
+; SDAG8-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_v2i8:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; SDAG10-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; SDAG10-NEXT:    v_sub_nc_u16 v2, 0, v1
+; SDAG10-NEXT:    v_sub_nc_u16 v3, 0, v0
+; SDAG10-NEXT:    v_max_i16 v1, v1, v2
+; SDAG10-NEXT:    v_max_i16 v0, v0, v3
+; SDAG10-NEXT:    v_lshlrev_b16 v2, 8, v1
+; SDAG10-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; SDAG10-NEXT:    v_or_b32_e32 v0, v0, v2
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_v2i8:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; SDAG1250-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG1250-NEXT:    v_sub_nc_u16 v2, 0, v1
+; SDAG1250-NEXT:    v_sub_nc_u16 v3, 0, v0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG1250-NEXT:    v_max_i16 v1, v1, v2
+; SDAG1250-NEXT:    v_max_i16 v0, v0, v3
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; SDAG1250-NEXT:    v_lshlrev_b16 v2, 8, v1
+; SDAG1250-NEXT:    v_and_b32_e32 v1, 0xff, v1
+; SDAG1250-NEXT:    v_or_b32_e32 v0, v0, v2
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_v2i8:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_v2i8:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0
+; GFX8-NEXT:    v_sub_u16_sdwa v3, v2, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT:    v_sub_u16_sdwa v2, v2, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT:    v_max_i16_sdwa v0, sext(v0), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_max_i16_sdwa v1, sext(v1), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_v2i8:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX10-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX10-NEXT:    v_sub_nc_u16 v2, 0, v0
+; GFX10-NEXT:    v_sub_nc_u16 v3, 0, v1
+; GFX10-NEXT:    v_max_i16 v0, v0, v2
+; GFX10-NEXT:    v_max_i16 v1, v1, v3
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_v2i8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX1250-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_sub_nc_u16 v2, 0, v0
+; GFX1250-NEXT:    v_sub_nc_u16 v3, 0, v1
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_max_i16 v0, v0, v2
+; GFX1250-NEXT:    v_max_i16 v1, v1, v3
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call <2 x i8> @llvm.abs.v2i8(<2 x i8> %arg, i1 false)
+  ret <2 x i8> %res
+}
+
+define amdgpu_cs <3 x i8> @abs_sgpr_v3i8(<3 x i8> inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_v3i8:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i8 s1, s1
+; SDAG6-NEXT:    s_sext_i32_i8 s0, s0
+; SDAG6-NEXT:    s_sext_i32_i8 s2, s2
+; SDAG6-NEXT:    s_abs_i32 s1, s1
+; SDAG6-NEXT:    s_abs_i32 s2, s2
+; SDAG6-NEXT:    s_lshl_b32 s1, s1, 8
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    s_lshl_b32 s3, s2, 16
+; SDAG6-NEXT:    s_or_b32 s0, s0, s1
+; SDAG6-NEXT:    s_or_b32 s0, s0, s3
+; SDAG6-NEXT:    s_lshr_b32 s1, s0, 8
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_v3i8:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; SDAG8-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG8-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_abs_i32 s1, s1
+; SDAG8-NEXT:    s_bfe_i32 s2, s2, 0x80000
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    s_sext_i32_i16 s2, s2
+; SDAG8-NEXT:    s_lshl_b32 s1, s1, 8
+; SDAG8-NEXT:    s_abs_i32 s2, s2
+; SDAG8-NEXT:    s_or_b32 s0, s0, s1
+; SDAG8-NEXT:    s_lshl_b32 s3, s2, 16
+; SDAG8-NEXT:    s_and_b32 s1, s0, 0xffff
+; SDAG8-NEXT:    s_or_b32 s1, s1, s3
+; SDAG8-NEXT:    s_lshr_b32 s1, s1, 8
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_v3i8:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; SDAG10-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG10-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG10-NEXT:    s_bfe_i32 s2, s2, 0x80000
+; SDAG10-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG10-NEXT:    s_abs_i32 s1, s1
+; SDAG10-NEXT:    s_abs_i32 s0, s0
+; SDAG10-NEXT:    s_lshl_b32 s1, s1, 8
+; SDAG10-NEXT:    s_sext_i32_i16 s2, s2
+; SDAG10-NEXT:    s_or_b32 s0, s0, s1
+; SDAG10-NEXT:    s_abs_i32 s2, s2
+; SDAG10-NEXT:    s_and_b32 s1, s0, 0xffff
+; SDAG10-NEXT:    s_lshl_b32 s3, s2, 16
+; SDAG10-NEXT:    s_or_b32 s1, s1, s3
+; SDAG10-NEXT:    s_lshr_b32 s1, s1, 8
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_v3i8:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_bfe_i32 s1, s1, 0x80000
+; SDAG1250-NEXT:    s_bfe_i32 s0, s0, 0x80000
+; SDAG1250-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG1250-NEXT:    s_bfe_i32 s2, s2, 0x80000
+; SDAG1250-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG1250-NEXT:    s_abs_i32 s1, s1
+; SDAG1250-NEXT:    s_abs_i32 s0, s0
+; SDAG1250-NEXT:    s_lshl_b32 s1, s1, 8
+; SDAG1250-NEXT:    s_sext_i32_i16 s2, s2
+; SDAG1250-NEXT:    s_or_b32 s0, s0, s1
+; SDAG1250-NEXT:    s_abs_i32 s2, s2
+; SDAG1250-NEXT:    s_and_b32 s1, s0, 0xffff
+; SDAG1250-NEXT:    s_lshl_b32 s3, s2, 16
+; SDAG1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; SDAG1250-NEXT:    s_or_b32 s1, s1, s3
+; SDAG1250-NEXT:    s_lshr_b32 s1, s1, 8
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX-LABEL: abs_sgpr_v3i8:
+; GFX:       ; %bb.0:
+; GFX-NEXT:    s_sext_i32_i8 s0, s0
+; GFX-NEXT:    s_sext_i32_i8 s1, s1
+; GFX-NEXT:    s_sext_i32_i8 s2, s2
+; GFX-NEXT:    s_abs_i32 s0, s0
+; GFX-NEXT:    s_abs_i32 s1, s1
+; GFX-NEXT:    s_abs_i32 s2, s2
+; GFX-NEXT:    ; return to shader part epilog
+  %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
+  ret <3 x i8> %res
+}
+
+define <3 x i8> @abs_vgpr_v3i8(<3 x i8>  %arg) {
+; SDAG6-LABEL: abs_vgpr_v3i8:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; SDAG6-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; SDAG6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; SDAG6-NEXT:    v_max_i32_e32 v0, v3, v0
+; SDAG6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; SDAG6-NEXT:    v_max_i32_e32 v1, v3, v1
+; SDAG6-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; SDAG6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1
+; SDAG6-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG6-NEXT:    v_sub_i32_e32 v1, vcc, 0, v2
+; SDAG6-NEXT:    v_max_i32_e32 v2, v1, v2
+; SDAG6-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
+; SDAG6-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG6-NEXT:    v_lshrrev_b32_e32 v1, 8, v0
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_v3i8:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_mov_b32_e32 v3, 0
+; SDAG8-NEXT:    v_sub_u16_sdwa v4, v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; SDAG8-NEXT:    v_max_i16_sdwa v0, sext(v0), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; SDAG8-NEXT:    v_sub_u16_sdwa v4, v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; SDAG8-NEXT:    v_max_i16_sdwa v1, sext(v1), v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; SDAG8-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG8-NEXT:    v_sub_u16_sdwa v1, v3, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; SDAG8-NEXT:    v_max_i16_sdwa v2, sext(v2), v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; SDAG8-NEXT:    v_lshlrev_b32_e32 v1, 16, v2
+; SDAG8-NEXT:    v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; SDAG8-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_v3i8:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; SDAG10-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; SDAG10-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; SDAG10-NEXT:    v_sub_nc_u16 v3, 0, v1
+; SDAG10-NEXT:    v_sub_nc_u16 v4, 0, v0
+; SDAG10-NEXT:    v_sub_nc_u16 v5, 0, v2
+; SDAG10-NEXT:    v_max_i16 v1, v1, v3
+; SDAG10-NEXT:    v_max_i16 v0, v0, v4
+; SDAG10-NEXT:    v_max_i16 v2, v2, v5
+; SDAG10-NEXT:    v_lshlrev_b16 v1, 8, v1
+; SDAG10-NEXT:    v_lshlrev_b32_e32 v3, 16, v2
+; SDAG10-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG10-NEXT:    v_or_b32_sdwa v1, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; SDAG10-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_v3i8:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; SDAG1250-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; SDAG1250-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; SDAG1250-NEXT:    v_sub_nc_u16 v3, 0, v1
+; SDAG1250-NEXT:    v_sub_nc_u16 v4, 0, v0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
+; SDAG1250-NEXT:    v_max_i16 v1, v1, v3
+; SDAG1250-NEXT:    v_sub_nc_u16 v3, 0, v2
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; SDAG1250-NEXT:    v_max_i16 v0, v0, v4
+; SDAG1250-NEXT:    v_lshlrev_b16 v1, 8, v1
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG1250-NEXT:    v_max_i16 v2, v2, v3
+; SDAG1250-NEXT:    v_dual_lshlrev_b32 v1, 16, v2 :: v_dual_bitop2_b32 v0, v0, v1 bitop3:0x54
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG1250-NEXT:    v_and_b32_e32 v3, 0xffff, v0
+; SDAG1250-NEXT:    v_or_b32_e32 v1, v3, v1
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG1250-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_v3i8:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
+; GFX6-NEXT:    v_max_i32_e32 v2, v2, v3
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_v3i8:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0
+; GFX8-NEXT:    v_sub_u16_sdwa v4, v3, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT:    v_max_i16_sdwa v0, sext(v0), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_sub_u16_sdwa v4, v3, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT:    v_sub_u16_sdwa v3, v3, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT:    v_max_i16_sdwa v1, sext(v1), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    v_max_i16_sdwa v2, sext(v2), v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_v3i8:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX10-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX10-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX10-NEXT:    v_sub_nc_u16 v3, 0, v0
+; GFX10-NEXT:    v_sub_nc_u16 v4, 0, v1
+; GFX10-NEXT:    v_sub_nc_u16 v5, 0, v2
+; GFX10-NEXT:    v_max_i16 v0, v0, v3
+; GFX10-NEXT:    v_max_i16 v1, v1, v4
+; GFX10-NEXT:    v_max_i16 v2, v2, v5
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_v3i8:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_bfe_i32 v0, v0, 0, 8
+; GFX1250-NEXT:    v_bfe_i32 v1, v1, 0, 8
+; GFX1250-NEXT:    v_bfe_i32 v2, v2, 0, 8
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT:    v_sub_nc_u16 v3, 0, v0
+; GFX1250-NEXT:    v_sub_nc_u16 v4, 0, v1
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT:    v_sub_nc_u16 v5, 0, v2
+; GFX1250-NEXT:    v_max_i16 v0, v0, v3
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-NEXT:    v_max_i16 v1, v1, v4
+; GFX1250-NEXT:    v_max_i16 v2, v2, v5
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call <3 x i8> @llvm.abs.v3i8(<3 x i8> %arg, i1 false)
+  ret <3 x i8> %res
+}
+
+define amdgpu_cs <2 x i16> @abs_sgpr_v2i16(<2 x i16> inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_v2i16:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG6-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG6-NEXT:    s_abs_i32 s1, s1
+; SDAG6-NEXT:    s_lshl_b32 s2, s1, 16
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    s_or_b32 s0, s0, s2
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_v2i16:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_ashr_i32 s1, s0, 16
+; SDAG8-NEXT:    s_abs_i32 s1, s1
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_lshl_b32 s1, s1, 16
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    s_or_b32 s0, s0, s1
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_v2i16:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    v_pk_sub_i16 v0, 0, s0
+; SDAG10-NEXT:    v_pk_max_i16 v0, s0, v0
+; SDAG10-NEXT:    v_readfirstlane_b32 s0, v0
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_v2i16:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    v_pk_sub_i16 v0, 0, s0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; SDAG1250-NEXT:    v_pk_max_i16 v0, s0, v0
+; SDAG1250-NEXT:    v_readfirstlane_b32 s0, v0
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_v2i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i16 s0, s0
+; GFX6-NEXT:    s_sext_i32_i16 s1, s1
+; GFX6-NEXT:    s_abs_i32 s0, s0
+; GFX6-NEXT:    s_abs_i32 s1, s1
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_v2i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
+; GFX8-NEXT:    s_sext_i32_i16 s1, s1
+; GFX8-NEXT:    s_sext_i32_i16 s0, s0
+; GFX8-NEXT:    s_abs_i32 s1, s1
+; GFX8-NEXT:    s_abs_i32 s0, s0
+; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
+; GFX8-NEXT:    s_or_b32 s0, s0, s1
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_v2i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_sext_i32_i16 s1, s0
+; GFX10-NEXT:    s_ashr_i32 s0, s0, 16
+; GFX10-NEXT:    s_abs_i32 s1, s1
+; GFX10-NEXT:    s_abs_i32 s0, s0
+; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s1, s0
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_v2i16:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_sext_i32_i16 s1, s0
+; GFX1250-NEXT:    s_ashr_i32 s0, s0, 16
+; GFX1250-NEXT:    s_abs_i32 s1, s1
+; GFX1250-NEXT:    s_abs_i32 s0, s0
+; GFX1250-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT:    s_pack_ll_b32_b16 s0, s1, s0
+; GFX1250-NEXT:    ; return to shader part epilog
+  %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
+  ret <2 x i16> %res
+}
+
+define <2 x i16> @abs_vgpr_v2i16(<2 x i16> %arg) {
+; SDAG6-LABEL: abs_vgpr_v2i16:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; SDAG6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; SDAG6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
+; SDAG6-NEXT:    v_max_i32_e32 v0, v2, v0
+; SDAG6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
+; SDAG6-NEXT:    v_max_i32_e32 v1, v2, v1
+; SDAG6-NEXT:    v_lshlrev_b32_e32 v2, 16, v1
+; SDAG6-NEXT:    v_or_b32_e32 v0, v0, v2
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_v2i16:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_mov_b32_e32 v1, 0
+; SDAG8-NEXT:    v_sub_u16_sdwa v1, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; SDAG8-NEXT:    v_sub_u16_e32 v2, 0, v0
+; SDAG8-NEXT:    v_max_i16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; SDAG8-NEXT:    v_max_i16_e32 v0, v0, v2
+; SDAG8-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_v2i16:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_pk_sub_i16 v1, 0, v0
+; SDAG10-NEXT:    v_pk_max_i16 v0, v0, v1
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_v2i16:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_pk_sub_i16 v1, 0, v0
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; SDAG1250-NEXT:    v_pk_max_i16 v0, v0, v1
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_v2i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v0
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v2
+; GFX6-NEXT:    v_sub_i32_e32 v2, vcc, 0, v1
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v2
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_v2i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v2, 0
+; GFX8-NEXT:    v_sub_u16_e32 v1, 0, v0
+; GFX8-NEXT:    v_sub_u16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_max_i16_e32 v1, v0, v1
+; GFX8-NEXT:    v_max_i16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_v2i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_pk_sub_i16 v1, 0, v0
+; GFX10-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_v2i16:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_pk_sub_i16 v1, 0, v0
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT:    v_pk_max_i16 v0, v0, v1
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call <2 x i16> @llvm.abs.v2i16(<2 x i16> %arg, i1 false)
+  ret <2 x i16> %res
+}
+
+define amdgpu_cs <3 x i16> @abs_sgpr_v3i16(<3 x i16> inreg %arg) {
+; SDAG6-LABEL: abs_sgpr_v3i16:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG6-NEXT:    s_sext_i32_i16 s3, s2
+; SDAG6-NEXT:    s_abs_i32 s1, s1
+; SDAG6-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG6-NEXT:    s_lshl_b32 s2, s1, 16
+; SDAG6-NEXT:    s_abs_i32 s3, s3
+; SDAG6-NEXT:    s_abs_i32 s0, s0
+; SDAG6-NEXT:    s_lshr_b64 s[4:5], s[2:3], 16
+; SDAG6-NEXT:    s_or_b32 s0, s0, s2
+; SDAG6-NEXT:    s_mov_b32 s1, s4
+; SDAG6-NEXT:    s_mov_b32 s2, s3
+; SDAG6-NEXT:    ; return to shader part epilog
+;
+; SDAG8-LABEL: abs_sgpr_v3i16:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_ashr_i32 s2, s0, 16
+; SDAG8-NEXT:    s_abs_i32 s2, s2
+; SDAG8-NEXT:    s_sext_i32_i16 s0, s0
+; SDAG8-NEXT:    s_sext_i32_i16 s1, s1
+; SDAG8-NEXT:    s_abs_i32 s0, s0
+; SDAG8-NEXT:    s_lshl_b32 s2, s2, 16
+; SDAG8-NEXT:    s_abs_i32 s1, s1
+; SDAG8-NEXT:    s_or_b32 s0, s0, s2
+; SDAG8-NEXT:    ; return to shader part epilog
+;
+; SDAG10-LABEL: abs_sgpr_v3i16:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    v_pk_sub_i16 v0, 0, s0
+; SDAG10-NEXT:    v_pk_sub_i16 v1, 0, s1
+; SDAG10-NEXT:    v_pk_max_i16 v0, s0, v0
+; SDAG10-NEXT:    v_pk_max_i16 v1, s1, v1
+; SDAG10-NEXT:    v_readfirstlane_b32 s0, v0
+; SDAG10-NEXT:    v_readfirstlane_b32 s1, v1
+; SDAG10-NEXT:    ; return to shader part epilog
+;
+; SDAG1250-LABEL: abs_sgpr_v3i16:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    v_pk_sub_i16 v0, 0, s0
+; SDAG1250-NEXT:    v_pk_sub_i16 v1, 0, s1
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG1250-NEXT:    v_pk_max_i16 v0, s0, v0
+; SDAG1250-NEXT:    v_pk_max_i16 v1, s1, v1
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG1250-NEXT:    v_readfirstlane_b32 s0, v0
+; SDAG1250-NEXT:    v_readfirstlane_b32 s1, v1
+; SDAG1250-NEXT:    ; return to shader part epilog
+;
+; GFX6-LABEL: abs_sgpr_v3i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_sext_i32_i16 s0, s0
+; GFX6-NEXT:    s_sext_i32_i16 s1, s1
+; GFX6-NEXT:    s_sext_i32_i16 s2, s2
+; GFX6-NEXT:    s_abs_i32 s0, s0
+; GFX6-NEXT:    s_abs_i32 s1, s1
+; GFX6-NEXT:    s_abs_i32 s2, s2
+; GFX6-NEXT:    ; return to shader part epilog
+;
+; GFX8-LABEL: abs_sgpr_v3i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_lshr_b32 s2, s0, 16
+; GFX8-NEXT:    s_sext_i32_i16 s2, s2
+; GFX8-NEXT:    s_sext_i32_i16 s0, s0
+; GFX8-NEXT:    s_abs_i32 s2, s2
+; GFX8-NEXT:    s_abs_i32 s0, s0
+; GFX8-NEXT:    s_sext_i32_i16 s1, s1
+; GFX8-NEXT:    s_lshl_b32 s2, s2, 16
+; GFX8-NEXT:    s_abs_i32 s1, s1
+; GFX8-NEXT:    s_or_b32 s0, s0, s2
+; GFX8-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: abs_sgpr_v3i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_sext_i32_i16 s2, s0
+; GFX10-NEXT:    s_ashr_i32 s0, s0, 16
+; GFX10-NEXT:    s_abs_i32 s2, s2
+; GFX10-NEXT:    s_abs_i32 s0, s0
+; GFX10-NEXT:    s_sext_i32_i16 s1, s1
+; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s2, s0
+; GFX10-NEXT:    s_abs_i32 s1, s1
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX1250-LABEL: abs_sgpr_v3i16:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_sext_i32_i16 s2, s0
+; GFX1250-NEXT:    s_ashr_i32 s0, s0, 16
+; GFX1250-NEXT:    s_abs_i32 s2, s2
+; GFX1250-NEXT:    s_abs_i32 s0, s0
+; GFX1250-NEXT:    s_sext_i32_i16 s1, s1
+; GFX1250-NEXT:    s_pack_ll_b32_b16 s0, s2, s0
+; GFX1250-NEXT:    s_abs_i32 s1, s1
+; GFX1250-NEXT:    ; return to shader part epilog
+  %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
+  ret <3 x i16> %res
+}
+
+define <3 x i16> @abs_vgpr_v3i16(<3 x i16> %arg) {
+; SDAG6-LABEL: abs_vgpr_v3i16:
+; SDAG6:       ; %bb.0:
+; SDAG6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; SDAG6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; SDAG6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; SDAG6-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; SDAG6-NEXT:    v_max_i32_e32 v0, v3, v0
+; SDAG6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; SDAG6-NEXT:    v_max_i32_e32 v1, v3, v1
+; SDAG6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
+; SDAG6-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
+; SDAG6-NEXT:    v_max_i32_e32 v2, v3, v2
+; SDAG6-NEXT:    v_or_b32_e32 v0, v0, v1
+; SDAG6-NEXT:    v_alignbit_b32 v1, v2, v1, 16
+; SDAG6-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG8-LABEL: abs_vgpr_v3i16:
+; SDAG8:       ; %bb.0:
+; SDAG8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG8-NEXT:    v_mov_b32_e32 v2, 0
+; SDAG8-NEXT:    v_sub_u16_e32 v3, 0, v1
+; SDAG8-NEXT:    v_sub_u16_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; SDAG8-NEXT:    v_max_i16_e32 v1, v1, v3
+; SDAG8-NEXT:    v_sub_u16_e32 v3, 0, v0
+; SDAG8-NEXT:    v_max_i16_sdwa v2, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; SDAG8-NEXT:    v_max_i16_e32 v0, v0, v3
+; SDAG8-NEXT:    v_or_b32_e32 v0, v0, v2
+; SDAG8-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG10-LABEL: abs_vgpr_v3i16:
+; SDAG10:       ; %bb.0:
+; SDAG10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; SDAG10-NEXT:    v_pk_sub_i16 v2, 0, v0
+; SDAG10-NEXT:    v_pk_sub_i16 v3, 0, v1
+; SDAG10-NEXT:    v_pk_max_i16 v0, v0, v2
+; SDAG10-NEXT:    v_pk_max_i16 v1, v1, v3
+; SDAG10-NEXT:    s_setpc_b64 s[30:31]
+;
+; SDAG1250-LABEL: abs_vgpr_v3i16:
+; SDAG1250:       ; %bb.0:
+; SDAG1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; SDAG1250-NEXT:    s_wait_kmcnt 0x0
+; SDAG1250-NEXT:    v_pk_sub_i16 v2, 0, v0
+; SDAG1250-NEXT:    v_pk_sub_i16 v3, 0, v1
+; SDAG1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; SDAG1250-NEXT:    v_pk_max_i16 v0, v0, v2
+; SDAG1250-NEXT:    v_pk_max_i16 v1, v1, v3
+; SDAG1250-NEXT:    s_set_pc_i64 s[30:31]
+;
+; GFX6-LABEL: abs_vgpr_v3i16:
+; GFX6:       ; %bb.0:
+; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-NEXT:    v_bfe_i32 v0, v0, 0, 16
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v0
+; GFX6-NEXT:    v_bfe_i32 v1, v1, 0, 16
+; GFX6-NEXT:    v_max_i32_e32 v0, v0, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v1
+; GFX6-NEXT:    v_bfe_i32 v2, v2, 0, 16
+; GFX6-NEXT:    v_max_i32_e32 v1, v1, v3
+; GFX6-NEXT:    v_sub_i32_e32 v3, vcc, 0, v2
+; GFX6-NEXT:    v_max_i32_e32 v2, v2, v3
+; GFX6-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: abs_vgpr_v3i16:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    v_mov_b32_e32 v3, 0
+; GFX8-NEXT:    v_sub_u16_e32 v2, 0, v0
+; GFX8-NEXT:    v_sub_u16_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
+; GFX8-NEXT:    v_sub_u16_e32 v4, 0, v1
+; GFX8-NEXT:    v_max_i16_e32 v2, v0, v2
+; GFX8-NEXT:    v_max_i16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT:    v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT:    v_max_i16_e32 v1, v1, v4
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: abs_vgpr_v3i16:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    v_pk_sub_i16 v2, 0, v0
+; GFX10-NEXT:    v_sub_nc_u16 v3, 0, v1
+; GFX10-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX10-NEXT:    v_max_i16 v1, v1, v3
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX1250-LABEL: abs_vgpr_v3i16:
+; GFX1250:       ; %bb.0:
+; GFX1250-NEXT:    s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT:    s_wait_kmcnt 0x0
+; GFX1250-NEXT:    v_pk_sub_i16 v2, 0, v0
+; GFX1250-NEXT:    v_sub_nc_u16 v3, 0, v1
+; GFX1250-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1250-NEXT:    v_pk_max_i16 v0, v0, v2
+; GFX1250-NEXT:    v_max_i16 v1, v1, v3
+; GFX1250-NEXT:    s_set_pc_i64 s[30:31]
+  %res = call <3 x i16> @llvm.abs.v3i16(<3 x i16> %arg, i1 false)
+  ret <3 x i16> %res
+}