diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index c698b42b00d10..9d3a89380441a 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -10,6 +10,7 @@ tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info) tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info) +tablegen(LLVM XtensaGenSDNodeInfo.inc -gen-sd-node-info) tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget) add_public_tablegen_target(XtensaCommonTableGen) @@ -22,6 +23,7 @@ add_llvm_target(XtensaCodeGen XtensaISelDAGToDAG.cpp XtensaISelLowering.cpp XtensaRegisterInfo.cpp + XtensaSelectionDAGInfo.cpp XtensaSubtarget.cpp XtensaTargetMachine.cpp diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 959553de99392..655b40fc57b97 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -12,6 +12,7 @@ #include "MCTargetDesc/XtensaMCTargetDesc.h" #include "Xtensa.h" +#include "XtensaSelectionDAGInfo.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index c211777e69894..71c98621c81ee 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -15,6 +15,7 @@ #include "XtensaConstantPoolValue.h" #include "XtensaInstrInfo.h" #include "XtensaMachineFunctionInfo.h" +#include "XtensaSelectionDAGInfo.h" #include "XtensaSubtarget.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/CallingConvLower.h" @@ -1510,58 +1511,6 @@ SDValue XtensaTargetLowering::LowerOperation(SDValue Op, } } -const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { - switch (Opcode) { - case XtensaISD::BR_JT: - return "XtensaISD::BR_JT"; - case XtensaISD::CALL: - return "XtensaISD::CALL"; - case XtensaISD::CALLW8: - return "XtensaISD::CALLW8"; - case XtensaISD::EXTUI: - return "XtensaISD::EXTUI"; - case XtensaISD::MOVSP: - return "XtensaISD::MOVSP"; - case XtensaISD::PCREL_WRAPPER: - return "XtensaISD::PCREL_WRAPPER"; - case XtensaISD::RET: - return "XtensaISD::RET"; - case XtensaISD::RETW: - return "XtensaISD::RETW"; - case XtensaISD::RUR: - return "XtensaISD::RUR"; - case XtensaISD::SELECT_CC: - return "XtensaISD::SELECT_CC"; - case XtensaISD::SELECT_CC_FP: - return "XtensaISD::SELECT_CC_FP"; - case XtensaISD::SRCL: - return "XtensaISD::SRCL"; - case XtensaISD::SRCR: - return "XtensaISD::SRCR"; - case XtensaISD::CMPUO: - return "XtensaISD::CMPUO"; - case XtensaISD::CMPUEQ: - return "XtensaISD::CMPUEQ"; - case XtensaISD::CMPULE: - return "XtensaISD::CMPULE"; - case XtensaISD::CMPULT: - return "XtensaISD::CMPULT"; - case XtensaISD::CMPOEQ: - return "XtensaISD::CMPOEQ"; - case XtensaISD::CMPOLE: - return "XtensaISD::CMPOLE"; - case XtensaISD::CMPOLT: - return "XtensaISD::CMPOLT"; - case XtensaISD::MADD: - return "XtensaISD::MADD"; - case XtensaISD::MSUB: - return "XtensaISD::MSUB"; - case XtensaISD::MOVS: - return "XtensaISD::MOVS"; - } - return nullptr; -} - TargetLowering::AtomicExpansionKind XtensaTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const { return AtomicExpansionKind::CmpXChg; diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index d84cbdb6afcef..829de0fe9c161 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -20,67 +20,6 @@ namespace llvm { -namespace XtensaISD { -enum { - FIRST_NUMBER = ISD::BUILTIN_OP_END, - BR_JT, - - // Calls a function. Operand 0 is the chain operand and operand 1 - // is the target address. The arguments start at operand 2. - // There is an optional glue operand at the end. - CALL, - // Call with rotation window by 8 registers - CALLW8, - - // Extract unsigned immediate. Operand 0 is value, operand 1 - // is bit position of the field [0..31], operand 2 is bit size - // of the field [1..16] - EXTUI, - - MOVSP, - - // Wraps a TargetGlobalAddress that should be loaded using PC-relative - // accesses. Operand 0 is the address. - PCREL_WRAPPER, - RET, - RETW, - - RUR, - - // Select with condition operator - This selects between a true value and - // a false value (ops #2 and #3) based on the boolean result of comparing - // the lhs and rhs (ops #0 and #1) of a conditional expression with the - // condition code in op #4 - SELECT_CC, - // Select with condition operator - This selects between a true value and - // a false value (ops #2 and #3) based on the boolean result of comparing - // f32 operands lhs and rhs (ops #0 and #1) of a conditional expression - // with the condition code in op #4 and boolean branch kind in op #5 - SELECT_CC_FP, - - // SRCL(R) performs shift left(right) of the concatenation of 2 registers - // and returns high(low) 32-bit part of 64-bit result - SRCL, - // Shift Right Combined - SRCR, - - // Floating point unordered compare conditions - CMPUEQ, - CMPULE, - CMPULT, - CMPUO, - // Floating point compare conditions - CMPOEQ, - CMPOLE, - CMPOLT, - // FP multipy-add/sub - MADD, - MSUB, - // FP move - MOVS, -}; -} - class XtensaSubtarget; class XtensaTargetLowering : public TargetLowering { @@ -104,8 +43,6 @@ class XtensaTargetLowering : public TargetLowering { bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; - const char *getTargetNodeName(unsigned Opcode) const override; - bool isFPImmLegal(const APFloat &Imm, EVT VT, bool ForCodeSize) const override; diff --git a/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp new file mode 100644 index 0000000000000..79fa81d424809 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.cpp @@ -0,0 +1,19 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "XtensaSelectionDAGInfo.h" + +#define GET_SDNODE_DESC +#include "XtensaGenSDNodeInfo.inc" + +using namespace llvm; + +XtensaSelectionDAGInfo::XtensaSelectionDAGInfo() + : SelectionDAGGenTargetInfo(XtensaGenSDNodeInfo) {} + +XtensaSelectionDAGInfo::~XtensaSelectionDAGInfo() = default; diff --git a/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h new file mode 100644 index 0000000000000..6fb22817db9f3 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaSelectionDAGInfo.h @@ -0,0 +1,28 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H +#define LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H + +#include "llvm/CodeGen/SelectionDAGTargetInfo.h" + +#define GET_SDNODE_ENUM +#include "XtensaGenSDNodeInfo.inc" + +namespace llvm { + +class XtensaSelectionDAGInfo : public SelectionDAGGenTargetInfo { +public: + XtensaSelectionDAGInfo(); + + ~XtensaSelectionDAGInfo() override; +}; + +} // namespace llvm + +#endif // LLVM_LIB_TARGET_XTENSA_XTENSASELECTIONDAGINFO_H diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp index 6b1d3255db247..c1a1efc85eb55 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "XtensaSubtarget.h" +#include "XtensaSelectionDAGInfo.h" #include "llvm/IR/GlobalValue.h" #include "llvm/Support/Debug.h" @@ -39,4 +40,12 @@ XtensaSubtarget::XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) : XtensaGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), - TSInfo(), FrameLowering(*this) {} + FrameLowering(*this) { + TSInfo = std::make_unique(); +} + +XtensaSubtarget::~XtensaSubtarget() = default; + +const SelectionDAGTargetInfo *XtensaSubtarget::getSelectionDAGInfo() const { + return TSInfo.get(); +} diff --git a/llvm/lib/Target/Xtensa/XtensaSubtarget.h b/llvm/lib/Target/Xtensa/XtensaSubtarget.h index b406534a0ec77..6a5201b6f6f32 100644 --- a/llvm/lib/Target/Xtensa/XtensaSubtarget.h +++ b/llvm/lib/Target/Xtensa/XtensaSubtarget.h @@ -17,7 +17,6 @@ #include "XtensaISelLowering.h" #include "XtensaInstrInfo.h" #include "XtensaRegisterInfo.h" -#include "llvm/CodeGen/SelectionDAGTargetInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" @@ -38,7 +37,7 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { const Triple &TargetTriple; XtensaInstrInfo InstrInfo; XtensaTargetLowering TLInfo; - SelectionDAGTargetInfo TSInfo; + std::unique_ptr TSInfo; XtensaFrameLowering FrameLowering; XtensaSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); @@ -47,6 +46,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { XtensaSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM); + ~XtensaSubtarget() override; + const Triple &getTargetTriple() const { return TargetTriple; } const TargetFrameLowering *getFrameLowering() const override { @@ -60,9 +61,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo { const XtensaTargetLowering *getTargetLowering() const override { return &TLInfo; } - const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { - return &TSInfo; - } + + const SelectionDAGTargetInfo *getSelectionDAGInfo() const override; bool hasDensity() const { return HasDensity; } bool hasMAC16() const { return HasMAC16; }