Skip to content

[SPARC] Mark branches as being expensive in early Niagara CPUs #166489

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Nov 5, 2025
Merged

[SPARC] Mark branches as being expensive in early Niagara CPUs #166489

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
bc56d36
[SPARC] Mark branches as being expensive in early Niagara CPUs
koachan Apr 4, 2025
57f8b6c
Update tests
koachan Nov 5, 2025
cb3e05c
Update tests
koachan Nov 5, 2025
ab573a1
Update tests
koachan Nov 5, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
12 changes: 9 additions & 3 deletions llvm/lib/Target/Sparc/Sparc.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,9 @@ def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true",
"rd %pc, %XX is slow", [FeatureV9]>;

def TuneNoPredictor : SubtargetFeature<"no-predictor", "HasNoPredictor", "true",
"Processor has no branch predictor, branches stall execution", []>;

//==== Features added predmoninantly for LEON subtarget support
include "LeonFeatures.td"

Expand Down Expand Up @@ -174,12 +177,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2, FeatureUA2005]>;
FeatureVIS2, FeatureUA2005],
[TuneNoPredictor]>;
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
FeatureVIS, FeatureVIS2, FeatureUA2005],
[TuneNoPredictor]>;
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005, FeatureUA2007]>;
FeatureUA2005, FeatureUA2007],
[TuneNoPredictor]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005, FeatureUA2007, FeatureOSA2011,
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/Sparc/SparcISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2000,6 +2000,14 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,

setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

// Some processors have no branch predictor and have pipelines longer than
// what can be covered by the delay slot. This results in a stall, so mark
// branches to be expensive on those processors.
setJumpIsExpensive(Subtarget->hasNoPredictor());
// The high cost of branching means that using conditional moves will
// still be profitable even if the condition is predictable.
PredictableSelectIsExpensive = !isJumpExpensive();

setMinFunctionAlignment(Align(4));

computeRegisterProperties(Subtarget->getRegisterInfo());
Expand Down
33 changes: 33 additions & 0 deletions llvm/test/CodeGen/SPARC/select-earlyniagara.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Copy link
Contributor

@s-barannikov s-barannikov Nov 5, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The test should show the difference in codegen between subtargets with and without branch predictor.

Copy link
Contributor Author

@koachan koachan Nov 5, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Done~

; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparc -mcpu=v9 | FileCheck --check-prefix=SPARC %s
; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparcv9 -mcpu=v9 | FileCheck --check-prefix=SPARC64 %s

;; Early Niagara processors should prefer conditional moves over branches
;; even when it's predictable.

define i32 @cinc(i32 %cond, i32 %num) #0 {
; SPARC-LABEL: cinc:
; SPARC: ! %bb.0: ! %entry
; SPARC-NEXT: add %o1, 1, %o2
; SPARC-NEXT: cmp %o0, 0
; SPARC-NEXT: move %icc, %o2, %o1
; SPARC-NEXT: retl
; SPARC-NEXT: mov %o1, %o0
;
; SPARC64-LABEL: cinc:
; SPARC64: ! %bb.0: ! %entry
; SPARC64-NEXT: add %o1, 1, %o2
; SPARC64-NEXT: cmp %o0, 0
; SPARC64-NEXT: move %icc, %o2, %o1
; SPARC64-NEXT: retl
; SPARC64-NEXT: mov %o1, %o0
entry:
%add = add nsw i32 %num, 1
%cmp = icmp eq i32 %cond, 0
%exp = call i1 @llvm.expect.i1(i1 %cmp, i1 0)
%ret = select i1 %exp, i32 %add, i32 %num
ret i32 %ret
}
declare i1 @llvm.expect.i1(i1, i1)

attributes #0 = { nounwind "tune-cpu"="niagara" }