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[SPARC] Mark branches as being expensive in early Niagara CPUs #166489

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merged 4 commits into from
Nov 5, 2025
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[SPARC] Mark branches as being expensive in early Niagara CPUs #166489

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[SPARC] Mark branches as being expensive in early Niagara CPUs
koachan Apr 4, 2025
57f8b6c
Update tests
koachan Nov 5, 2025
cb3e05c
Update tests
koachan Nov 5, 2025
ab573a1
Update tests
koachan Nov 5, 2025
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12 changes: 9 additions & 3 deletions llvm/lib/Target/Sparc/Sparc.td
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Original file line number Diff line number Diff line change
Expand Up @@ -95,6 +95,9 @@ def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
def TuneSlowRDPC : SubtargetFeature<"slow-rdpc", "HasSlowRDPC", "true",
"rd %pc, %XX is slow", [FeatureV9]>;

def TuneNoPredictor : SubtargetFeature<"no-predictor", "HasNoPredictor", "true",
"Processor has no branch predictor, branches stall execution", []>;

//==== Features added predmoninantly for LEON subtarget support
include "LeonFeatures.td"

Expand Down Expand Up @@ -174,12 +177,15 @@ def : Proc<"ultrasparc3", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2],
[TuneSlowRDPC]>;
def : Proc<"niagara", [FeatureV9, FeatureV8Deprecated, FeatureVIS,
FeatureVIS2, FeatureUA2005]>;
FeatureVIS2, FeatureUA2005],
[TuneNoPredictor]>;
def : Proc<"niagara2", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureUA2005]>;
FeatureVIS, FeatureVIS2, FeatureUA2005],
[TuneNoPredictor]>;
def : Proc<"niagara3", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005, FeatureUA2007]>;
FeatureUA2005, FeatureUA2007],
[TuneNoPredictor]>;
def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
FeatureVIS, FeatureVIS2, FeatureVIS3,
FeatureUA2005, FeatureUA2007, FeatureOSA2011,
Expand Down
8 changes: 8 additions & 0 deletions llvm/lib/Target/Sparc/SparcISelLowering.cpp
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Expand Up @@ -2000,6 +2000,14 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,

setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);

// Some processors have no branch predictor and have pipelines longer than
// what can be covered by the delay slot. This results in a stall, so mark
// branches to be expensive on those processors.
setJumpIsExpensive(Subtarget->hasNoPredictor());
// The high cost of branching means that using conditional moves will
// still be profitable even if the condition is predictable.
PredictableSelectIsExpensive = !isJumpExpensive();

setMinFunctionAlignment(Align(4));

computeRegisterProperties(Subtarget->getRegisterInfo());
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43 changes: 43 additions & 0 deletions llvm/test/CodeGen/SPARC/select-earlyniagara.ll
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@@ -0,0 +1,43 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@s-barannikov s-barannikov Nov 5, 2025

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The test should show the difference in codegen between subtargets with and without branch predictor.

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@koachan koachan Nov 5, 2025

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Done~

; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparc -mcpu=v9 | FileCheck --check-prefix=SPARC %s
; RUN: llc -O3 < %s -relocation-model=pic -mtriple=sparcv9 -mcpu=v9 | FileCheck --check-prefix=SPARC64 %s

;; Early Niagara processors should prefer conditional moves over branches
;; even when it's predictable.

define i32 @cinc(i32 %cond, i32 %num) #0 {
; SPARC-LABEL: cinc:
; SPARC: ! %bb.0: ! %entry
; SPARC-NEXT: cmp %o0, 0
; SPARC-NEXT: bne %icc, .LBB0_2
; SPARC-NEXT: mov %o1, %o0
; SPARC-NEXT: ! %bb.1: ! %inc
; SPARC-NEXT: add %o0, 1, %o0
; SPARC-NEXT: .LBB0_2: ! %cont
; SPARC-NEXT: retl
; SPARC-NEXT: nop
;
; SPARC64-LABEL: cinc:
; SPARC64: ! %bb.0: ! %entry
; SPARC64-NEXT: cmp %o0, 0
; SPARC64-NEXT: bne %icc, .LBB0_2
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@koachan koachan Nov 5, 2025

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I'm tuning this for niagara and from debugging dumps, I see that branches have been properly marked as expensive and PredictableSelectIsExpensive is false, yet the codegen still chooses branches over conditional moves.
How do I convince the codegen to emit conditional moves here?

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@s-barannikov s-barannikov Nov 5, 2025

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I guess this is because the input IR contains explicit branches. llc doesn't run CFG optimizer.
Consider rewriting this test to use select instruction

; SPARC64-NEXT: mov %o1, %o0
; SPARC64-NEXT: ! %bb.1: ! %inc
; SPARC64-NEXT: add %o0, 1, %o0
; SPARC64-NEXT: .LBB0_2: ! %cont
; SPARC64-NEXT: retl
; SPARC64-NEXT: nop
entry:
%cmp = icmp eq i32 %cond, 0
%exp = call i1 @llvm.expect.i1(i1 %cmp, i1 0)
br i1 %exp, label %inc, label %cont
inc:
%add = add nsw i32 %num, 1
br label %cont
cont:
%phi = phi i32 [ %add, %inc ], [ %num, %entry ]
ret i32 %phi
}
declare i1 @llvm.expect.i1(i1, i1)

attributes #0 = { nounwind "tune-cpu"="niagara" }
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