diff --git a/llvm/docs/CommandGuide/llvm-objdump.rst b/llvm/docs/CommandGuide/llvm-objdump.rst
index aaf38f84b92e5..44649c670dd42 100644
--- a/llvm/docs/CommandGuide/llvm-objdump.rst
+++ b/llvm/docs/CommandGuide/llvm-objdump.rst
@@ -284,7 +284,7 @@ OPTIONS
   any analysis with a special representation (i.e. BlockFrequency,
   BranchProbability, etc) are printed as raw hex values.
 
-  Only supported for AArch64, BPF, PowerPC, and X86.
+  Only supported for AArch64, BPF, PowerPC, RISC-V, and X86.
 
   Example:
     A non-symbolized branch instruction with a local target and pc-relative memory access like
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index bfe68274eae3f..61ff14f7f6255 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -135,6 +135,7 @@ Changes to the RISC-V Backend
 * Adds experimental support for the 'Zibi` (Branch with Immediate) extension.
 * Add support for Zvfofp8min (OFP8 conversion extension)
 * Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension).
+* `llvm-objdump` now has support for `--symbolize-operands` with RISC-V.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 7b9c4b3e800cd..02bdbb8c5155c 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -16,6 +16,7 @@
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCInstrAnalysis.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/CommandLine.h"
@@ -108,6 +109,10 @@ void RISCVInstPrinter::printBranchOperand(const MCInst *MI, uint64_t Address,
                                           unsigned OpNo,
                                           const MCSubtargetInfo &STI,
                                           raw_ostream &O) {
+  // Do not print the numeric target address when symbolizing.
+  if (SymbolizeOperands)
+    return;
+
   const MCOperand &MO = MI->getOperand(OpNo);
   if (!MO.isImm())
     return printOperand(MI, OpNo, STI, O);
diff --git a/llvm/test/MC/RISCV/symbolize-operands.s b/llvm/test/MC/RISCV/symbolize-operands.s
new file mode 100644
index 0000000000000..cad1f3d265342
--- /dev/null
+++ b/llvm/test/MC/RISCV/symbolize-operands.s
@@ -0,0 +1,43 @@
+# RUN: llvm-mc -triple=riscv32 < %s -mattr=-relax -filetype=obj -o - \
+# RUN: | llvm-objdump -d --no-leading-addr --no-show-raw-insn --symbolize-operands - \
+# RUN: | FileCheck %s
+
+# CHECK-LABEL: <.text>:
+  .text
+  .p2align  2
+# CHECK: blez a0, <L3>
+  blez a0, .LBB0_6
+  li a3, 0
+  li a2, 0
+# CHECK: j <L1>
+  j .LBB0_3
+# CHECK-NEXT: <L0>:
+.LBB0_2:
+  addi a3, a3, 1
+# CHECK: beq a3, a0, <L4>
+  beq a3, a0, .LBB0_7
+# CHECK-NEXT: <L1>:
+.LBB0_3:
+  slli a4, a3, 2
+  add a4, a1, a4
+  lw a5, 0(a4)
+  lbu a4, 0(a5)
+# CHECK: beqz a4, <L0>
+  beqz a4, .LBB0_2
+  addi a5, a5, 1
+# CHECK: <L2>
+.LBB0_5:
+  add a2, a2, a4
+  lbu a4, 0(a5)
+  addi a5, a5, 1
+# CHECK: bnez a4, <L2>
+  bnez a4, .LBB0_5
+# CHECK-NEXT: j <L0>
+  j .LBB0_2
+# CHECK-NEXT: <L3>:
+.LBB0_6:
+  li a2, 0
+# CHECK: <L4>:
+.LBB0_7:
+  mv a0, a2
+  ret
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index 3ec644a472bfc..0153badb6603e 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1571,7 +1571,8 @@ collectLocalBranchTargets(ArrayRef<uint8_t> Bytes, MCInstrAnalysis *MIA,
   const bool isX86 = STI->getTargetTriple().isX86();
   const bool isAArch64 = STI->getTargetTriple().isAArch64();
   const bool isBPF = STI->getTargetTriple().isBPF();
-  if (!isPPC && !isX86 && !isAArch64 && !isBPF)
+  const bool isRISCV = STI->getTargetTriple().isRISCV();
+  if (!isPPC && !isX86 && !isAArch64 && !isBPF && !isRISCV)
     return;
 
   if (MIA)