Skip to content

[Clang] Generalize interp__builtin_ia32_shuffle_generic to handle single op permute shuffles. #167236

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 4 commits into from
Nov 11, 2025
Merged

[Clang] Generalize interp__builtin_ia32_shuffle_generic to handle single op permute shuffles. #167236

Show file tree
Hide file tree
Changes from 1 commit
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
7dce6c6
Generalize interp__builtin_ia32_shuffle_generic to handle single op p…
TelGome Nov 9, 2025
83aa1fd
Fix style and format
TelGome Nov 11, 2025
5f7f103
Merge branch 'main' into issue_166342
RKSimon Nov 11, 2025
46b0fa2
Merge branch 'main' into issue_166342
RKSimon Nov 11, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
221 changes: 90 additions & 131 deletions clang/lib/AST/ByteCode/InterpBuiltin.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2841,76 +2841,6 @@ static bool interp__builtin_blend(InterpState &S, CodePtr OpPC,
return true;
}

static bool interp__builtin_ia32_pshufb(InterpState &S, CodePtr OpPC,
const CallExpr *Call) {
assert(Call->getNumArgs() == 2 && "masked forms handled via select*");
const Pointer &Control = S.Stk.pop<Pointer>();
const Pointer &Src = S.Stk.pop<Pointer>();
const Pointer &Dst = S.Stk.peek<Pointer>();

unsigned NumElems = Dst.getNumElems();
assert(NumElems == Control.getNumElems());
assert(NumElems == Dst.getNumElems());

for (unsigned Idx = 0; Idx != NumElems; ++Idx) {
uint8_t Ctlb = static_cast<uint8_t>(Control.elem<int8_t>(Idx));

if (Ctlb & 0x80) {
Dst.elem<int8_t>(Idx) = 0;
} else {
unsigned LaneBase = (Idx / 16) * 16;
unsigned SrcOffset = Ctlb & 0x0F;
unsigned SrcIdx = LaneBase + SrcOffset;

Dst.elem<int8_t>(Idx) = Src.elem<int8_t>(SrcIdx);
}
}
Dst.initializeAllElements();
return true;
}

static bool interp__builtin_ia32_pshuf(InterpState &S, CodePtr OpPC,
const CallExpr *Call, bool IsShufHW) {
assert(Call->getNumArgs() == 2 && "masked forms handled via select*");
APSInt ControlImm = popToAPSInt(S, Call->getArg(1));
const Pointer &Src = S.Stk.pop<Pointer>();
const Pointer &Dst = S.Stk.peek<Pointer>();

unsigned NumElems = Dst.getNumElems();
PrimType ElemT = Dst.getFieldDesc()->getPrimType();

unsigned ElemBits = static_cast<unsigned>(primSize(ElemT) * 8);
if (ElemBits != 16 && ElemBits != 32)
return false;

unsigned LaneElts = 128u / ElemBits;
assert(LaneElts && (NumElems % LaneElts == 0));

uint8_t Ctl = static_cast<uint8_t>(ControlImm.getZExtValue());

for (unsigned Idx = 0; Idx != NumElems; Idx++) {
unsigned LaneBase = (Idx / LaneElts) * LaneElts;
unsigned LaneIdx = Idx % LaneElts;
unsigned SrcIdx = Idx;
unsigned Sel = (Ctl >> (2 * (LaneIdx & 0x3))) & 0x3;
if (ElemBits == 32) {
SrcIdx = LaneBase + Sel;
} else {
constexpr unsigned HalfSize = 4;
bool InHigh = LaneIdx >= HalfSize;
if (!IsShufHW && !InHigh) {
SrcIdx = LaneBase + Sel;
} else if (IsShufHW && InHigh) {
SrcIdx = LaneBase + HalfSize + Sel;
}
}

INT_TYPE_SWITCH_NO_BOOL(ElemT, { Dst.elem<T>(Idx) = Src.elem<T>(SrcIdx); });
}
Dst.initializeAllElements();
return true;
}

static bool interp__builtin_ia32_test_op(
InterpState &S, CodePtr OpPC, const CallExpr *Call,
llvm::function_ref<bool(const APInt &A, const APInt &B)> Fn) {
Expand Down Expand Up @@ -3377,61 +3307,46 @@ static bool interp__builtin_ia32_vpconflict(InterpState &S, CodePtr OpPC,
return true;
}

static bool interp__builtin_x86_byteshift(
InterpState &S, CodePtr OpPC, const CallExpr *Call, unsigned ID,
llvm::function_ref<APInt(const Pointer &, unsigned Lane, unsigned I,
unsigned Shift)>
Fn) {
assert(Call->getNumArgs() == 2);

APSInt ImmAPS = popToAPSInt(S, Call->getArg(1));
uint64_t Shift = ImmAPS.getZExtValue() & 0xff;

const Pointer &Src = S.Stk.pop<Pointer>();
if (!Src.getFieldDesc()->isPrimitiveArray())
return false;

unsigned NumElems = Src.getNumElems();
const Pointer &Dst = S.Stk.peek<Pointer>();
PrimType ElemT = Src.getFieldDesc()->getPrimType();

for (unsigned Lane = 0; Lane != NumElems; Lane += 16) {
for (unsigned I = 0; I != 16; ++I) {
unsigned Base = Lane + I;
APSInt Result = APSInt(Fn(Src, Lane, I, Shift));
INT_TYPE_SWITCH_NO_BOOL(ElemT,
{ Dst.elem<T>(Base) = static_cast<T>(Result); });
}
}

Dst.initializeAllElements();

return true;
}

static bool interp__builtin_ia32_shuffle_generic(
InterpState &S, CodePtr OpPC, const CallExpr *Call,
llvm::function_ref<std::pair<unsigned, int>(unsigned, unsigned)>
GetSourceIndex) {

assert(Call->getNumArgs() == 3);
assert(Call->getNumArgs() == 2 || Call->getNumArgs() == 3);

unsigned ShuffleMask = 0;
Pointer A, MaskVector, B;

QualType Arg2Type = Call->getArg(2)->getType();
bool IsVectorMask = false;
if (Arg2Type->isVectorType()) {
IsVectorMask = true;
B = S.Stk.pop<Pointer>();
MaskVector = S.Stk.pop<Pointer>();
A = S.Stk.pop<Pointer>();
} else if (Arg2Type->isIntegerType()) {
ShuffleMask = popToAPSInt(S, Call->getArg(2)).getZExtValue();
B = S.Stk.pop<Pointer>();
A = S.Stk.pop<Pointer>();
bool IsSingleOperand = (Call->getNumArgs() == 2);

if (IsSingleOperand) {
QualType MaskType = Call->getArg(1)->getType();
if (MaskType->isVectorType()) {
IsVectorMask = true;
MaskVector = S.Stk.pop<Pointer>();
A = S.Stk.pop<Pointer>();
B = A;
} else if (MaskType->isIntegerType()) {
ShuffleMask = popToAPSInt(S, Call->getArg(1)).getZExtValue();
A = S.Stk.pop<Pointer>();
B = A;
} else {
return false;
}
} else {
return false;
QualType Arg2Type = Call->getArg(2)->getType();
if (Arg2Type->isVectorType()) {
IsVectorMask = true;
B = S.Stk.pop<Pointer>();
MaskVector = S.Stk.pop<Pointer>();
A = S.Stk.pop<Pointer>();
} else if (Arg2Type->isIntegerType()) {
ShuffleMask = popToAPSInt(S, Call->getArg(2)).getZExtValue();
B = S.Stk.pop<Pointer>();
A = S.Stk.pop<Pointer>();
} else {
return false;
}
}

QualType Arg0Type = Call->getArg(0)->getType();
Expand All @@ -3455,6 +3370,7 @@ static bool interp__builtin_ia32_shuffle_generic(
ShuffleMask = static_cast<unsigned>(MaskVector.elem<T>(DstIdx));
});
}

auto [SrcVecIdx, SrcIdx] = GetSourceIndex(DstIdx, ShuffleMask);

if (SrcIdx < 0) {
Expand Down Expand Up @@ -4555,22 +4471,59 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
case X86::BI__builtin_ia32_pshufb128:
case X86::BI__builtin_ia32_pshufb256:
case X86::BI__builtin_ia32_pshufb512:
return interp__builtin_ia32_pshufb(S, OpPC, Call);
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call, [](unsigned DstIdx, unsigned ShuffleMask) {
uint8_t Ctlb = static_cast<uint8_t>(ShuffleMask);
if (Ctlb & 0x80) {
return std::make_pair(0, -1);
} else {
Copy link
Collaborator

@RKSimon RKSimon Nov 11, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

(style) break if-else chains with returns:

if (Ctlb & 0x80)
  return std::make_pair(0, -1);

unsigned LaneBase = (DstIdx / 16) * 16;
unsigned SrcOffset = Ctlb & 0x0F;
unsigned SrcIdx = LaneBase + SrcOffset;
return std::make_pair(0, static_cast<int>(SrcIdx));

(Similar request for the other cases below)

Copy link
Contributor Author

@TelGome TelGome Nov 11, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

The style and format have been revised.

unsigned LaneBase = (DstIdx / 16) * 16;
unsigned SrcOffset = Ctlb & 0x0F;
unsigned SrcIdx = LaneBase + SrcOffset;
return std::make_pair(0, static_cast<int>(SrcIdx));
}
});

case X86::BI__builtin_ia32_pshuflw:
case X86::BI__builtin_ia32_pshuflw256:
case X86::BI__builtin_ia32_pshuflw512:
return interp__builtin_ia32_pshuf(S, OpPC, Call, false);
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call, [](unsigned DstIdx, unsigned ShuffleMask) {
unsigned LaneBase = (DstIdx / 8) * 8;
unsigned LaneIdx = DstIdx % 8;
if (LaneIdx < 4) {
unsigned Sel = (ShuffleMask >> (2 * LaneIdx)) & 0x3;
return std::make_pair(0, static_cast<int>(LaneBase + Sel));
} else {
return std::make_pair(0, static_cast<int>(DstIdx));
}
});

case X86::BI__builtin_ia32_pshufhw:
case X86::BI__builtin_ia32_pshufhw256:
case X86::BI__builtin_ia32_pshufhw512:
return interp__builtin_ia32_pshuf(S, OpPC, Call, true);
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call, [](unsigned DstIdx, unsigned ShuffleMask) {
unsigned LaneBase = (DstIdx / 8) * 8;
unsigned LaneIdx = DstIdx % 8;
if (LaneIdx >= 4) {
unsigned Sel = (ShuffleMask >> (2 * (LaneIdx - 4))) & 0x3;
return std::make_pair(0, static_cast<int>(LaneBase + 4 + Sel));
} else {
return std::make_pair(0, static_cast<int>(DstIdx));
}
});
Copy link
Collaborator

@RKSimon RKSimon Nov 11, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

extra brace? clang-format?

Copy link
Contributor Author

@TelGome TelGome Nov 11, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sorry, I'm not very familiar with the clang-format. I've checked the code and removed the extra brace.


case X86::BI__builtin_ia32_pshufd:
case X86::BI__builtin_ia32_pshufd256:
case X86::BI__builtin_ia32_pshufd512:
return interp__builtin_ia32_pshuf(S, OpPC, Call, false);
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call, [](unsigned DstIdx, unsigned ShuffleMask) {
unsigned LaneBase = (DstIdx / 4) * 4;
unsigned LaneIdx = DstIdx % 4;
unsigned Sel = (ShuffleMask >> (2 * LaneIdx)) & 0x3;
return std::make_pair(0, static_cast<int>(LaneBase + Sel));
});

case X86::BI__builtin_ia32_kandqi:
case X86::BI__builtin_ia32_kandhi:
Expand Down Expand Up @@ -4728,13 +4681,17 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
// The lane width is hardcoded to 16 to match the SIMD register size,
// but the algorithm processes one byte per iteration,
// so APInt(8, ...) is correct and intentional.
return interp__builtin_x86_byteshift(
S, OpPC, Call, BuiltinID,
[](const Pointer &Src, unsigned Lane, unsigned I, unsigned Shift) {
if (I < Shift) {
return APInt(8, 0);
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call,
[](unsigned DstIdx, unsigned Shift) -> std::pair<unsigned, int> {
unsigned LaneBase = (DstIdx / 16) * 16;
unsigned LaneIdx = DstIdx % 16;
if (LaneIdx < Shift) {
return std::make_pair(0, -1);
}
return APInt(8, Src.elem<uint8_t>(Lane + I - Shift));

return std::make_pair(0, static_cast<int>(LaneBase + LaneIdx - Shift));

});

case X86::BI__builtin_ia32_psrldqi128_byteshift:
Expand All @@ -4744,14 +4701,16 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call,
// The lane width is hardcoded to 16 to match the SIMD register size,
// but the algorithm processes one byte per iteration,
// so APInt(8, ...) is correct and intentional.
return interp__builtin_x86_byteshift(
S, OpPC, Call, BuiltinID,
[](const Pointer &Src, unsigned Lane, unsigned I, unsigned Shift) {
if (I + Shift < 16) {
return APInt(8, Src.elem<uint8_t>(Lane + I + Shift));
return interp__builtin_ia32_shuffle_generic(
S, OpPC, Call,
[](unsigned DstIdx, unsigned Shift) -> std::pair<unsigned, int> {
unsigned LaneBase = (DstIdx / 16) * 16;
unsigned LaneIdx = DstIdx % 16;
if (LaneIdx + Shift < 16) {
return std::make_pair(0, static_cast<int>(LaneBase + LaneIdx + Shift));
}

return APInt(8, 0);
return std::make_pair(0, -1);
});

default:
Expand Down
Loading
Loading