[AMDGPU] Adding instruction specific features #167809
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@@ -166,6 +166,13 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, | |
| bool HasMAIInsts = false; | ||
| bool HasFP8Insts = false; | ||
| bool HasFP8ConversionInsts = false; | ||
| bool HasVCUBEInsts = false; | ||
| bool HasVLERPInsts = false; | ||
| bool HasVSADInsts = false; | ||
| bool HasVQSADInsts = false; | ||
| bool HasVCVTNORMInsts = false; | ||
| bool HasVCVTPKNORMVOP2Insts = false; | ||
| bool HasVCVTPKNORMVOP3Insts = false; | ||
| bool HasFP8E5M3Insts = false; | ||
| bool HasCvtFP8Vop1Bug = false; | ||
| bool HasPkFmacF16Inst = false; | ||
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@@ -892,6 +899,20 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, | |
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| bool hasFP8ConversionInsts() const { return HasFP8ConversionInsts; } | ||
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| bool hasVCUBEInsts() const { return HasVCUBEInsts; } | ||
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| bool hasVLERPInsts() const { return HasVLERPInsts; } | ||
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| bool hasVSADInsts() const { return HasVSADInsts; } | ||
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| bool hasVQSADInsts() const { return HasVQSADInsts; } | ||
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| bool hasVCVTNORMInsts() const { return HasVCVTNORMInsts; } | ||
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| bool hasVCVTPKNORMVOP2Insts() const { return HasVCVTPKNORMVOP2Insts; } | ||
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| bool hasVCVTPKNORMVOP3Insts() const { return HasVCVTPKNORMVOP3Insts; } | ||
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| bool hasFP8E5M3Insts() const { return HasFP8E5M3Insts; } | ||
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| bool hasPkFmacF16Inst() const { | ||
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@@ -616,15 +616,15 @@ let SubtargetPredicate = isGFX9Plus in { | |
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| let isReMaterializable = 1 in | ||
| defm V_SAT_PK_U8_I16 : VOP1Inst_t16<"v_sat_pk_u8_i16", VOP_I16_I32>; | ||
| } // End SubtargetPredicate = isGFX9Plus | ||
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| let mayRaiseFPException = 0, SubtargetPredicate = HasVCVTNORMInsts in { | ||
| defm V_CVT_NORM_I16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_norm_i16_f16", | ||
| VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>; | ||
| defm V_CVT_NORM_U16_F16 : VOP1Inst_t16_with_profiles <"v_cvt_norm_u16_f16", | ||
| VOP_I16_F16_SPECIAL_OMOD, VOP_I16_F16_SPECIAL_OMOD_t16, VOP_I16_F16_SPECIAL_OMOD_fake16>; | ||
| } // End mayRaiseFPException = 0, SubtargetPredicate = HasVCVTNORMInsts | ||
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| let SubtargetPredicate = isGFX9Only in { | ||
| defm V_SCREEN_PARTITION_4SE_B32 : VOP1Inst <"v_screen_partition_4se_b32", VOP_I32_I32>; | ||
| } // End SubtargetPredicate = isGFX9Only | ||
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@@ -971,7 +971,7 @@ defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_a | |
| } // End IsNeverUniform = 1 | ||
| defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, any_fldexp>; | ||
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| let ReadsModeReg = 0, mayRaiseFPException = 0, SubtargetPredicate = HasVCVTPKNORMVOP2Insts in { | ||
| defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_i16_f32>; | ||
| defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_V2I16_F32_F32, AMDGPUpknorm_u16_f32>; | ||
| } | ||
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@@ -185,7 +185,8 @@ defm V_FMA_LEGACY_F32 : VOP3Inst <"v_fma_legacy_f32", | |
| defm V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; | ||
| defm V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; | ||
| defm V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, any_fma>, VOPD_Component<0x13, "v_fma_f32">; | ||
| let SubtargetPredicate = HasVLERPInsts in | ||
| defm V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>; | ||
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| let SchedRW = [WriteIntMul] in { | ||
| let SubtargetPredicate = HasMadU32Inst in | ||
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@@ -258,12 +259,12 @@ defm V_DIV_FMAS_F64 : VOP3Inst <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC>; | |
| } // End isCommutable = 1 | ||
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| let isReMaterializable = 1 in { | ||
| let mayRaiseFPException = 0, SubtargetPredicate = HasVCUBEInsts in { | ||
| defm V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>; | ||
| defm V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>; | ||
| defm V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>; | ||
| defm V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>; | ||
| } // mayRaiseFPException = 0, SubtargetPredicate = HasVCUBEInsts | ||
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| defm V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>; | ||
| defm V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>; | ||
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@@ -306,12 +307,12 @@ let SubtargetPredicate = HasMinimum3Maximum3F32, ReadsModeReg = 0 in { | |
| defm V_MAXIMUM3_F32 : VOP3Inst <"v_maximum3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmaximum3>; | ||
| } // End SubtargetPredicate = isGFX12Plus, ReadsModeReg = 0 | ||
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| let isCommutable = 1, SubtargetPredicate = HasVSADInsts in { | ||
| defm V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; | ||
| defm V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; | ||
| defm V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; | ||
| defm V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>; | ||
| } // End isCommutable = 1, SubtargetPredicate = HasVSADInsts | ||
| defm V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>; | ||
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| defm V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", DIV_FIXUP_F32_PROF, AMDGPUdiv_fixup>; | ||
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@@ -424,7 +425,8 @@ def VOPProfileMQSAD : VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP> { | |
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| let SubtargetPredicate = isGFX7Plus in { | ||
| let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in { | ||
| let SubtargetPredicate = HasVQSADInsts in | ||
| defm V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>; | ||
| defm V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOPProfileMQSAD>; | ||
| } // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] | ||
| } // End SubtargetPredicate = isGFX7Plus | ||
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@@ -789,9 +791,6 @@ let isCommutable = 1 in { | |
| defm V_MAD_I32_I16 : VOP3Inst_t16 <"v_mad_i32_i16", VOP_I32_I16_I16_I32>; | ||
| } // End isCommutable = 1 | ||
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| defm V_PACK_B32_F16 : VOP3Inst_t16 <"v_pack_b32_f16", VOP_B32_F16_F16>; | ||
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| let isReMaterializable = 1 in { | ||
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@@ -996,6 +995,11 @@ def : GCNPat<(DivergentBinFrag<or> (or_oneuse i64:$src0, i64:$src1), i64:$src2), | |
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| } // End SubtargetPredicate = isGFX9Plus | ||
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| let SubtargetPredicate = HasVCVTPKNORMVOP3Insts in { | ||
| defm V_CVT_PKNORM_I16_F16 : VOP3Inst_t16 <"v_cvt_pknorm_i16_f16", VOP_B32_F16_F16>; | ||
| defm V_CVT_PKNORM_U16_F16 : VOP3Inst_t16 <"v_cvt_pknorm_u16_f16", VOP_B32_F16_F16>; | ||
| } // end SubtargetPredicate = HasVCVTPKNORMVOP3Insts | ||
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| // FIXME: Probably should hardcode clamp bit in pseudo and avoid this. | ||
| class OpSelBinOpClampPat<SDPatternOperator node, | ||
| Instruction inst> : GCNPat< | ||
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| Original file line number | Diff line number | Diff line change |
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| @@ -1,4 +1,3 @@ | ||
| ; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s | ||
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| declare i32 @llvm.amdgcn.lerp(i32, i32, i32) #0 | ||
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Doesn't follow feature naming scheme, no caps