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[AArch64] Combine vector FNEG+FMA into FNML[A|S] #167900

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[AArch64] Combine vector FNEG+FMA into FNML[A|S] #167900

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3c115a2
Combine vector FNEG+FMA into `FNML[A|S]`
dheaton-arm Nov 13, 2025
6a530d8
Address review comments
dheaton-arm Nov 18, 2025
ae2ba40
Use existing TableGen patterns
dheaton-arm Nov 24, 2025
9892c86
Remove SVE handling and add pattern to compensate
dheaton-arm Nov 24, 2025
2879d78
Use custom lowering rather than DAG Combiner
dheaton-arm Nov 25, 2025
dd43ed9
Address feedback
dheaton-arm Dec 1, 2025
89064ba
Remove redundant check prefixes
dheaton-arm Dec 1, 2025
0a9a6dd
Consolidate conversions to lambda and simplify early-exit condition
dheaton-arm Dec 2, 2025
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44 changes: 43 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1524,6 +1524,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,

for (auto VT : {MVT::v16i8, MVT::v8i8, MVT::v4i16, MVT::v2i32})
setOperationAction(ISD::GET_ACTIVE_LANE_MASK, VT, Custom);

for (auto VT : {MVT::v8f16, MVT::v4f32, MVT::v2f64})
setOperationAction(ISD::FMA, VT, Custom);
}

if (Subtarget->isSVEorStreamingSVEAvailable()) {
Expand Down Expand Up @@ -7730,6 +7733,45 @@ SDValue AArch64TargetLowering::LowerFMUL(SDValue Op, SelectionDAG &DAG) const {
return FCVTNT(VT, BottomBF16, Pg, TopF32);
}

SDValue AArch64TargetLowering::LowerFMA(SDValue Op, SelectionDAG &DAG) const {
SDValue OpA = Op->getOperand(0);
SDValue OpB = Op->getOperand(1);
SDValue OpC = Op->getOperand(2);
EVT VT = Op.getValueType();
SDLoc DL(Op);

// Bail early if we're definitely not looking to merge FNEGs into the FMA.
if (!VT.isFixedLengthVector() || OpC.getOpcode() != ISD::FNEG) {
if (VT.isScalableVector() || VT.getScalarType() == MVT::bf16 ||
useSVEForFixedLengthVectorVT(VT, !Subtarget->isNeonAvailable()))
return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);
return Op; // Fallback to NEON lowering.
}

// Convert FMA/FNEG nodes to SVE to enable the following patterns:
// fma(a, b, neg(c)) -> fnmls(a, b, c)
// fma(neg(a), b, neg(c)) -> fnmla(a, b, c)
// fma(a, neg(b), neg(c)) -> fnmla(a, b, c)
SDValue Pg = getPredicateForVector(DAG, DL, VT);
EVT ContainerVT = getContainerForFixedLengthVector(DAG, VT);

// Reuse `LowerToPredicatedOp` but drop the subsequent `extract_subvector`
OpA = OpA.getOpcode() == ISD::FNEG
? LowerToPredicatedOp(OpA, DAG, AArch64ISD::FNEG_MERGE_PASSTHRU)
->getOperand(0)
: convertToScalableVector(DAG, ContainerVT, OpA);
OpB = OpB.getOpcode() == ISD::FNEG
? LowerToPredicatedOp(OpB, DAG, AArch64ISD::FNEG_MERGE_PASSTHRU)
->getOperand(0)
: convertToScalableVector(DAG, ContainerVT, OpB);
OpC = LowerToPredicatedOp(OpC, DAG, AArch64ISD::FNEG_MERGE_PASSTHRU)
->getOperand(0);

SDValue ScalableRes =
DAG.getNode(AArch64ISD::FMA_PRED, DL, ContainerVT, Pg, OpA, OpB, OpC);
return convertFromScalableVector(DAG, VT, ScalableRes);
}

SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const {
LLVM_DEBUG(dbgs() << "Custom lowering: ");
Expand Down Expand Up @@ -7806,7 +7848,7 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
case ISD::FMUL:
return LowerFMUL(Op, DAG);
case ISD::FMA:
return LowerToPredicatedOp(Op, DAG, AArch64ISD::FMA_PRED);
return LowerFMA(Op, DAG);
case ISD::FDIV:
return LowerToPredicatedOp(Op, DAG, AArch64ISD::FDIV_PRED);
case ISD::FNEG:
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.h
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Expand Up @@ -615,6 +615,7 @@ class AArch64TargetLowering : public TargetLowering {
SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFMUL(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerFMA(SDValue Op, SelectionDAG &DAG) const;

SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
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Expand Up @@ -462,6 +462,7 @@ def AArch64fmlsidx : PatFrags<(ops node:$acc, node:$op1, node:$op2, node:$idx),
def AArch64fnmla_p : PatFrags<(ops node:$pg, node:$za, node:$zn, node:$zm),
[(int_aarch64_sve_fnmla_u node:$pg, node:$za, node:$zn, node:$zm),
(AArch64fma_p node:$pg, (AArch64fneg_mt node:$pg, node:$zn, (undef)), node:$zm, (AArch64fneg_mt node:$pg, node:$za, (undef))),
(AArch64fma_p node:$pg, node:$zn, (AArch64fneg_mt node:$pg, node:$zm, (undef)), (AArch64fneg_mt node:$pg, node:$za, (undef))),
(AArch64fneg_mt_nsz node:$pg, (AArch64fma_p node:$pg, node:$zn, node:$zm, node:$za), (undef))]>;

def AArch64fnmls_p : PatFrags<(ops node:$pg, node:$za, node:$zn, node:$zm),
Expand Down
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