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[PowerPC] cost modeling for length type VP intrinsic load/store #168938

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[PowerPC] cost modeling for length type VP intrinsic load/store #168938

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2fa5e1e
cost modeling for EVL vp.load/vp.store
RolandF77 Nov 20, 2025
fd8d758
Merge branch 'main' into ppcvpcost
RolandF77 Nov 20, 2025
5d98a9b
fix checks
RolandF77 Nov 21, 2025
5c7d0b1
formatting
RolandF77 Nov 21, 2025
000794a
address comments
RolandF77 Nov 28, 2025
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Merge branch 'main' into ppcvpcost
RolandF77 Nov 28, 2025
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62 changes: 62 additions & 0 deletions llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,10 @@ using namespace llvm;

#define DEBUG_TYPE "ppctti"

static cl::opt<bool> PPCEVL("ppc-evl",
cl::desc("Allow EVL type vp.load/vp.store"),
cl::init(false), cl::Hidden);

static cl::opt<bool> Pwr9EVL("ppc-pwr9-evl",
cl::desc("Allow vp.load and vp.store for pwr9"),
cl::init(false), cl::Hidden);
Expand Down Expand Up @@ -1078,3 +1082,61 @@ PPCTTIImpl::getVPLegalizationStrategy(const VPIntrinsic &PI) const {

return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
}

bool PPCTTIImpl::hasActiveVectorLength() const {
unsigned CPU = ST->getCPUDirective();
if (!PPCEVL)
return false;
if (CPU == PPC::DIR_PWR10 || CPU == PPC::DIR_PWR_FUTURE ||
(Pwr9EVL && CPU == PPC::DIR_PWR9))
return true;
return false;
Comment on lines +1090 to +1093
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@fhahn fhahn Nov 28, 2025

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This could just be

Suggested change
if (CPU == PPC::DIR_PWR10 || CPU == PPC::DIR_PWR_FUTURE ||
(Pwr9EVL && CPU == PPC::DIR_PWR9))
return true;
return false;
return CPU == PPC::DIR_PWR10 || CPU == PPC::DIR_PWR_FUTURE ||
(Pwr9EVL && CPU == PPC::DIR_PWR9);

This means vector predication intrinsics are supported? This would need some tests with vp intrinsics, which are different to masked ones used in the tests.

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@RolandF77 RolandF77 Dec 1, 2025

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We can only do EVL vp.load and vp.store. When I tried an example it didn't look like LV used the generic intrinsic path for those.

}

static inline bool isLegalLoadWithLengthType(EVT VT) {
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@diggerlin diggerlin Nov 27, 2025

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since the function is a simple static function and only used in the isLegalMaskedLoad , we can make the function as lamda function in the isLegalMaskedLoad

if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
return false;
return true;
}

bool PPCTTIImpl::isLegalMaskedLoad(Type *DataType, Align Alignment,
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@diggerlin diggerlin Nov 27, 2025

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it looks the function isLegalMaskedLoad has same logic and argument as isLegalMaskedStore, can we change the function name to isLegalMaskedLoadStore ?

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@RolandF77 RolandF77 Nov 27, 2025

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These are target hooks - methods defined in TargetTransformInfo in Analysis to give info to opt passes about target characteristics, which we override to provide PPC specific answers. We can't change the names.

unsigned AddressSpace) const {
if (!hasActiveVectorLength())
return false;
if (!isLegalLoadWithLengthType(TLI->getValueType(DL, DataType, true)))
return false;
return true;
}

bool PPCTTIImpl::isLegalMaskedStore(Type *DataType, Align Alignment,
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@diggerlin diggerlin Nov 27, 2025 •
edited
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I do not think the function isLegalMaskedStore used in the patch ?

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@RolandF77 RolandF77 Nov 27, 2025

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It is exposed to external users. It is conceptually used in the patch through getMaskedMemoryOpCost but since it is currently the same as for load I didn't differentiate. I guess I can make this clearer by calling both from there.

unsigned AddressSpace) const {
return isLegalMaskedLoad(DataType, Alignment, AddressSpace);
}

InstructionCost
PPCTTIImpl::getMaskedMemoryOpCost(const MemIntrinsicCostAttributes &MICA,
TTI::TargetCostKind CostKind) const {
Type *DataTy = MICA.getDataType();
Align Alignment = MICA.getAlignment();
unsigned Opcode = MICA.getID() == Intrinsic::masked_load ? Instruction::Load
: Instruction::Store;
unsigned AddressSpace = MICA.getAddressSpace();

InstructionCost BaseCost = BaseT::getMaskedMemoryOpCost(MICA, CostKind);

auto VecTy = dyn_cast<FixedVectorType>(DataTy);
if (!VecTy)
return BaseCost;
if (!isLegalMaskedLoad(VecTy->getScalarType(), Alignment, AddressSpace))
return BaseCost;
if (VecTy->getPrimitiveSizeInBits() > 128)
return BaseCost;

// Is scalar compare + select + maybe shift + vector load
InstructionCost Adj = vectorCostAdjustmentFactor(Opcode, DataTy, nullptr);
InstructionCost Cost = 2 + Adj;
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@diggerlin diggerlin Nov 27, 2025

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nit: change to
InstructionCost Cost = 2 + vectorCostAdjustmentFactor(Opcode, DataTy, nullptr);

and I am curiously what the 2 means for? is it possible to have comment for it ?

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@RolandF77 RolandF77 Nov 27, 2025

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That is what the above comment is supposed to be for. I can try to make it more clear.

if (ST->getCPUDirective() != PPC::DIR_PWR_FUTURE ||
VecTy->getScalarSizeInBits() != 8)
Cost += 1; // need shift
return Cost;
}
11 changes: 11 additions & 0 deletions llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
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Expand Up @@ -153,6 +153,17 @@ class PPCTTIImpl final : public BasicTTIImplBase<PPCTTIImpl> {
TargetTransformInfo::VPLegalization
getVPLegalizationStrategy(const VPIntrinsic &PI) const override;

bool hasActiveVectorLength() const override;

bool isLegalMaskedStore(Type *DataType, Align Alignment,
unsigned AddressSpace) const override;
bool isLegalMaskedLoad(Type *DataType, Align Alignment,
unsigned AddressSpace) const override;

InstructionCost
getMaskedMemoryOpCost(const MemIntrinsicCostAttributes &MICA,
TTI::TargetCostKind CostKind) const override;

private:
// The following constant is used for estimating costs on power9.
static const InstructionCost::CostType P9PipelineFlushEstimate = 80;
Expand Down
19 changes: 19 additions & 0 deletions llvm/test/Analysis/CostModel/PowerPC/ld-st-with-length.ll
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@@ -0,0 +1,19 @@
; RUN: opt < %s -mcpu=pwr9 -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s --check-prefix=P9
; RUN: opt < %s -mcpu=pwr10 -ppc-evl -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s --check-prefix=P10
; RUN: opt < %s -mcpu=future -ppc-evl -passes="print<cost-model>" 2>&1 -disable-output | FileCheck %s --check-prefix=FUTURE
target datalayout = "e-m:e-Fn32-i64:64-i128:128-n32:64-S128-v256:256:256-v512:512:512"
target triple = "powerpc64le-unknown-linux-gnu"

define void @bar(ptr %base, <2 x i8> %val) {
; P9: cost of 16 for {{.*}} @llvm.masked.load.v2i8.p0
; P10: cost of 4 for {{.*}} @llvm.masked.load.v2i8.p0
; FUTURE: cost of 3 for {{.*}} @llvm.masked.load.v2i8.p0
; P9: cost of 12 for {{.*}} @llvm.masked.store.v2i8.p0
; P10: cost of 4 for {{.*}} @llvm.masked.store.v2i8.p0
; FUTURE: cost of 3 for {{.*}} @llvm.masked.store.v2i8.p0
%x2 = call <2 x i8> @llvm.masked.load.v2i8.p0(ptr %base, i32 1, <2 x i1> <i1 1, i1 1>, <2 x i8> %val)

call void @llvm.masked.store.v2i8.p0(<2 x i8> %x2, ptr %base, i32 1, <2 x i1> <i1 1, i1 1>)
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@fhahn fhahn Nov 28, 2025

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I think you should cover at least all supported types + some unsupported ones


ret void
}