[LV][NFC] Remove remaining uses of undef in tests

llvm/test/Transforms/LoopVectorize/X86/pr39160.ll

@@ -1,75 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
 ; RUN: opt -passes=loop-vectorize -S < %s 2>&1 | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; Make sure that we can compile the test without crash.
-define void @barney(ptr %dst, i1 %arg) {
-
-; CHECK-LABEL: @barney(
-; CHECK:       middle.block:
-
-bb:
-  br label %bb2
-
-bb2:                                              ; preds = %bb2, %bb
-  %tmp4 = icmp slt i32 undef, 0
-  br i1 %tmp4, label %bb2, label %bb5
-
-bb5:                                              ; preds = %bb2
-  br label %bb19
-
-bb18:                                             ; preds = %bb33
-  ret void
-
-bb19:                                             ; preds = %bb36, %bb5
-  %tmp21 = phi i64 [ undef, %bb36 ], [ 2, %bb5 ]
-  %tmp22 = phi i32 [ %tmp65, %bb36 ], [ undef, %bb5 ]
-  br label %bb50
-
-bb33:                                             ; preds = %bb62
-  br i1 %arg, label %bb18, label %bb36
-
-bb36:                                             ; preds = %bb33
-  br label %bb19
-
-bb46:                                             ; preds = %bb50
-  br i1 %arg, label %bb48, label %bb59
-
-bb48:                                             ; preds = %bb46
-  %tmp49 = add i32 %tmp52, 14
-  ret void
-
-bb50:                                             ; preds = %bb50, %bb19
-  %tmp52 = phi i32 [ %tmp55, %bb50 ], [ %tmp22, %bb19 ]
-  %tmp53 = phi i64 [ %tmp56, %bb50 ], [ 1, %bb19 ]
-  %gep = getelementptr inbounds i8, ptr %dst, i64 %tmp53
-  store i8 1, ptr %gep
-  %tmp54 = add i32 %tmp52, 12
-  %tmp55 = add i32 %tmp52, 13
-  %tmp56 = add nuw nsw i64 %tmp53, 1
-  %tmp58 = icmp ult i64 %tmp53, undef
-  br i1 %tmp58, label %bb50, label %bb46
-
-bb59:                                             ; preds = %bb46
-  br label %bb62
-
-bb62:                                             ; preds = %bb68, %bb59
-  %tmp63 = phi i32 [ %tmp65, %bb68 ], [ %tmp55, %bb59 ]
-  %tmp64 = phi i64 [ %tmp66, %bb68 ], [ %tmp56, %bb59 ]
-  %tmp65 = add i32 %tmp63, 13
-  %tmp66 = add nuw nsw i64 %tmp64, 1
-  %tmp67 = icmp ult i64 %tmp66, %tmp21
-  br i1 %tmp67, label %bb68, label %bb33
-
-bb68:                                             ; preds = %bb62
-  br label %bb62
-}
 
 define i32 @foo(ptr addrspace(1) %p) {
-
-; CHECK-LABEL: foo
-; CHECK:       middle.block:
+; CHECK-LABEL: define i32 @foo(
+; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:    br label %[[OUTER:.*]]
+; CHECK:       [[OUTER]]:
+; CHECK-NEXT:    [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], %[[OUTER_LATCH:.*]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ 2, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[OUTER_LATCH]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 8
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    [[N_MOD_VF:%.*]] = urem i32 [[TMP0]], 8
+; CHECK-NEXT:    [[N_VEC:%.*]] = sub i32 [[TMP0]], [[N_MOD_VF]]
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 1, [[N_VEC]]
+; CHECK-NEXT:    [[TMP2:%.*]] = mul i32 [[N_VEC]], 2
+; CHECK-NEXT:    [[TMP3:%.*]] = add i32 6, [[TMP2]]
+; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
+; CHECK:       [[VECTOR_BODY]]:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 6, i32 8, i32 10, i32 12>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 8)
+; CHECK-NEXT:    [[TMP4]] = or <4 x i32> [[VEC_PHI]], [[VEC_IND]]
+; CHECK-NEXT:    [[TMP5]] = or <4 x i32> [[VEC_PHI1]], [[STEP_ADD]]
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
+; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 8)
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:       [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:    [[BIN_RDX:%.*]] = or <4 x i32> [[TMP5]], [[TMP4]]
+; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[BIN_RDX]])
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP0]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label %[[OUTER_LATCH]], label %[[SCALAR_PH]]
+; CHECK:       [[SCALAR_PH]]:
+; CHECK-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER]] ]
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ 1, %[[OUTER]] ]
+; CHECK-NEXT:    [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ 6, %[[OUTER]] ]
+; CHECK-NEXT:    br label %[[INNER:.*]]
+; CHECK:       [[INNER]]:
+; CHECK-NEXT:    [[TMP8:%.*]] = phi i32 [ [[TMP10:%.*]], %[[INNER]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ]
+; CHECK-NEXT:    [[A:%.*]] = phi i32 [ [[TMP11:%.*]], %[[INNER]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
+; CHECK-NEXT:    [[B:%.*]] = phi i32 [ [[TMP9:%.*]], %[[INNER]] ], [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ]
+; CHECK-NEXT:    [[TMP9]] = add i32 [[B]], 2
+; CHECK-NEXT:    [[TMP10]] = or i32 [[TMP8]], [[B]]
+; CHECK-NEXT:    [[TMP11]] = add nuw nsw i32 [[A]], 1
+; CHECK-NEXT:    [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
+; CHECK-NEXT:    [[TMP13:%.*]] = icmp ugt i64 [[IV]], [[TMP12]]
+; CHECK-NEXT:    br i1 [[TMP13]], label %[[INNER]], label %[[OUTER_LATCH]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK:       [[OUTER_LATCH]]:
+; CHECK-NEXT:    [[DOTLCSSA:%.*]] = phi i32 [ [[TMP10]], %[[INNER]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ]
+; CHECK-NEXT:    store atomic i32 [[DOTLCSSA]], ptr addrspace(1) [[P]] unordered, align 4
+; CHECK-NEXT:    [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
+; CHECK-NEXT:    [[TMP14:%.*]] = icmp ugt i64 [[IV]], 63
+; CHECK-NEXT:    [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
+; CHECK-NEXT:    br i1 [[TMP14]], label %[[EXIT:.*]], label %[[OUTER]]
+; CHECK:       [[EXIT]]:
+; CHECK-NEXT:    ret i32 0
+;
 
 entry:
   br label %outer

llvm/test/Transforms/LoopVectorize/if-conversion.ll

@@ -237,22 +237,36 @@ for.end:                                          ; preds = %for.inc, %entry
 ; Handle PHI with single incoming value having a full mask.
 ; PR34523
 
-; NOTE: Changing PHI inputs from undef to poison leads to change in
-; behaviour of the test. Left as undef for now.
-define void @PR34523() {
-; CHECK-LABEL: define void @PR34523() {
-; CHECK-NEXT:  [[BB1:.*:]]
-; CHECK-NEXT:    br i1 true, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
+define void @PR34523(ptr %p, i16 %val) {
+; CHECK-LABEL: define void @PR34523(
+; CHECK-SAME: ptr [[P:%.*]], i16 [[VAL:%.*]]) {
+; CHECK-NEXT:  [[BB1:.*]]:
+; CHECK-NEXT:    [[TMP0:%.*]] = add i16 [[VAL]], 1
+; CHECK-NEXT:    [[SMAX:%.*]] = call i16 @llvm.smax.i16(i16 [[TMP0]], i16 2)
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i16 [[VAL]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = add i16 [[SMAX]], [[TMP1]]
+; CHECK-NEXT:    [[TMP3:%.*]] = zext i16 [[TMP2]] to i32
+; CHECK-NEXT:    [[TMP4:%.*]] = add nuw nsw i32 [[TMP3]], 1
+; CHECK-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i16 [[TMP2]], 3
+; CHECK-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
 ; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    [[N_VEC:%.*]] = and i32 [[TMP4]], 131068
+; CHECK-NEXT:    [[DOTCAST:%.*]] = trunc i32 [[N_VEC]] to i16
+; CHECK-NEXT:    [[TMP5:%.*]] = add i16 [[VAL]], [[DOTCAST]]
 ; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
 ; CHECK:       [[VECTOR_BODY]]:
-; CHECK-NEXT:    br i1 poison, label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
 ; CHECK:       [[MIDDLE_BLOCK]]:
-; CHECK-NEXT:    br i1 poison, label %[[BB5:.*]], label %[[SCALAR_PH]]
+; CHECK-NEXT:    [[CMP_N:%.*]] = icmp eq i32 [[TMP4]], [[N_VEC]]
+; CHECK-NEXT:    br i1 [[CMP_N]], label %[[BB5:.*]], label %[[SCALAR_PH]]
 ; CHECK:       [[SCALAR_PH]]:
+; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i16 [ [[TMP5]], %[[MIDDLE_BLOCK]] ], [ [[VAL]], %[[BB1]] ]
 ; CHECK-NEXT:    br label %[[BB2:.*]]
 ; CHECK:       [[BB2]]:
-; CHECK-NEXT:    [[I:%.*]] = phi i16 [ undef, %[[SCALAR_PH]] ], [ [[_TMP2:%.*]], %[[BB4:.*]] ]
+; CHECK-NEXT:    [[I:%.*]] = phi i16 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[_TMP2:%.*]], %[[BB4:.*]] ]
 ; CHECK-NEXT:    br label %[[BB3:.*]]
 ; CHECK:       [[BB3]]:
 ; CHECK-NEXT:    br label %[[BB4]]
@@ -267,11 +281,11 @@ bb1:
   br label %bb2
 
 bb2:                                             ; preds = %bb4, %bb1
-  %i = phi i16 [ undef, %bb1 ], [ %_tmp2, %bb4 ]
+  %i = phi i16 [ %val, %bb1 ], [ %_tmp2, %bb4 ]
   br label %bb3
 
 bb3:                                             ; preds = %bb2
-  %_tmp1 = phi ptr [ undef, %bb2 ]
+  %_tmp1 = phi ptr [ %p, %bb2 ]
   br label %bb4
 
 bb4:                                             ; preds = %bb3

llvm/test/Transforms/LoopVectorize/incorrect-dom-info.ll

@@ -58,7 +58,7 @@ thread-pre-split.loopexit:                        ; preds = %11, %.thread-pre-sp
   br i1 %arg, label %11, label %22
 
 ; <label>:11                                      ; preds = %.lr.ph21
-  %12 = getelementptr inbounds [0 x i8], ptr @PL_utf8skip, i64 0, i64 undef
+  %12 = getelementptr inbounds [0 x i8], ptr @PL_utf8skip, i64 0, i64 0
   %13 = load i8, ptr %12, align 1
   %14 = zext i8 %13 to i64
   %15 = icmp ugt i64 %14, %10

llvm/test/Transforms/LoopVectorize/interleaved-accesses-uniform-load.ll

@@ -1,4 +1,6 @@
-; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true < %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -S -passes=loop-vectorize -force-vector-width=4 -force-vector-interleave=1 \
+; RUN:   -enable-interleaved-mem-accesses=true < %s | FileCheck %s
 
 ; Make sure the vectorizer can handle this loop: The strided load is only used
 ; by the loop's exit condition, which is not vectorized, and is therefore
@@ -29,10 +31,31 @@
 %0 zeroinitializer], align 8
 
 define dso_local void @test_dead_load(i32 %arg) {
-; CHECK-LABEL: @test_dead_load(
-; CHECK: vector.body:
-; CHECK: %wide.vec = load <16 x i32>, ptr %3, align 8
-; CHECK: %strided.vec = shufflevector <16 x i32> %wide.vec, <16 x i32> undef, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+; CHECK-LABEL: define dso_local void @test_dead_load(
+; CHECK-SAME: i32 [[ARG:%.*]]) {
+; CHECK-NEXT:  [[BB1:.*:]]
+; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
+; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
+; CHECK:       [[VECTOR_BODY]]:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP0:%.*]] = icmp eq i64 [[INDEX_NEXT]], 52
+; CHECK-NEXT:    br i1 [[TMP0]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK:       [[MIDDLE_BLOCK]]:
+; CHECK-NEXT:    br label %[[SCALAR_PH:.*]]
+; CHECK:       [[SCALAR_PH]]:
+; CHECK-NEXT:    br label %[[BB2:.*]]
+; CHECK:       [[BB2]]:
+; CHECK-NEXT:    [[TMP:%.*]] = phi ptr [ [[TMP6:%.*]], %[[BB2]] ], [ getelementptr (i8, ptr @[[GLOB0:[0-9]+]], i64 832), %[[SCALAR_PH]] ]
+; CHECK-NEXT:    [[TMP3:%.*]] = getelementptr inbounds [[TMP0]], ptr [[TMP]], i64 0, i32 1
+; CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 8
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 258
+; CHECK-NEXT:    [[TMP6]] = getelementptr inbounds [[TMP0]], ptr [[TMP]], i64 1
+; CHECK-NEXT:    br i1 [[TMP5]], label %[[BB65:.*]], label %[[BB2]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK:       [[BB65]]:
+; CHECK-NEXT:    unreachable
+;
 bb1:
   br label %bb2
 

llvm/test/Transforms/LoopVectorize/iv_outside_user.ll

@@ -262,15 +262,16 @@ for.end:
   ret i32 %phi
 }
 
-define void @PR30742() {
-; CHECK-LABEL: define void @PR30742() {
+define void @PR30742(ptr %p) {
+; CHECK-LABEL: define void @PR30742(
+; CHECK-SAME: ptr [[P:%.*]]) {
 ; CHECK-NEXT:  [[BB0:.*:]]
 ; CHECK-NEXT:    br label %[[BB1:.*]]
 ; CHECK:       [[BB1_LOOPEXIT:.*]]:
 ; CHECK-NEXT:    br label %[[BB1]]
 ; CHECK:       [[BB1]]:
-; CHECK-NEXT:    [[TMP00:%.*]] = load i32, ptr undef, align 16
-; CHECK-NEXT:    [[TMP01:%.*]] = sub i32 [[TMP00]], undef
+; CHECK-NEXT:    [[TMP00:%.*]] = load i32, ptr [[P]], align 16
+; CHECK-NEXT:    [[TMP01:%.*]] = sub i32 [[TMP00]], 3
 ; CHECK-NEXT:    [[TMP02:%.*]] = icmp slt i32 [[TMP01]], 1
 ; CHECK-NEXT:    [[TMP03:%.*]] = select i1 [[TMP02]], i32 1, i32 [[TMP01]]
 ; CHECK-NEXT:    [[TMP04:%.*]] = add nsw i32 [[TMP03]], -7
@@ -307,7 +308,7 @@ define void @PR30742() {
 ; CHECK-NEXT:    br i1 [[TMP07]], label %[[BB2]], label %[[BB3]], {{!llvm.loop ![0-9]+}}
 ; CHECK:       [[BB3]]:
 ; CHECK-NEXT:    [[TMP08:%.*]] = phi i32 [ [[TMP05]], %[[BB2]] ], [ [[IND_ESCAPE]], %[[MIDDLE_BLOCK10]] ]
-; CHECK-NEXT:    [[TMP09:%.*]] = sub i32 [[TMP00]], undef
+; CHECK-NEXT:    [[TMP09:%.*]] = sub i32 [[TMP00]], 4
 ; CHECK-NEXT:    [[TMP10:%.*]] = icmp slt i32 [[TMP09]], 1
 ; CHECK-NEXT:    [[TMP11:%.*]] = select i1 [[TMP10]], i32 1, i32 [[TMP09]]
 ; CHECK-NEXT:    [[TMP12:%.*]] = add nsw i32 [[TMP11]], -7
@@ -346,8 +347,8 @@ BB0:
   br label %BB1
 
 BB1:
-  %tmp00 = load i32, ptr undef, align 16
-  %tmp01 = sub i32 %tmp00, undef
+  %tmp00 = load i32, ptr %p, align 16
+  %tmp01 = sub i32 %tmp00, 3
   %tmp02 = icmp slt i32 %tmp01, 1
   %tmp03 = select i1 %tmp02, i32 1, i32 %tmp01
   %tmp04 = add nsw i32 %tmp03, -7
@@ -361,7 +362,7 @@ BB2:
 
 BB3:
   %tmp08 = phi i32 [ %tmp05, %BB2 ]
-  %tmp09 = sub i32 %tmp00, undef
+  %tmp09 = sub i32 %tmp00, 4
   %tmp10 = icmp slt i32 %tmp09, 1
   %tmp11 = select i1 %tmp10, i32 1, i32 %tmp09
   %tmp11.inc = add nsw i32 %tmp11, -7