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Fixes simple issue found static analyzer #169958

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Fixes simple issue found static analyzer #169958

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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1373,7 +1373,7 @@ void GISelValueTracking::computeKnownFPClass(Register R,
(KnownLHS.isKnownNeverInfinity() || KnownRHS.isKnownNeverInfinity()))
Known.knownNot(fcNan);

if (Opcode == Instruction::FAdd) {
if (Opcode == TargetOpcode::G_FADD) {
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@arsenm arsenm Nov 30, 2025

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Clearly there is missing test coverage

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@Seraphimt Seraphimt Dec 1, 2025

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I added all in one PR because fixs is minor(typo and missprint) and it's a bit cluttered creating 10 separate of these.
I'll try add tests for G_FADD and rest.

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@arsenm arsenm Dec 2, 2025

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At minimum should separate the ones that have functional changes from one that do not

if (KnownLHS.cannotBeOrderedLessThanZero() &&
KnownRHS.cannotBeOrderedLessThanZero())
Known.knownNot(KnownFPClass::OrderedLessThanZeroMask);
Expand Down Expand Up @@ -1488,7 +1488,7 @@ void GISelValueTracking::computeKnownFPClass(Register R,
KnownLHS, Depth + 1);
}

if (Opcode == Instruction::FDiv) {
if (Opcode == TargetOpcode::G_FDIV) {
// Only 0/0, Inf/Inf produce NaN.
if (KnownLHS.isKnownNeverNaN() && KnownRHS.isKnownNeverNaN() &&
(KnownLHS.isKnownNeverInfinity() ||
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3 changes: 1 addition & 2 deletions llvm/lib/CodeGen/MachineFunction.cpp
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Expand Up @@ -1439,8 +1439,7 @@ void MachineJumpTableInfo::print(raw_ostream &OS) const {
OS << printJumpTableEntryReference(i) << ':';
for (const MachineBasicBlock *MBB : JumpTables[i].MBBs)
OS << ' ' << printMBBReference(*MBB);
if (i != e)
OS << '\n';
OS << '\n';
}

OS << '\n';
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5 changes: 0 additions & 5 deletions llvm/lib/CodeGen/MachineInstr.cpp
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Expand Up @@ -2011,39 +2011,34 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
// operands.
if (MCSymbol *PreInstrSymbol = getPreInstrSymbol()) {
if (!FirstOp) {
FirstOp = false;
OS << ',';
}
OS << " pre-instr-symbol ";
MachineOperand::printSymbol(OS, *PreInstrSymbol);
}
if (MCSymbol *PostInstrSymbol = getPostInstrSymbol()) {
if (!FirstOp) {
FirstOp = false;
OS << ',';
}
OS << " post-instr-symbol ";
MachineOperand::printSymbol(OS, *PostInstrSymbol);
}
if (MDNode *HeapAllocMarker = getHeapAllocMarker()) {
if (!FirstOp) {
FirstOp = false;
OS << ',';
}
OS << " heap-alloc-marker ";
HeapAllocMarker->printAsOperand(OS, MST);
}
if (MDNode *PCSections = getPCSections()) {
if (!FirstOp) {
FirstOp = false;
OS << ',';
}
OS << " pcsections ";
PCSections->printAsOperand(OS, MST);
}
if (MDNode *MMRA = getMMRAMetadata()) {
if (!FirstOp) {
FirstOp = false;
OS << ',';
}
OS << " mmra ";
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7 changes: 3 additions & 4 deletions llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp
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Expand Up @@ -395,10 +395,9 @@ LVScope *LVDWARFReader::processOneDie(const DWARFDie &InputDIE, LVScope *Parent,
if (abbrCode) {
if (const DWARFAbbreviationDeclaration *AbbrevDecl =
TheDIE.getAbbreviationDeclarationPtr())
if (AbbrevDecl)
for (const DWARFAbbreviationDeclaration::AttributeSpec &AttrSpec :
AbbrevDecl->attributes())
processOneAttribute(TheDIE, &CurrentEndOffset, AttrSpec);
for (const DWARFAbbreviationDeclaration::AttributeSpec &AttrSpec :
AbbrevDecl->attributes())
processOneAttribute(TheDIE, &CurrentEndOffset, AttrSpec);
}
};

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
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Expand Up @@ -5732,7 +5732,7 @@ void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
AArch64::FPR8RegClass.contains(SrcReg)) {
if (Subtarget.hasZeroCycleRegMoveFPR128() &&
!Subtarget.hasZeroCycleRegMoveFPR64() &&
!Subtarget.hasZeroCycleRegMoveFPR64() && Subtarget.isNeonAvailable()) {
!Subtarget.hasZeroCycleRegMoveFPR32() && Subtarget.isNeonAvailable()) {
MCRegister DestRegQ = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
&AArch64::FPR128RegClass);
MCRegister SrcRegQ = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
Expand Down
5 changes: 1 addition & 4 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
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Expand Up @@ -416,7 +416,7 @@ bool PPCInstrInfo::getFMAPatterns(MachineInstr &Root,

// If this is not Leaf FMA Instr, its 'add' operand should only have one use
// as this fma will be changed later.
return IsLeaf ? true : MRI->hasOneNonDBGUse(OpAdd.getReg());
return MRI->hasOneNonDBGUse(OpAdd.getReg());
};

int16_t AddOpIdx = -1;
Expand Down Expand Up @@ -5809,9 +5809,6 @@ bool PPCInstrInfo::getMemOperandWithOffsetWidth(
if (!LdSt.getOperand(1).isImm() ||
(!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()))
return false;
if (!LdSt.getOperand(1).isImm() ||
(!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()))
return false;

if (!LdSt.hasOneMemOperand())
return false;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp
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Expand Up @@ -694,7 +694,7 @@ class VEOperand : public MCParsedAsmOperand {
if (!ConstExpr)
return false;
unsigned regIdx = ConstExpr->getValue();
if (regIdx > 31 || MISCRegs[regIdx] == VE::NoRegister)
if (regIdx >= std::size(MISCRegs) || MISCRegs[regIdx] == VE::NoRegister)
return false;
Op.Kind = k_Register;
Op.Reg.Reg = MISCRegs[regIdx];
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/TargetParser/Host.cpp
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Expand Up @@ -2195,9 +2195,9 @@ StringMap<bool> sys::getHostCPUFeatures() {
bool HasLeaf24 =
MaxLevel >= 0x24 && !getX86CpuIDAndInfo(0x24, &EAX, &EBX, &ECX, &EDX);

int AVX10Ver = HasLeaf24 && (EBX & 0xff);
Features["avx10.1"] = HasAVX10 && AVX10Ver >= 1;
Features["avx10.2"] = HasAVX10 && AVX10Ver >= 2;
int AVX10Ver = EBX & 0xff;
Features["avx10.1"] = HasAVX10 && HasLeaf24 && AVX10Ver >= 1;
Features["avx10.2"] = HasAVX10 && HasLeaf24 && AVX10Ver >= 2;

return Features;
}
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18 changes: 8 additions & 10 deletions llvm/lib/Transforms/Utils/SimplifyCFG.cpp
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Expand Up @@ -1909,17 +1909,15 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(Instruction *TI,
});
if (!AllSame)
return false;
if (AllSame) {
LockstepReverseIterator<true> LRI(Succs);
while (LRI.isValid()) {
Instruction *I0 = (*LRI)[0];
if (any_of(*LRI, [I0](Instruction *I) {
return !areIdenticalUpToCommutativity(I0, I);
})) {
return false;
}
--LRI;
LockstepReverseIterator<true> LRI(Succs);
while (LRI.isValid()) {
Instruction *I0 = (*LRI)[0];
if (any_of(*LRI, [I0](Instruction *I) {
return !areIdenticalUpToCommutativity(I0, I);
})) {
return false;
}
--LRI;
}
// Now we know that all instructions in all successors can be hoisted. Let
// the loop below handle the hoisting.
Expand Down