diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 8dc40a665bd9a..780891152845b 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -1293,25 +1293,25 @@ defm SVRSQRTE : SInstZPZ<"svrsqrte", "Ui", "aarch64_sve_ursqrte">; //------------------------------------------------------------------------------ -multiclass SInstZPZxZ flags=[]> { - def _M : SInst; - def _X : SInst; - def _Z : SInst; +multiclass SInstZPZxZ flags=[]> { + def _M : SInst; + def _X : SInst; + def _Z : SInst; - def _N_M : SInst; - def _N_X : SInst; - def _N_Z : SInst; + def _N_M : SInst; + def _N_X : SInst; + def _N_Z : SInst; } let SVETargetGuard = "sve2|sme" in { -defm SVQRSHL_S : SInstZPZxZ<"svqrshl", "csil", "dPdx", "dPdK", "aarch64_sve_sqrshl", [VerifyRuntimeMode]>; -defm SVQRSHL_U : SInstZPZxZ<"svqrshl", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_uqrshl", [VerifyRuntimeMode]>; -defm SVQSHL_S : SInstZPZxZ<"svqshl", "csil", "dPdx", "dPdK", "aarch64_sve_sqshl", [VerifyRuntimeMode]>; -defm SVQSHL_U : SInstZPZxZ<"svqshl", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_uqshl", [VerifyRuntimeMode]>; -defm SVRSHL_S : SInstZPZxZ<"svrshl", "csil", "dPdx", "dPdK", "aarch64_sve_srshl", [VerifyRuntimeMode]>; -defm SVRSHL_U : SInstZPZxZ<"svrshl", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_urshl", [VerifyRuntimeMode]>; -defm SVSQADD : SInstZPZxZ<"svsqadd", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_usqadd", [VerifyRuntimeMode]>; -defm SVUQADD : SInstZPZxZ<"svuqadd", "csil", "dPdu", "dPdL", "aarch64_sve_suqadd", [VerifyRuntimeMode]>; +defm SVQRSHL_S : SInstZPZxZ<"svqrshl", "csil", "dPdx", "dPdK", "aarch64_sve_sqrshl", "aarch64_sve_sqrshl_u", [VerifyRuntimeMode]>; +defm SVQRSHL_U : SInstZPZxZ<"svqrshl", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_uqrshl", "aarch64_sve_uqrshl_u", [VerifyRuntimeMode]>; +defm SVQSHL_S : SInstZPZxZ<"svqshl", "csil", "dPdx", "dPdK", "aarch64_sve_sqshl", "aarch64_sve_sqshl_u", [VerifyRuntimeMode]>; +defm SVQSHL_U : SInstZPZxZ<"svqshl", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_uqshl", "aarch64_sve_uqshl_u", [VerifyRuntimeMode]>; +defm SVRSHL_S : SInstZPZxZ<"svrshl", "csil", "dPdx", "dPdK", "aarch64_sve_srshl", "aarch64_sve_srshl_u", [VerifyRuntimeMode]>; +defm SVRSHL_U : SInstZPZxZ<"svrshl", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_urshl", "aarch64_sve_urshl_u", [VerifyRuntimeMode]>; +defm SVSQADD : SInstZPZxZ<"svsqadd", "UcUsUiUl", "dPdx", "dPdK", "aarch64_sve_usqadd", "aarch64_sve_usqadd", [VerifyRuntimeMode]>; +defm SVUQADD : SInstZPZxZ<"svuqadd", "csil", "dPdu", "dPdL", "aarch64_sve_suqadd", "aarch64_sve_suqadd", [VerifyRuntimeMode]>; def SVABA_S : SInst<"svaba[_{d}]", "dddd", "csil" , MergeNone, "aarch64_sve_saba", [VerifyRuntimeMode]>; def SVABA_U : SInst<"svaba[_{d}]", "dddd", "UcUsUiUl", MergeNone, "aarch64_sve_uaba", [VerifyRuntimeMode]>; diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qrshl.c b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qrshl.c index cb1793d98418a..5b47497286847 100644 --- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qrshl.c +++ b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qrshl.c @@ -297,12 +297,12 @@ svuint64_t test_svqrshl_u64_m(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-LABEL: @test_svqrshl_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svqrshl_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svqrshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -313,13 +313,13 @@ svint8_t test_svqrshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-LABEL: @test_svqrshl_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svqrshl_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svqrshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -330,13 +330,13 @@ svint16_t test_svqrshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-LABEL: @test_svqrshl_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svqrshl_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svqrshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -347,13 +347,13 @@ svint32_t test_svqrshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-LABEL: @test_svqrshl_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svqrshl_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svqrshl_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -363,12 +363,12 @@ svint64_t test_svqrshl_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-LABEL: @test_svqrshl_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z17test_svqrshl_u8_xu10__SVBool_tu11__SVUint8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svqrshl_u8_x(svbool_t pg, svuint8_t op1, svint8_t op2) @@ -379,13 +379,13 @@ svuint8_t test_svqrshl_u8_x(svbool_t pg, svuint8_t op1, svint8_t op2) // CHECK-LABEL: @test_svqrshl_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svqrshl_u16_xu10__SVBool_tu12__SVUint16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svqrshl_u16_x(svbool_t pg, svuint16_t op1, svint16_t op2) @@ -396,13 +396,13 @@ svuint16_t test_svqrshl_u16_x(svbool_t pg, svuint16_t op1, svint16_t op2) // CHECK-LABEL: @test_svqrshl_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svqrshl_u32_xu10__SVBool_tu12__SVUint32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svqrshl_u32_x(svbool_t pg, svuint32_t op1, svint32_t op2) @@ -413,13 +413,13 @@ svuint32_t test_svqrshl_u32_x(svbool_t pg, svuint32_t op1, svint32_t op2) // CHECK-LABEL: @test_svqrshl_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z18test_svqrshl_u64_xu10__SVBool_tu12__SVUint64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svqrshl_u64_x(svbool_t pg, svuint64_t op1, svint64_t op2) @@ -775,14 +775,14 @@ svuint64_t test_svqrshl_n_u64_m(svbool_t pg, svuint64_t op1, int64_t op2) // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z19test_svqrshl_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svqrshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -795,7 +795,7 @@ svint8_t test_svqrshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z20test_svqrshl_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -803,7 +803,7 @@ svint8_t test_svqrshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svqrshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -816,7 +816,7 @@ svint16_t test_svqrshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z20test_svqrshl_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -824,7 +824,7 @@ svint16_t test_svqrshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svqrshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -837,7 +837,7 @@ svint32_t test_svqrshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z20test_svqrshl_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -845,7 +845,7 @@ svint32_t test_svqrshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svqrshl_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -857,14 +857,14 @@ svint64_t test_svqrshl_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z19test_svqrshl_n_u8_xu10__SVBool_tu11__SVUint8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svqrshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) @@ -877,7 +877,7 @@ svuint8_t test_svqrshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z20test_svqrshl_n_u16_xu10__SVBool_tu12__SVUint16_ts( @@ -885,7 +885,7 @@ svuint8_t test_svqrshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svqrshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) @@ -898,7 +898,7 @@ svuint16_t test_svqrshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z20test_svqrshl_n_u32_xu10__SVBool_tu12__SVUint32_ti( @@ -906,7 +906,7 @@ svuint16_t test_svqrshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svqrshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) @@ -919,7 +919,7 @@ svuint32_t test_svqrshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z20test_svqrshl_n_u64_xu10__SVBool_tu12__SVUint64_tl( @@ -927,7 +927,7 @@ svuint32_t test_svqrshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svqrshl_n_u64_x(svbool_t pg, svuint64_t op1, int64_t op2) diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qshl.c b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qshl.c index 4faef0234f037..8dc83b5247924 100644 --- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qshl.c +++ b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_qshl.c @@ -297,12 +297,12 @@ svuint64_t test_svqshl_u64_m(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-LABEL: @test_svqshl_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z16test_svqshl_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svqshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -313,13 +313,13 @@ svint8_t test_svqshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-LABEL: @test_svqshl_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svqshl_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svqshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -330,13 +330,13 @@ svint16_t test_svqshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-LABEL: @test_svqshl_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svqshl_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svqshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -347,13 +347,13 @@ svint32_t test_svqshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-LABEL: @test_svqshl_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svqshl_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svqshl_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -363,12 +363,12 @@ svint64_t test_svqshl_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-LABEL: @test_svqshl_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z16test_svqshl_u8_xu10__SVBool_tu11__SVUint8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svqshl_u8_x(svbool_t pg, svuint8_t op1, svint8_t op2) @@ -379,13 +379,13 @@ svuint8_t test_svqshl_u8_x(svbool_t pg, svuint8_t op1, svint8_t op2) // CHECK-LABEL: @test_svqshl_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svqshl_u16_xu10__SVBool_tu12__SVUint16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svqshl_u16_x(svbool_t pg, svuint16_t op1, svint16_t op2) @@ -396,13 +396,13 @@ svuint16_t test_svqshl_u16_x(svbool_t pg, svuint16_t op1, svint16_t op2) // CHECK-LABEL: @test_svqshl_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svqshl_u32_xu10__SVBool_tu12__SVUint32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svqshl_u32_x(svbool_t pg, svuint32_t op1, svint32_t op2) @@ -413,13 +413,13 @@ svuint32_t test_svqshl_u32_x(svbool_t pg, svuint32_t op1, svint32_t op2) // CHECK-LABEL: @test_svqshl_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svqshl_u64_xu10__SVBool_tu12__SVUint64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svqshl_u64_x(svbool_t pg, svuint64_t op1, svint64_t op2) @@ -775,14 +775,14 @@ svuint64_t test_svqshl_n_u64_m(svbool_t pg, svuint64_t op1, int64_t op2) // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z18test_svqshl_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svqshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -795,7 +795,7 @@ svint8_t test_svqshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svqshl_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -803,7 +803,7 @@ svint8_t test_svqshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svqshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -816,7 +816,7 @@ svint16_t test_svqshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svqshl_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -824,7 +824,7 @@ svint16_t test_svqshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svqshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -837,7 +837,7 @@ svint32_t test_svqshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svqshl_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -845,7 +845,7 @@ svint32_t test_svqshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svqshl_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -857,14 +857,14 @@ svint64_t test_svqshl_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z18test_svqshl_n_u8_xu10__SVBool_tu11__SVUint8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svqshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) @@ -877,7 +877,7 @@ svuint8_t test_svqshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svqshl_n_u16_xu10__SVBool_tu12__SVUint16_ts( @@ -885,7 +885,7 @@ svuint8_t test_svqshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svqshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) @@ -898,7 +898,7 @@ svuint16_t test_svqshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svqshl_n_u32_xu10__SVBool_tu12__SVUint32_ti( @@ -906,7 +906,7 @@ svuint16_t test_svqshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svqshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) @@ -919,7 +919,7 @@ svuint32_t test_svqshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svqshl_n_u64_xu10__SVBool_tu12__SVUint64_tl( @@ -927,7 +927,7 @@ svuint32_t test_svqshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svqshl_n_u64_x(svbool_t pg, svuint64_t op1, int64_t op2) diff --git a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_rshl.c b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_rshl.c index 9891b80460aff..dc03a20850672 100644 --- a/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_rshl.c +++ b/clang/test/CodeGen/AArch64/sve2-intrinsics/acle_sve2_rshl.c @@ -297,12 +297,12 @@ svuint64_t test_svrshl_u64_m(svbool_t pg, svuint64_t op1, svint64_t op2) // CHECK-LABEL: @test_svrshl_s8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z16test_svrshl_s8_xu10__SVBool_tu10__SVInt8_tS0_( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svrshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) @@ -313,13 +313,13 @@ svint8_t test_svrshl_s8_x(svbool_t pg, svint8_t op1, svint8_t op2) // CHECK-LABEL: @test_svrshl_s16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svrshl_s16_xu10__SVBool_tu11__SVInt16_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svrshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) @@ -330,13 +330,13 @@ svint16_t test_svrshl_s16_x(svbool_t pg, svint16_t op1, svint16_t op2) // CHECK-LABEL: @test_svrshl_s32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svrshl_s32_xu10__SVBool_tu11__SVInt32_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svrshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) @@ -347,13 +347,13 @@ svint32_t test_svrshl_s32_x(svbool_t pg, svint32_t op1, svint32_t op2) // CHECK-LABEL: @test_svrshl_s64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svrshl_s64_xu10__SVBool_tu11__SVInt64_tS0_( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svrshl_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) @@ -363,12 +363,12 @@ svint64_t test_svrshl_s64_x(svbool_t pg, svint64_t op1, svint64_t op2) // CHECK-LABEL: @test_svrshl_u8_x( // CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z16test_svrshl_u8_xu10__SVBool_tu11__SVUint8_tu10__SVInt8_t( // CPP-CHECK-NEXT: entry: -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svrshl_u8_x(svbool_t pg, svuint8_t op1, svint8_t op2) @@ -379,13 +379,13 @@ svuint8_t test_svrshl_u8_x(svbool_t pg, svuint8_t op1, svint8_t op2) // CHECK-LABEL: @test_svrshl_u16_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svrshl_u16_xu10__SVBool_tu12__SVUint16_tu11__SVInt16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svrshl_u16_x(svbool_t pg, svuint16_t op1, svint16_t op2) @@ -396,13 +396,13 @@ svuint16_t test_svrshl_u16_x(svbool_t pg, svuint16_t op1, svint16_t op2) // CHECK-LABEL: @test_svrshl_u32_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svrshl_u32_xu10__SVBool_tu12__SVUint32_tu11__SVInt32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svrshl_u32_x(svbool_t pg, svuint32_t op1, svint32_t op2) @@ -413,13 +413,13 @@ svuint32_t test_svrshl_u32_x(svbool_t pg, svuint32_t op1, svint32_t op2) // CHECK-LABEL: @test_svrshl_u64_x( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z17test_svrshl_u64_xu10__SVBool_tu12__SVUint64_tu11__SVInt64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[OP2:%.*]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svrshl_u64_x(svbool_t pg, svuint64_t op1, svint64_t op2) @@ -775,14 +775,14 @@ svuint64_t test_svrshl_n_u64_m(svbool_t pg, svuint64_t op1, int64_t op2) // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z18test_svrshl_n_s8_xu10__SVBool_tu10__SVInt8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svint8_t test_svrshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) @@ -795,7 +795,7 @@ svint8_t test_svrshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svrshl_n_s16_xu10__SVBool_tu11__SVInt16_ts( @@ -803,7 +803,7 @@ svint8_t test_svrshl_n_s8_x(svbool_t pg, svint8_t op1, int8_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint16_t test_svrshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) @@ -816,7 +816,7 @@ svint16_t test_svrshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svrshl_n_s32_xu10__SVBool_tu11__SVInt32_ti( @@ -824,7 +824,7 @@ svint16_t test_svrshl_n_s16_x(svbool_t pg, svint16_t op1, int16_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint32_t test_svrshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) @@ -837,7 +837,7 @@ svint32_t test_svrshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svrshl_n_s64_xu10__SVBool_tu11__SVInt64_tl( @@ -845,7 +845,7 @@ svint32_t test_svrshl_n_s32_x(svbool_t pg, svint32_t op1, int32_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svint64_t test_svrshl_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) @@ -857,14 +857,14 @@ svint64_t test_svrshl_n_s64_x(svbool_t pg, svint64_t op1, int64_t op2) // CHECK-NEXT: entry: // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP0]] // // CPP-CHECK-LABEL: @_Z18test_svrshl_n_u8_xu10__SVBool_tu11__SVUint8_ta( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i8 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv16i8( [[PG:%.*]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP0]] // svuint8_t test_svrshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) @@ -877,7 +877,7 @@ svuint8_t test_svrshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svrshl_n_u16_xu10__SVBool_tu12__SVUint16_ts( @@ -885,7 +885,7 @@ svuint8_t test_svrshl_n_u8_x(svbool_t pg, svuint8_t op1, int8_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i16 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv8i16( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint16_t test_svrshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) @@ -898,7 +898,7 @@ svuint16_t test_svrshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svrshl_n_u32_xu10__SVBool_tu12__SVUint32_ti( @@ -906,7 +906,7 @@ svuint16_t test_svrshl_n_u16_x(svbool_t pg, svuint16_t op1, int16_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i32 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv4i32( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint32_t test_svrshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) @@ -919,7 +919,7 @@ svuint32_t test_svrshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CHECK-NEXT: ret [[TMP1]] // // CPP-CHECK-LABEL: @_Z19test_svrshl_n_u64_xu10__SVBool_tu12__SVUint64_tl( @@ -927,7 +927,7 @@ svuint32_t test_svrshl_n_u32_x(svbool_t pg, svuint32_t op1, int32_t op2) // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) // CPP-CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement poison, i64 [[OP2:%.*]], i64 0 // CPP-CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector [[DOTSPLATINSERT]], poison, zeroinitializer -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv2i64( [[TMP0]], [[OP1:%.*]], [[DOTSPLAT]]) // CPP-CHECK-NEXT: ret [[TMP1]] // svuint64_t test_svrshl_n_u64_x(svbool_t pg, svuint64_t op1, int64_t op2) diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index 1c86c6815f049..272e800dfc94c 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -2449,7 +2449,9 @@ def int_aarch64_sve_sqrdmlsh_lane : AdvSIMD_3VectorArgIndexed_Intrinsic<[IntrSpe def int_aarch64_sve_sqrdmulh : AdvSIMD_2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sqrdmulh_lane : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sqrshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; +def int_aarch64_sve_sqrshl_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sqshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; +def int_aarch64_sve_sqshl_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sqshlu : AdvSIMD_SVE_ShiftByImm_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sqsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sqsub_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; @@ -2457,6 +2459,7 @@ def int_aarch64_sve_sqsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpecul def int_aarch64_sve_srhadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_sri : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_srshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; +def int_aarch64_sve_srshl_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_srshr : AdvSIMD_SVE_ShiftByImm_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_srsra : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_ssra : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>; @@ -2467,13 +2470,16 @@ def int_aarch64_sve_uhsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpecul def int_aarch64_sve_uhsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_uqadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_uqrshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; +def int_aarch64_sve_uqrshl_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_uqshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; +def int_aarch64_sve_uqshl_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_uqsub : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_uqsub_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_uqsubr : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_urecpe : AdvSIMD_Merged1VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_urhadd : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_urshl : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; +def int_aarch64_sve_urshl_u : AdvSIMD_Pred2VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_urshr : AdvSIMD_SVE_ShiftByImm_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_ursqrte : AdvSIMD_Merged1VectorArg_Intrinsic<[IntrSpeculatable]>; def int_aarch64_sve_ursra : AdvSIMD_2VectorArgIndexed_Intrinsic<[IntrSpeculatable]>; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index e99b3f8ff07e0..a5cb149af6d34 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3885,12 +3885,12 @@ let Predicates = [HasSVE2_or_SME] in { defm SQRSHLR_ZPmZ : sve2_int_arith_pred<0b011100, "sqrshlr", null_frag, "SQRSHLR_ZPZZ", DestructiveBinaryCommWithRev, "SQRSHL_ZPmZ", /*isReverseInstr*/ 1>; defm UQRSHLR_ZPmZ : sve2_int_arith_pred<0b011110, "uqrshlr", null_frag, "UQRSHLR_ZPZZ", DestructiveBinaryCommWithRev, "UQRSHL_ZPmZ", /*isReverseInstr*/ 1>; - defm SRSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd; - defm URSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd; - defm SQSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd; - defm UQSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd; - defm SQRSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd; - defm UQRSHL_ZPZZ : sve_int_bin_pred_all_active_bhsd; + defm SRSHL_ZPZZ : sve_int_bin_pred_bhsd; + defm URSHL_ZPZZ : sve_int_bin_pred_bhsd; + defm SQSHL_ZPZZ : sve_int_bin_pred_bhsd; + defm UQSHL_ZPZZ : sve_int_bin_pred_bhsd; + defm SQRSHL_ZPZZ : sve_int_bin_pred_bhsd; + defm UQRSHL_ZPZZ : sve_int_bin_pred_bhsd; } // End HasSVE2_or_SME let Predicates = [HasSVE2_or_SME, UseExperimentalZeroingPseudos] in { @@ -3909,6 +3909,9 @@ let Predicates = [HasSVE2_or_SME] in { defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right< 0b1101, "urshr", "URSHR_ZPZI", AArch64urshri_p>; defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu", "SQSHLU_ZPZI", int_aarch64_sve_sqshlu>; + defm SQSHL_ZPZI : sve_int_shift_pred_bhsd; + defm UQSHL_ZPZI : sve_int_shift_pred_bhsd; + // SVE2 integer add/subtract long defm SADDLB_ZZZ : sve2_wide_int_arith_long<0b00000, "saddlb", int_aarch64_sve_saddlb>; defm SADDLT_ZZZ : sve2_wide_int_arith_long<0b00001, "saddlt", int_aarch64_sve_saddlt>; diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 3a5f1499f9d2d..f11bd7c6a5a6b 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -1446,10 +1446,22 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) { case Intrinsic::aarch64_sve_orr: return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_orr_u) .setMatchingIROpcode(Instruction::Or); + case Intrinsic::aarch64_sve_sqrshl: + return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqrshl_u); + case Intrinsic::aarch64_sve_sqshl: + return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqshl_u); case Intrinsic::aarch64_sve_sqsub: return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqsub_u); + case Intrinsic::aarch64_sve_srshl: + return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_srshl_u); + case Intrinsic::aarch64_sve_uqrshl: + return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uqrshl_u); + case Intrinsic::aarch64_sve_uqshl: + return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uqshl_u); case Intrinsic::aarch64_sve_uqsub: return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uqsub_u); + case Intrinsic::aarch64_sve_urshl: + return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_urshl_u); case Intrinsic::aarch64_sve_add_u: return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode( diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll index 13e1eae8caec8..a471625cd5ad8 100644 --- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll +++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp-undef.ll @@ -1,54 +1,1090 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s +; +; SQRSHL +; + +define @sqrshl_i8( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @sqrshl_i16( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @sqrshl_i32( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @sqrshl_i64( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; SQRSHL (swapped operands) +; + +define @sqrshl_i8_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i8_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv16i8( %pg, + %b, + %a) + ret %out +} + +define @sqrshl_i16_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i16_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshlr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv8i16( %pg, + %b, + %a) + ret %out +} + +define @sqrshl_i32_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i32_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshlr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv4i32( %pg, + %b, + %a) + ret %out +} + +define @sqrshl_i64_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqrshl_i64_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqrshlr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv2i64( %pg, + %b, + %a) + ret %out +} + +; +; SQRSHL (movprfx) +; + +define @sqrshl_i8_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqrshl_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @sqrshl_i16_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqrshl_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqrshl z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @sqrshl_i32_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqrshl_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqrshl z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @sqrshl_i64_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqrshl_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqrshl z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqrshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; SQSHL (Vectors) +; + +define @sqshl_i8( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @sqshl_i16( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @sqshl_i32( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @sqshl_i64( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; SQSHL (Vectors, swapped operands) +; + +define @sqshl_i8_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i8_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshlr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv16i8( %pg, + %b, + %a) + ret %out +} + +define @sqshl_i16_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i16_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshlr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv8i16( %pg, + %b, + %a) + ret %out +} + +define @sqshl_i32_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i32_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshlr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv4i32( %pg, + %b, + %a) + ret %out +} + +define @sqshl_i64_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: sqshl_i64_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshlr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv2i64( %pg, + %b, + %a) + ret %out +} + +; +; SQSHL (Vectors, movpfrx) +; + +define @sqshl_i8_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqshl_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @sqshl_i16_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqshl_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @sqshl_i32_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqshl_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @sqshl_i64_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: sqshl_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; SQSHL (Immediate) +; + +define @sqshl_n_i8( %pg, %a) { +; CHECK-LABEL: sqshl_n_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #7 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv16i8( %pg, + %a, + splat (i8 7)) + ret %out +} + +define @sqshl_n_i16( %pg, %a) { +; CHECK-LABEL: sqshl_n_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #15 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv8i16( %pg, + %a, + splat (i16 15)) + ret %out +} + +define @sqshl_n_i32( %pg, %a) { +; CHECK-LABEL: sqshl_n_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #31 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv4i32( %pg, + %a, + splat (i32 31)) + ret %out +} + +define @sqshl_n_i64( %pg, %a) { +; CHECK-LABEL: sqshl_n_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #63 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv2i64( %pg, + %a, + splat (i64 63)) + ret %out +} + +define @sqshl_n_i8_out_of_range( %pg, %a) { +; CHECK-LABEL: sqshl_n_i8_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.b, #8 // =0x8 +; CHECK-NEXT: sqshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv16i8( %pg, + %a, + splat (i8 8)) + ret %out +} + +define @sqshl_n_i16_out_of_range( %pg, %a) { +; CHECK-LABEL: sqshl_n_i16_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.h, #16 // =0x10 +; CHECK-NEXT: sqshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv8i16( %pg, + %a, + splat (i16 16)) + ret %out +} + +define @sqshl_n_i32_out_of_range( %pg, %a) { +; CHECK-LABEL: sqshl_n_i32_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.s, #32 // =0x20 +; CHECK-NEXT: sqshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv4i32( %pg, + %a, + splat (i32 32)) + ret %out +} + +define @sqshl_n_i64_out_of_range( %pg, %a) { +; CHECK-LABEL: sqshl_n_i64_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.d, #64 // =0x40 +; CHECK-NEXT: sqshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv2i64( %pg, + %a, + splat (i64 64)) + ret %out +} + +; +; SQSHL (Immediate, movprfx) +; + +define @sqshl_n_i8_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: sqshl_n_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.b, p0/m, z0.b, #7 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv16i8( %pg, + %a, + splat (i8 7)) + ret %out +} + +define @sqshl_n_i16_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: sqshl_n_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.h, p0/m, z0.h, #15 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv8i16( %pg, + %a, + splat (i16 15)) + ret %out +} + +define @sqshl_n_i32_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: sqshl_n_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.s, p0/m, z0.s, #31 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv4i32( %pg, + %a, + splat (i32 31)) + ret %out +} + +define @sqshl_n_i64_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: sqshl_n_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: sqshl z0.d, p0/m, z0.d, #63 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqshl.u.nxv2i64( %pg, + %a, + splat (i64 63)) + ret %out +} + ; ; SQSUB ; -define @sqsub_i8_u( %pg, %a, %b) { -; CHECK-LABEL: sqsub_i8_u: +define @sqsub_i8_u( %pg, %a, %b) { +; CHECK-LABEL: sqsub_i8_u: +; CHECK: // %bb.0: +; CHECK-NEXT: sqsub z0.b, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqsub.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @sqsub_i16_u( %pg, %a, %b) { +; CHECK-LABEL: sqsub_i16_u: +; CHECK: // %bb.0: +; CHECK-NEXT: sqsub z0.h, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqsub.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @sqsub_i32_u( %pg, %a, %b) { +; CHECK-LABEL: sqsub_i32_u: +; CHECK: // %bb.0: +; CHECK-NEXT: sqsub z0.s, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqsub.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @sqsub_i64_u( %pg, %a, %b) { +; CHECK-LABEL: sqsub_i64_u: +; CHECK: // %bb.0: +; CHECK-NEXT: sqsub z0.d, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.sqsub.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; SRSHL +; + +define @srshl_i8( %pg, %a, %b) { +; CHECK-LABEL: srshl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: srshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @srshl_i16( %pg, %a, %b) { +; CHECK-LABEL: srshl_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: srshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @srshl_i32( %pg, %a, %b) { +; CHECK-LABEL: srshl_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: srshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @srshl_i64( %pg, %a, %b) { +; CHECK-LABEL: srshl_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: srshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; SRSHL (swapped operands) +; + +define @srshl_i8_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: srshl_i8_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv16i8( %pg, + %b, + %a) + ret %out +} + +define @srshl_i16_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: srshl_i16_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: srshlr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv8i16( %pg, + %b, + %a) + ret %out +} + +define @srshl_i32_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: srshl_i32_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: srshlr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv4i32( %pg, + %b, + %a) + ret %out +} + +define @srshl_i64_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: srshl_i64_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: srshlr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv2i64( %pg, + %b, + %a) + ret %out +} + +; +; SRSHL (movprfx) +; + +define @srshl_i8_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: srshl_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: srshl z0.b, p0/m, z0.b, z2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @srshl_i16_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: srshl_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: srshl z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @srshl_i32_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: srshl_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: srshl z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @srshl_i64_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: srshl_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: srshl z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.srshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; UQRSHL +; + +define @uqrshl_i8( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @uqrshl_i16( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @uqrshl_i32( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @uqrshl_i64( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; UQRSHL (swapped operands) +; + +define @uqrshl_i8_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i8_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv16i8( %pg, + %b, + %a) + ret %out +} + +define @uqrshl_i16_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i16_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshlr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv8i16( %pg, + %b, + %a) + ret %out +} + +define @uqrshl_i32_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i32_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshlr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv4i32( %pg, + %b, + %a) + ret %out +} + +define @uqrshl_i64_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqrshl_i64_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqrshlr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv2i64( %pg, + %b, + %a) + ret %out +} + +; +; UQRSHL (movprfx) +; + +define @uqrshl_i8_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqrshl_i8_movprfx: ; CHECK: // %bb.0: -; CHECK-NEXT: sqsub z0.b, z0.b, z1.b +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqrshl z0.b, p0/m, z0.b, z2.b ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.sqsub.u.nxv16i8( %pg, + %out = call @llvm.aarch64.sve.uqrshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @uqrshl_i16_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqrshl_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqrshl z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @uqrshl_i32_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqrshl_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqrshl z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @uqrshl_i64_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqrshl_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqrshl z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqrshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; UQSHL (Vectors) +; + +define @uqshl_i8( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv16i8( %pg, %a, %b) ret %out } -define @sqsub_i16_u( %pg, %a, %b) { -; CHECK-LABEL: sqsub_i16_u: +define @uqshl_i16( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i16: ; CHECK: // %bb.0: -; CHECK-NEXT: sqsub z0.h, z0.h, z1.h +; CHECK-NEXT: uqshl z0.h, p0/m, z0.h, z1.h ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.sqsub.u.nxv8i16( %pg, + %out = call @llvm.aarch64.sve.uqshl.u.nxv8i16( %pg, %a, %b) ret %out } -define @sqsub_i32_u( %pg, %a, %b) { -; CHECK-LABEL: sqsub_i32_u: +define @uqshl_i32( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i32: ; CHECK: // %bb.0: -; CHECK-NEXT: sqsub z0.s, z0.s, z1.s +; CHECK-NEXT: uqshl z0.s, p0/m, z0.s, z1.s ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.sqsub.u.nxv4i32( %pg, + %out = call @llvm.aarch64.sve.uqshl.u.nxv4i32( %pg, %a, %b) ret %out } -define @sqsub_i64_u( %pg, %a, %b) { -; CHECK-LABEL: sqsub_i64_u: +define @uqshl_i64( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i64: ; CHECK: // %bb.0: -; CHECK-NEXT: sqsub z0.d, z0.d, z1.d +; CHECK-NEXT: uqshl z0.d, p0/m, z0.d, z1.d ; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.sqsub.u.nxv2i64( %pg, + %out = call @llvm.aarch64.sve.uqshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; UQSHL (Vectors, swapped operands) +; + +define @uqshl_i8_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i8_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv16i8( %pg, + %b, + %a) + ret %out +} + +define @uqshl_i16_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i16_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshlr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv8i16( %pg, + %b, + %a) + ret %out +} + +define @uqshl_i32_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i32_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshlr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv4i32( %pg, + %b, + %a) + ret %out +} + +define @uqshl_i64_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: uqshl_i64_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshlr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv2i64( %pg, + %b, + %a) + ret %out +} + +; +; UQSHL (Vectors, movprfx) +; + +define @uqshl_i8_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqshl_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @uqshl_i16_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqshl_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @uqshl_i32_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqshl_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @uqshl_i64_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: uqshl_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv2i64( %pg, %a, %b) ret %out } +; +; UQSHL (Immediate) +; + +define @uqshl_n_i8( %pg, %a) { +; CHECK-LABEL: uqshl_n_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #7 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv16i8( %pg, + %a, + splat(i8 7)) + ret %out +} + +define @uqshl_n_i16( %pg, %a) { +; CHECK-LABEL: uqshl_n_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #15 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv8i16( %pg, + %a, + splat(i16 15)) + ret %out +} + +define @uqshl_n_i32( %pg, %a) { +; CHECK-LABEL: uqshl_n_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #31 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv4i32( %pg, + %a, + splat(i32 31)) + ret %out +} + +define @uqshl_n_i64( %pg, %a) { +; CHECK-LABEL: uqshl_n_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #63 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv2i64( %pg, + %a, + splat(i64 63)) + ret %out +} + +define @uqshl_n_i8_out_of_range( %pg, %a) { +; CHECK-LABEL: uqshl_n_i8_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.b, #8 // =0x8 +; CHECK-NEXT: uqshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv16i8( %pg, + %a, + splat(i8 8)) + ret %out +} + +define @uqshl_n_i16_out_of_range( %pg, %a) { +; CHECK-LABEL: uqshl_n_i16_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.h, #16 // =0x10 +; CHECK-NEXT: uqshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv8i16( %pg, + %a, + splat(i16 16)) + ret %out +} + +define @uqshl_n_i32_out_of_range( %pg, %a) { +; CHECK-LABEL: uqshl_n_i32_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.s, #32 // =0x20 +; CHECK-NEXT: uqshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv4i32( %pg, + %a, + splat(i32 32)) + ret %out +} + +define @uqshl_n_i64_out_of_range( %pg, %a) { +; CHECK-LABEL: uqshl_n_i64_out_of_range: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z1.d, #64 // =0x40 +; CHECK-NEXT: uqshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv2i64( %pg, + %a, + splat(i64 64)) + ret %out +} + +; +; UQSHL (Immediate, movprfx) +; + +define @uqshl_n_i8_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: uqshl_n_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.b, p0/m, z0.b, #7 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv16i8( %pg, + %a, + splat(i8 7)) + ret %out +} + +define @uqshl_n_i16_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: uqshl_n_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.h, p0/m, z0.h, #15 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv8i16( %pg, + %a, + splat(i16 15)) + ret %out +} + +define @uqshl_n_i32_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: uqshl_n_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.s, p0/m, z0.s, #31 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv4i32( %pg, + %a, + splat(i32 31)) + ret %out +} + +define @uqshl_n_i64_movprfx( %pg, %unused, %a) { +; CHECK-LABEL: uqshl_n_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: uqshl z0.d, p0/m, z0.d, #63 +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.uqshl.u.nxv2i64( %pg, + %a, + splat(i64 63)) + ret %out +} + ; ; UQSUB ; @@ -97,12 +1133,150 @@ define @uqsub_i64_u( %pg, ret %out } -declare @llvm.aarch64.sve.uqsub.u.nxv16i8(, , ) -declare @llvm.aarch64.sve.uqsub.u.nxv8i16(, , ) -declare @llvm.aarch64.sve.uqsub.u.nxv4i32(, , ) -declare @llvm.aarch64.sve.uqsub.u.nxv2i64(, , ) +; +; URSHL +; + +define @urshl_i8( %pg, %a, %b) { +; CHECK-LABEL: urshl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: urshl z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @urshl_i16( %pg, %a, %b) { +; CHECK-LABEL: urshl_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: urshl z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @urshl_i32( %pg, %a, %b) { +; CHECK-LABEL: urshl_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: urshl z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} + +define @urshl_i64( %pg, %a, %b) { +; CHECK-LABEL: urshl_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: urshl z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} + +; +; URSHL (swapped operands) +; + +define @urshl_i8_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: urshl_i8_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv16i8( %pg, + %b, + %a) + ret %out +} + +define @urshl_i16_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: urshl_i16_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: urshlr z0.h, p0/m, z0.h, z1.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv8i16( %pg, + %b, + %a) + ret %out +} + +define @urshl_i32_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: urshl_i32_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: urshlr z0.s, p0/m, z0.s, z1.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv4i32( %pg, + %b, + %a) + ret %out +} + +define @urshl_i64_swapped_operands( %pg, %a, %b) { +; CHECK-LABEL: urshl_i64_swapped_operands: +; CHECK: // %bb.0: +; CHECK-NEXT: urshlr z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv2i64( %pg, + %b, + %a) + ret %out +} + +; +; URSHL (movprfx) +; + +define @urshl_i8_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: urshl_i8_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: urshl z0.b, p0/m, z0.b, z2.b +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv16i8( %pg, + %a, + %b) + ret %out +} + +define @urshl_i16_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: urshl_i16_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: urshl z0.h, p0/m, z0.h, z2.h +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv8i16( %pg, + %a, + %b) + ret %out +} + +define @urshl_i32_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: urshl_i32_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: urshl z0.s, p0/m, z0.s, z2.s +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv4i32( %pg, + %a, + %b) + ret %out +} -declare @llvm.aarch64.sve.sqsub.u.nxv16i8(, , ) -declare @llvm.aarch64.sve.sqsub.u.nxv8i16(, , ) -declare @llvm.aarch64.sve.sqsub.u.nxv4i32(, , ) -declare @llvm.aarch64.sve.sqsub.u.nxv2i64(, , ) +define @urshl_i64_movprfx( %pg, %unused, %a, %b) { +; CHECK-LABEL: urshl_i64_movprfx: +; CHECK: // %bb.0: +; CHECK-NEXT: movprfx z0, z1 +; CHECK-NEXT: urshl z0.d, p0/m, z0.d, z2.d +; CHECK-NEXT: ret + %out = call @llvm.aarch64.sve.urshl.u.nxv2i64( %pg, + %a, + %b) + ret %out +} diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp.ll index 1b6873e84b09e..d76b8c7f8dc2a 100644 --- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp.ll +++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-uniform-dsp.ll @@ -771,74 +771,6 @@ define @sqrshl_i64( %pg, ret %out } -; -; SQRSHLR -; - -define @sqrshlr_i8( %a, %b) { -; CHECK-LABEL: sqrshlr_i8: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: sqrshlr z0.b, p0/m, z0.b, z1.b -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) - %out = call @llvm.aarch64.sve.sqrshl.nxv16i8( %pg, - %b, - %a) - ret %out -} - -define @sqrshlr_i16( %a, %b) { -; CHECK-LABEL: sqrshlr_i16: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: sqrshlr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) - %out = call @llvm.aarch64.sve.sqrshl.nxv8i16( %pg, - %b, - %a) - ret %out -} - -define @sqrshlr_i32( %a, %b) { -; CHECK-LABEL: sqrshlr_i32: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: sqrshlr z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) - %out = call @llvm.aarch64.sve.sqrshl.nxv4i32( %pg, - %b, - %a) - ret %out -} - -define @sqrshlr_i64( %a, %b) { -; CHECK-LABEL: sqrshlr_i64: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: sqrshlr z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) - %out = call @llvm.aarch64.sve.sqrshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - -define @sqrshlr_i64_noptrue( %pg, %a, %b) { -; CHECK-LABEL: sqrshlr_i64_noptrue: -; CHECK: // %bb.0: -; CHECK-NEXT: sqrshl z1.d, p0/m, z1.d, z0.d -; CHECK-NEXT: mov z0.d, z1.d -; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.sqrshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - ; ; SQSHL (Vectors) ; @@ -887,74 +819,6 @@ define @sqshl_i64( %pg, % ret %out } -; -; SQSHLR -; - -define @sqshlr_i8( %a, %b) { -; CHECK-LABEL: sqshlr_i8: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: sqshlr z0.b, p0/m, z0.b, z1.b -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) - %out = call @llvm.aarch64.sve.sqshl.nxv16i8( %pg, - %b, - %a) - ret %out -} - -define @sqshlr_i16( %a, %b) { -; CHECK-LABEL: sqshlr_i16: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: sqshlr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) - %out = call @llvm.aarch64.sve.sqshl.nxv8i16( %pg, - %b, - %a) - ret %out -} - -define @sqshlr_i32( %a, %b) { -; CHECK-LABEL: sqshlr_i32: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: sqshlr z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) - %out = call @llvm.aarch64.sve.sqshl.nxv4i32( %pg, - %b, - %a) - ret %out -} - -define @sqshlr_i64( %a, %b) { -; CHECK-LABEL: sqshlr_i64: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: sqshlr z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) - %out = call @llvm.aarch64.sve.sqshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - -define @sqshlr_i64_noptrue( %pg, %a, %b) { -; CHECK-LABEL: sqshlr_i64_noptrue: -; CHECK: // %bb.0: -; CHECK-NEXT: sqshl z1.d, p0/m, z1.d, z0.d -; CHECK-NEXT: mov z0.d, z1.d -; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.sqshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - ; ; SQSHL (Scalar) ; @@ -1346,75 +1210,6 @@ define @srshl_i64( %pg, % %b) ret %out } - -; -; SRSHLR -; - -define @srshlr_i8( %a, %b) { -; CHECK-LABEL: srshlr_i8: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: srshlr z0.b, p0/m, z0.b, z1.b -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) - %out = call @llvm.aarch64.sve.srshl.nxv16i8( %pg, - %b, - %a) - ret %out -} - -define @srshlr_i16( %a, %b) { -; CHECK-LABEL: srshlr_i16: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: srshlr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) - %out = call @llvm.aarch64.sve.srshl.nxv8i16( %pg, - %b, - %a) - ret %out -} - -define @srshlr_i32( %a, %b) { -; CHECK-LABEL: srshlr_i32: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: srshlr z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) - %out = call @llvm.aarch64.sve.srshl.nxv4i32( %pg, - %b, - %a) - ret %out -} - -define @srshlr_i64( %a, %b) { -; CHECK-LABEL: srshlr_i64: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: srshlr z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) - %out = call @llvm.aarch64.sve.srshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - -define @srshlr_i64_noptrue( %pg, %a, %b) { -; CHECK-LABEL: srshlr_i64_noptrue: -; CHECK: // %bb.0: -; CHECK-NEXT: srshl z1.d, p0/m, z1.d, z0.d -; CHECK-NEXT: mov z0.d, z1.d -; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.srshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - ; ; SRSHR ; @@ -1895,74 +1690,6 @@ define @uqrshl_i64( %pg, ret %out } -; -; UQRSHLR -; - -define @uqrshlr_i8( %a, %b) { -; CHECK-LABEL: uqrshlr_i8: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: uqrshlr z0.b, p0/m, z0.b, z1.b -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) - %out = call @llvm.aarch64.sve.uqrshl.nxv16i8( %pg, - %b, - %a) - ret %out -} - -define @uqrshlr_i16( %a, %b) { -; CHECK-LABEL: uqrshlr_i16: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: uqrshlr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) - %out = call @llvm.aarch64.sve.uqrshl.nxv8i16( %pg, - %b, - %a) - ret %out -} - -define @uqrshlr_i32( %a, %b) { -; CHECK-LABEL: uqrshlr_i32: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: uqrshlr z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) - %out = call @llvm.aarch64.sve.uqrshl.nxv4i32( %pg, - %b, - %a) - ret %out -} - -define @uqrshlr_i64( %a, %b) { -; CHECK-LABEL: uqrshlr_i64: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: uqrshlr z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) - %out = call @llvm.aarch64.sve.uqrshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - -define @uqrshlr_i64_noptrue( %pg, %a, %b) { -; CHECK-LABEL: uqrshlr_i64_noptrue: -; CHECK: // %bb.0: -; CHECK-NEXT: uqrshl z1.d, p0/m, z1.d, z0.d -; CHECK-NEXT: mov z0.d, z1.d -; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.uqrshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - ; ; UQSHL (Vectors) ; @@ -2011,74 +1738,6 @@ define @uqshl_i64( %pg, % ret %out } -; -; UQSHLR -; - -define @uqshlr_i8( %a, %b) { -; CHECK-LABEL: uqshlr_i8: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: uqshlr z0.b, p0/m, z0.b, z1.b -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) - %out = call @llvm.aarch64.sve.uqshl.nxv16i8( %pg, - %b, - %a) - ret %out -} - -define @uqshlr_i16( %a, %b) { -; CHECK-LABEL: uqshlr_i16: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: uqshlr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) - %out = call @llvm.aarch64.sve.uqshl.nxv8i16( %pg, - %b, - %a) - ret %out -} - -define @uqshlr_i32( %a, %b) { -; CHECK-LABEL: uqshlr_i32: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: uqshlr z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) - %out = call @llvm.aarch64.sve.uqshl.nxv4i32( %pg, - %b, - %a) - ret %out -} - -define @uqshlr_i64( %a, %b) { -; CHECK-LABEL: uqshlr_i64: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: uqshlr z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) - %out = call @llvm.aarch64.sve.uqshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - -define @uqshlr_i64_noptrue( %pg, %a, %b) { -; CHECK-LABEL: uqshlr_i64_noptrue: -; CHECK: // %bb.0: -; CHECK-NEXT: uqshl z1.d, p0/m, z1.d, z0.d -; CHECK-NEXT: mov z0.d, z1.d -; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.uqshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - ; ; UQSHL (Scalar) ; @@ -2390,74 +2049,6 @@ define @urshl_i64( %pg, % ret %out } -; -; URSHLR -; - -define @urshlr_i8( %a, %b) { -; CHECK-LABEL: urshlr_i8: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: urshlr z0.b, p0/m, z0.b, z1.b -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) - %out = call @llvm.aarch64.sve.urshl.nxv16i8( %pg, - %b, - %a) - ret %out -} - -define @urshlr_i16( %a, %b) { -; CHECK-LABEL: urshlr_i16: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: urshlr z0.h, p0/m, z0.h, z1.h -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) - %out = call @llvm.aarch64.sve.urshl.nxv8i16( %pg, - %b, - %a) - ret %out -} - -define @urshlr_i32( %a, %b) { -; CHECK-LABEL: urshlr_i32: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: urshlr z0.s, p0/m, z0.s, z1.s -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) - %out = call @llvm.aarch64.sve.urshl.nxv4i32( %pg, - %b, - %a) - ret %out -} - -define @urshlr_i64( %a, %b) { -; CHECK-LABEL: urshlr_i64: -; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: urshlr z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: ret - %pg = call @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) - %out = call @llvm.aarch64.sve.urshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - -define @urshlr_i64_noptrue( %pg, %a, %b) { -; CHECK-LABEL: urshlr_i64_noptrue: -; CHECK: // %bb.0: -; CHECK-NEXT: urshl z1.d, p0/m, z1.d, z0.d -; CHECK-NEXT: mov z0.d, z1.d -; CHECK-NEXT: ret - %out = call @llvm.aarch64.sve.urshl.nxv2i64( %pg, - %b, - %a) - ret %out -} - ; ; URSHR ; @@ -2884,8 +2475,3 @@ declare @llvm.aarch64.sve.usra.nxv16i8(, @llvm.aarch64.sve.usra.nxv8i16(, , i32) declare @llvm.aarch64.sve.usra.nxv4i32(, , i32) declare @llvm.aarch64.sve.usra.nxv2i64(, , i32) - -declare @llvm.aarch64.sve.ptrue.nxv16i1(i32) -declare @llvm.aarch64.sve.ptrue.nxv8i1(i32) -declare @llvm.aarch64.sve.ptrue.nxv4i1(i32) -declare @llvm.aarch64.sve.ptrue.nxv2i1(i32) diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll index ddcaeaf44592e..b5420e9111746 100644 --- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll +++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-comb-no-active-lanes.ll @@ -848,8 +848,7 @@ declare @llvm.aarch64.sve.sqrshl.nxv4i32(, < define @simplify_sqrshl_intrinsic( %a, %b) #0 { ; CHECK-LABEL: define @simplify_sqrshl_intrinsic ; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( zeroinitializer, [[A]], [[B]]) -; CHECK-NEXT: ret [[R]] +; CHECK-NEXT: ret [[A]] ; %r = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( zeroinitializer, %a, %b) ret %r @@ -859,8 +858,7 @@ declare @llvm.aarch64.sve.sqshl.nxv4i32(, @simplify_sqshl_intrinsic( %a, %b) #0 { ; CHECK-LABEL: define @simplify_sqshl_intrinsic ; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.sqshl.nxv4i32( zeroinitializer, [[A]], [[B]]) -; CHECK-NEXT: ret [[R]] +; CHECK-NEXT: ret [[A]] ; %r = tail call @llvm.aarch64.sve.sqshl.nxv4i32( zeroinitializer, %a, %b) ret %r @@ -902,8 +900,7 @@ declare @llvm.aarch64.sve.srshl.nxv4i32(, @simplify_srshl_intrinsic( %a, %b) #0 { ; CHECK-LABEL: define @simplify_srshl_intrinsic ; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.srshl.nxv4i32( zeroinitializer, [[A]], [[B]]) -; CHECK-NEXT: ret [[R]] +; CHECK-NEXT: ret [[A]] ; %r = tail call @llvm.aarch64.sve.srshl.nxv4i32( zeroinitializer, %a, %b) ret %r @@ -1105,8 +1102,7 @@ declare @llvm.aarch64.sve.uqrshl.nxv4i32(, < define @simplify_uqrshl_intrinsic( %a, %b) #0 { ; CHECK-LABEL: define @simplify_uqrshl_intrinsic ; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( zeroinitializer, [[A]], [[B]]) -; CHECK-NEXT: ret [[R]] +; CHECK-NEXT: ret [[A]] ; %r = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( zeroinitializer, %a, %b) ret %r @@ -1116,8 +1112,7 @@ declare @llvm.aarch64.sve.uqshl.nxv4i32(, @simplify_uqshl_intrinsic( %a, %b) #0 { ; CHECK-LABEL: define @simplify_uqshl_intrinsic ; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.uqshl.nxv4i32( zeroinitializer, [[A]], [[B]]) -; CHECK-NEXT: ret [[R]] +; CHECK-NEXT: ret [[A]] ; %r = tail call @llvm.aarch64.sve.uqshl.nxv4i32( zeroinitializer, %a, %b) ret %r @@ -1170,8 +1165,7 @@ declare @llvm.aarch64.sve.urshl.nxv4i32(, @simplify_urshl_intrinsic( %a, %b) #0 { ; CHECK-LABEL: define @simplify_urshl_intrinsic ; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { -; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.urshl.nxv4i32( zeroinitializer, [[A]], [[B]]) -; CHECK-NEXT: ret [[R]] +; CHECK-NEXT: ret [[A]] ; %r = tail call @llvm.aarch64.sve.urshl.nxv4i32( zeroinitializer, %a, %b) ret %r diff --git a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-to-u-form.ll b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-to-u-form.ll index 8072b3f8f5394..96ac0efde8764 100644 --- a/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-to-u-form.ll +++ b/llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-to-u-form.ll @@ -357,6 +357,26 @@ define @replace_smulh_intrinsic_i32( %a, %r } +define @replace_sqrshl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_sqrshl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.sqrshl.u.nxv4i32( splat (i1 true), [[A]], [[B]]) +; CHECK-NEXT: ret [[R]] +; + %r = tail call @llvm.aarch64.sve.sqrshl.nxv4i32( splat (i1 true), %a, %b) + ret %r +} + +define @replace_sqshl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_sqshl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.sqshl.u.nxv4i32( splat (i1 true), [[A]], [[B]]) +; CHECK-NEXT: ret [[R]] +; + %r = tail call @llvm.aarch64.sve.sqshl.nxv4i32( splat (i1 true), %a, %b) + ret %r +} + declare @llvm.aarch64.sve.sqsub.nxv4i32(, , ) define @replace_sqsub_intrinsic_i32( %a, %b) #0 { ; CHECK-LABEL: define @replace_sqsub_intrinsic_i32 @@ -368,6 +388,16 @@ define @replace_sqsub_intrinsic_i32( %a, %r } +define @replace_srshl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_srshl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.srshl.u.nxv4i32( splat (i1 true), [[A]], [[B]]) +; CHECK-NEXT: ret [[R]] +; + %r = tail call @llvm.aarch64.sve.srshl.nxv4i32( splat (i1 true), %a, %b) + ret %r +} + declare @llvm.aarch64.sve.sub.nxv4i32(, , ) define @replace_sub_intrinsic_i32( %a, %b) #0 { ; CHECK-LABEL: define @replace_sub_intrinsic_i32 @@ -434,6 +464,26 @@ define @replace_umulh_intrinsic_i32( %a, %r } +define @replace_uqrshl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_uqrshl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.uqrshl.u.nxv4i32( splat (i1 true), [[A]], [[B]]) +; CHECK-NEXT: ret [[R]] +; + %r = tail call @llvm.aarch64.sve.uqrshl.nxv4i32( splat (i1 true), %a, %b) + ret %r +} + +define @replace_uqshl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_uqshl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.uqshl.u.nxv4i32( splat (i1 true), [[A]], [[B]]) +; CHECK-NEXT: ret [[R]] +; + %r = tail call @llvm.aarch64.sve.uqshl.nxv4i32( splat (i1 true), %a, %b) + ret %r +} + declare @llvm.aarch64.sve.uqsub.nxv4i32(, , ) define @replace_uqsub_intrinsic_i32( %a, %b) #0 { ; CHECK-LABEL: define @replace_uqsub_intrinsic_i32 @@ -445,4 +495,14 @@ define @replace_uqsub_intrinsic_i32( %a, %r } +define @replace_urshl_intrinsic_i32( %a, %b) #0 { +; CHECK-LABEL: define @replace_urshl_intrinsic_i32 +; CHECK-SAME: ( [[A:%.*]], [[B:%.*]]) #[[ATTR1]] { +; CHECK-NEXT: [[R:%.*]] = tail call @llvm.aarch64.sve.urshl.u.nxv4i32( splat (i1 true), [[A]], [[B]]) +; CHECK-NEXT: ret [[R]] +; + %r = tail call @llvm.aarch64.sve.urshl.nxv4i32( splat (i1 true), %a, %b) + ret %r +} + attributes #0 = { "target-features"="+sve,+sve2" }