[test-suite] Fix RISC-V Support in benchmark 1.3.0

Summary:
Fixed by backporting the upstream fix from here:
  google/benchmark#833

Reviewers: lebedev.ri

Reviewed By: lebedev.ri

Subscribers: asb, kito-cheng, shiva0217, rogfer01, rkruppe, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64237

llvm-svn: 365610

Author: lenary

MicroBenchmarks/libs/benchmark-1.3.0/README.llvm

@@ -0,0 +1,14 @@
+LLVM notes
+----------
+This directory contains the Google Benchmark source code. Currently, the checked out
+Benchmark library version is v1.3.0.
+
+This directory is under a different license than LLVM.
+
+Changes:
+* https://github.com/google/benchmark/commit/ff2c255af5bb2fc2e5cd3b3685f0c6283117ce73
+  is applied on top of v1.3.0 to add s390x Support.
+* https://github.com/google/benchmark/commit/aad6a5fa767529d3353bd3beb89e126c7b0868ca
+  is applied on top of v1.3.0 to add NetBSD Support.
+* https://github.com/google/benchmark/commit/4abdfbb802d1b514703223f5f852ce4a507d32d2
+  is applied on top of v1.3.0 to add RISC-V timer support.

MicroBenchmarks/libs/benchmark-1.3.0/src/cycleclock.h

@@ -164,6 +164,21 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
   uint64_t tsc;
   asm("stck %0" : "=Q" (tsc) : : "cc");
   return tsc;
+#elif defined(__riscv) // RISC-V
+  // Use RDCYCLE (and RDCYCLEH on riscv32)
+#if __riscv_xlen == 32
+  uint64_t cycles_low, cycles_hi0, cycles_hi1;
+  asm("rdcycleh %0" : "=r"(cycles_hi0));
+  asm("rdcycle %0" : "=r"(cycles_lo));
+  asm("rdcycleh %0" : "=r"(cycles_hi1));
+  // This matches the PowerPC overflow detection, above
+  cycles_lo &= -static_cast<int64_t>(cycles_hi0 == cycles_hi1);
+  return (cycles_hi1 << 32) | cycles_lo;
+#else
+  uint64_t cycles;
+  asm("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#endif
 #else
 // The soft failover to a generic implementation is automatic only for ARM.
 // For other platforms the developer is expected to make an attempt to create