[RISCV] Remove -force-tail-folding-style=data-with-evl from EVL configs

This shouldn't be needed any more.

Author: asb

zorg/buildbot/builders/annotated/rise-riscv-build.sh

@@ -29,7 +29,7 @@ case "$BUILDBOT_BUILDERNAME" in
     export BB_QEMU_MEM="64G"
     ;;
   "clang-riscv-rva23-evl-vec-2stage")
-    TARGET_CFLAGS="-march=rva23u64 -mllvm -force-tail-folding-style=data-with-evl -mllvm -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue"
+    TARGET_CFLAGS="-march=rva23u64 -mllvm -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue"
     export BB_IMG_DIR=$(pwd)/..
      # TODO: Switch to specifying rva23u64 once qemu on the builder is
      # upgraded to a version that recognises it.

zorg/buildbot/builders/annotated/rise-riscv-gauntlet-build.sh

@@ -97,7 +97,7 @@ for CONF in rva20 rva22 rva23 rva23-evl rva23-mrvv-vec-bits; do
       QEMU_CPU=$RVA23_QEMU_CPU
       ;;
     rva23-evl)
-      CFLAGS="-march=rva23u64 -mllvm -force-tail-folding-style=data-with-evl -mllvm -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue"
+      CFLAGS="-march=rva23u64 -mllvm -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue"
       QEMU_CPU=$RVA23_QEMU_CPU
       ;;
     rva23-mrvv-vec-bits)