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Add tests for asint16 (#299)
Add tests for asint16 with input types uint16_t, int16_t, and half. Closes #173
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#--- source.hlsl
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StructuredBuffer<half4> In0 : register(t0);
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RWStructuredBuffer<int16_t4> Out0 : register(u1);
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[numthreads(1,1,1)]
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void main() {
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Out0[0] = asint16(In0[0]);
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Out0[1] = int16_t4(asint16(In0[1].xyz), asint16(In0[1].w));
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Out0[2] = int16_t4(asint16(In0[2].xy), asint16(In0[2].zw));
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Out0[3] = asint16(half4(-5, 0, 10.111, 0.05));
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: In0
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Format: Float16
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Stride: 8
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Data: [0xc500, 0, 0x490e, 0x2a66, 0xbc00, 0x5640, 0xc500, 0, 0x490e, 0x2a66, 0xbc00, 0x5640]
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# [-5, 0, 10.111, 0.05, -1, 100, -5, 0, 10.111, 0.05, -1, 100]
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- Name: Out0
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Format: Int16
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Stride: 8
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ZeroInitSize: 32
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- Name: ExpectedOut0
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Format: Int16
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Stride: 8
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Data: [ -15104, 0, 18702, 10854, -17408, 22080, -15104, 0, 18702, 10854, -17408, 22080, -15104, 0, 18702, 10854 ]
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Results:
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- Result: Test0
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Rule: BufferExact
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Actual: Out0
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Expected: ExpectedOut0
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DescriptorSets:
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- Resources:
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- Name: In0
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: Out0
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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#--- end
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# REQUIRES: Int16
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# REQUIRES: Half
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# RUN: split-file %s %t
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# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o
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#--- source.hlsl
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StructuredBuffer<int16_t4> In0 : register(t0);
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StructuredBuffer<uint16_t4> In1 : register(t1);
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RWStructuredBuffer<int16_t4> Out0 : register(u2);
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RWStructuredBuffer<int16_t4> Out1 : register(u3);
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[numthreads(1,1,1)]
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void main() {
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Out0[0] = asint16(In0[0]);
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Out0[1] = int16_t4(asint16(In0[1].xyz), asint16(In0[1].w));
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Out0[2] = int16_t4(asint16(In0[2].xy), asint16(In0[2].zw));
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Out0[3] = asint16(int16_t4(0, 32767, -100, -32768));
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Out1[0] = asint16(In1[0]);
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Out1[1] = int16_t4(asint16(In1[1].xyz), asint16(In1[1].w));
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Out1[2] = int16_t4(asint16(In1[2].xy), asint16(In1[2].zw));
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Out1[3] = asint16(uint16_t4(0, 100, 65535, 10));
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [1, 1, 1]
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Buffers:
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- Name: In0
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Format: Int16
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Stride: 8
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Data: [0, 32767, -100, -32768, 10, 20, 30, 6000, -3000, -30000, 50, 60]
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- Name: In1
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Format: UInt16
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Stride: 8
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Data: [0, 100, 65535, 10, 20, 30, 40, 50, 60, 70, 80, 6000]
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- Name: Out0
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Format: Int16
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Stride: 8
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ZeroInitSize: 32
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- Name: ExpectedOut0
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Format: Int16
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Stride: 8
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Data: [0, 32767, -100, -32768, 10, 20, 30, 6000, -3000, -30000, 50, 60, 0, 32767, -100, -32768]
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- Name: Out1
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Format: Int16
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Stride: 8
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ZeroInitSize: 32
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- Name: ExpectedOut1
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Format: Int16
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Stride: 8
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Data: [ 0, 100, -1, 10, 20, 30, 40, 50, 60, 70, 80, 6000, 0, 100, -1, 10 ]
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Results:
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- Result: Test0
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Rule: BufferExact
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Actual: Out0
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Expected: ExpectedOut0
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- Result: Test1
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Rule: BufferExact
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Actual: Out1
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Expected: ExpectedOut1
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DescriptorSets:
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- Resources:
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- Name: In0
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: In1
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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- Name: Out0
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: Out1
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 3
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Space: 0
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VulkanBinding:
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Binding: 3
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#--- end
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# REQUIRES: Int16
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# RUN: split-file %s %t
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# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

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