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bob80905Finn Plummer
bob80905
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Finn Plummer
authored
Add WaveReadLaneAt tests (#349)
This PR implements testing for the WaveReadLaneAt intrinsic. It's an improved copy of @inbelic's work here: #295 - WaveReadLaneAt.[16|32|64].test adds testing of the basic types (and vectors) - WaveReadLaneAt.udt.test adds testing for a matrix, user defined struct and for floating point edge-case values - WaveReadLaneAt.index.test adds testing of various use-cases with different indices Resolves: #144 --------- Co-authored-by: Finn Plummer <[email protected]>
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‎test/WaveOps/WaveReadLaneAt.16.test

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#--- source.hlsl
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StructuredBuffer<int16_t4> InInt : register(t0);
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RWStructuredBuffer<int16_t4> OutInt : register(u1);
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StructuredBuffer<uint16_t4> InUInt : register(t2);
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RWStructuredBuffer<uint16_t4> OutUInt : register(u3);
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StructuredBuffer<float16_t4> InFloat : register(t4);
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RWStructuredBuffer<float16_t4> OutFloat : register(u5);
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[numthreads(4,1,1)]
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void main(uint32_t3 TID : SV_GroupThreadID) {
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uint OutIdx = TID.x * 3;
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// Int
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OutInt[OutIdx] = WaveReadLaneAt(InInt[TID.x], TID.x);
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uint16_t4 ThreadInInt = {InInt[TID.x].xyz, InInt[TID.x].w};
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OutInt[OutIdx + 1] = WaveReadLaneAt(ThreadInInt, TID.x);;
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OutInt[OutIdx + 2].xy = WaveReadLaneAt(InInt[TID.x].xy, TID.x);
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// UInt
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OutUInt[OutIdx] = WaveReadLaneAt(InUInt[TID.x], TID.x);
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int16_t4 ThreadInUInt = {InUInt[TID.x].xyz, InUInt[TID.x].w};
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OutUInt[OutIdx + 1] = WaveReadLaneAt(ThreadInUInt, TID.x);;
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OutUInt[OutIdx + 2].xy = WaveReadLaneAt(InUInt[TID.x].xy, TID.x);
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// Float
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OutFloat[OutIdx] = WaveReadLaneAt(InFloat[TID.x], TID.x);
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float16_t4 ThreadInFloat = {InFloat[TID.x].xyz, InFloat[TID.x].w};
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OutFloat[OutIdx + 1] = WaveReadLaneAt(ThreadInFloat, TID.x);;
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OutFloat[OutIdx + 2].xy = WaveReadLaneAt(InFloat[TID.x].xy, TID.x);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [4, 1, 1]
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Buffers:
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- Name: InInt
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Format: Int16
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Stride: 8
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ]
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- Name: OutInt
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Format: Int16
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Stride: 8
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ZeroInitSize: 72
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- Name: ExpectedOutInt # The result we expect
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Format: Int16
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Stride: 8
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Data: [ 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 0, 0, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 0, 0, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 0, 0 ]
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- Name: InUInt
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Format: UInt16
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Stride: 8
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ]
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- Name: OutUInt
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Format: UInt16
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Stride: 8
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ZeroInitSize: 72
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- Name: ExpectedOutUInt # The result we expect
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Format: UInt16
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Stride: 8
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Data: [ 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 0, 0, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 0, 0, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 0, 0 ]
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- Name: InFloat
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Format: Float16
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Stride: 8
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ]
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- Name: OutFloat
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Format: Float16
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Stride: 8
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ZeroInitSize: 72
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- Name: ExpectedOutFloat # The result we expect
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Format: Float16
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Stride: 8
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Data: [ 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 0, 0, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 0, 0, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 0, 0 ]
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Results:
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- Result: TestInt
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Rule: BufferExact
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Actual: OutInt
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Expected: ExpectedOutInt
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- Result: TestUInt
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Rule: BufferExact
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Actual: OutUInt
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Expected: ExpectedOutUInt
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- Result: TestFloat
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Rule: BufferExact
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Actual: OutFloat
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Expected: ExpectedOutFloat
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DescriptorSets:
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- Resources:
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- Name: InInt
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: OutInt
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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- Name: InUInt
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: OutUInt
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 3
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Space: 0
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VulkanBinding:
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Binding: 3
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- Name: InFloat
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 4
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Space: 0
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VulkanBinding:
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Binding: 4
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- Name: OutFloat
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 5
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Space: 0
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VulkanBinding:
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Binding: 5
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...
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#--- end
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# Tracked by https://github.com/llvm/offload-test-suite/issues/351
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# XFAIL: Metal
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# REQUIRES: Half, Int16
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# RUN: split-file %s %t
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# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

‎test/WaveOps/WaveReadLaneAt.32.test

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#--- source.hlsl
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StructuredBuffer<int4> InInt : register(t0);
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RWStructuredBuffer<int4> OutInt : register(u1);
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StructuredBuffer<uint4> InUInt : register(t2);
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RWStructuredBuffer<uint4> OutUInt : register(u3);
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StructuredBuffer<float4> InFloat : register(t4);
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RWStructuredBuffer<float4> OutFloat : register(u5);
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// Checks for edge-case floats
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StructuredBuffer<float> InEdgeFloat : register(t6);
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RWStructuredBuffer<float> OutEdgeFloat : register(u7);
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[numthreads(4,1,1)]
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void main(uint3 TID : SV_GroupThreadID) {
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uint OutIdx = TID.x * 3;
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// Int
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OutInt[OutIdx] = WaveReadLaneAt(InInt[TID.x], TID.x);
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uint4 ThreadInInt = {InInt[TID.x].xyz, InInt[TID.x].w};
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OutInt[OutIdx + 1] = WaveReadLaneAt(ThreadInInt, TID.x);
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OutInt[OutIdx + 2].xy = WaveReadLaneAt(InInt[TID.x].xy, TID.x);
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// UInt
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OutUInt[OutIdx] = WaveReadLaneAt(InUInt[TID.x], TID.x);
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uint4 ThreadInUInt = {InUInt[TID.x].xyz, InUInt[TID.x].w};
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OutUInt[OutIdx + 1] = WaveReadLaneAt(ThreadInUInt, TID.x);
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OutUInt[OutIdx + 2].xy = WaveReadLaneAt(InUInt[TID.x].xy, TID.x);
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// Float
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OutFloat[OutIdx] = WaveReadLaneAt(InFloat[TID.x], TID.x);
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uint4 ThreadInFloat = {InFloat[TID.x].xyz, InFloat[TID.x].w};
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OutFloat[OutIdx + 1] = WaveReadLaneAt(ThreadInFloat, TID.x);
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OutFloat[OutIdx + 2].xy = WaveReadLaneAt(InFloat[TID.x].xy, TID.x);
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// Edge-Cases
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OutEdgeFloat[TID.x] = WaveReadLaneAt(InEdgeFloat[TID.x], TID.x);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [4, 1, 1]
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Buffers:
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- Name: InInt
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Format: Int32
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Stride: 16
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ]
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- Name: OutInt
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Format: Int32
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Stride: 16
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ZeroInitSize: 144
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- Name: ExpectedOutInt # The result we expect
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Format: Int32
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Stride: 16
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Data: [ 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 0, 0, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 0, 0, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 0, 0 ]
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- Name: InUInt
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Format: UInt32
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Stride: 16
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ]
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- Name: OutUInt
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Format: UInt32
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Stride: 16
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ZeroInitSize: 144
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- Name: ExpectedOutUInt # The result we expect
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Format: UInt32
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Stride: 16
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Data: [ 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 0, 0, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 0, 0, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 0, 0 ]
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- Name: InFloat
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Format: Float32
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Stride: 16
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Data: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 ]
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- Name: OutFloat
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Format: Float32
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Stride: 16
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ZeroInitSize: 144
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- Name: ExpectedOutFloat # The result we expect
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Format: Float32
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Stride: 16
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Data: [ 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 0, 0, 4, 5, 6, 7, 4, 5, 6, 7, 4, 5, 0, 0, 8, 9, 10, 11, 8, 9, 10, 11, 8, 9, 0, 0 ]
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- Name: InEdgeFloat
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Format: Float32
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Stride: 4
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Data: [inf, -inf, nan, 0 ]
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- Name: OutEdgeFloat
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Format: Float32
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Stride: 4
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ZeroInitSize: 16
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- Name: ExpectedOutEdgeFloat # The result we expect
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Format: Float32
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Stride: 4
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Data: [ inf, -inf, nan, 0]
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Results:
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- Result: TestInt
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Rule: BufferExact
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Actual: OutInt
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Expected: ExpectedOutInt
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- Result: TestUInt
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Rule: BufferExact
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Actual: OutUInt
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Expected: ExpectedOutUInt
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- Result: TestFloat
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Rule: BufferExact
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Actual: OutFloat
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Expected: ExpectedOutFloat
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- Result: TestEdgeFloat
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Rule: BufferExact
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Actual: OutEdgeFloat
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Expected: ExpectedOutEdgeFloat
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DescriptorSets:
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- Resources:
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- Name: InInt
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: OutInt
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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- Name: InUInt
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 2
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Space: 0
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VulkanBinding:
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Binding: 2
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- Name: OutUInt
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 3
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Space: 0
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VulkanBinding:
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Binding: 3
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- Name: InFloat
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 4
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Space: 0
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VulkanBinding:
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Binding: 4
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- Name: OutFloat
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 5
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Space: 0
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VulkanBinding:
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Binding: 5
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- Name: InEdgeFloat
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 6
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Space: 0
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VulkanBinding:
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Binding: 6
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- Name: OutEdgeFloat
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 7
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Space: 0
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VulkanBinding:
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Binding: 7
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...
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#--- end
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# Tracked by https://github.com/llvm/offload-test-suite/issues/351
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# XFAIL: Metal
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Gis -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

‎test/WaveOps/WaveReadLaneAt.Bool.test

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#--- source.hlsl
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StructuredBuffer<bool4> InBool : register(t0);
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RWStructuredBuffer<bool4> OutBool : register(u1);
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[numthreads(4,1,1)]
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void main(uint32_t3 TID : SV_GroupThreadID) {
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uint OutIdx = TID.x * 3;
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// Bool
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OutBool[OutIdx] = WaveReadLaneAt(InBool[TID.x], TID.x);
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bool4 ThreadInBool = {InBool[TID.x].xyz, InBool[TID.x].w};
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OutBool[OutIdx + 1] = WaveReadLaneAt(ThreadInBool, TID.x);
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OutBool[OutIdx + 2].xy = WaveReadLaneAt(InBool[TID.x].xy, TID.x);
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}
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//--- pipeline.yaml
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---
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Shaders:
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- Stage: Compute
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Entry: main
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DispatchSize: [4, 1, 1]
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Buffers:
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- Name: InBool
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Format: Bool
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Stride: 16
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Data: [ 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 1 ]
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- Name: OutBool
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Format: Bool
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Stride: 16
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ZeroInitSize: 144
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- Name: ExpectedOutBool # The result we expect
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Format: Bool
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Stride: 16
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Data: [ 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0 ]
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Results:
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- Result: TestBool
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Rule: BufferExact
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Actual: OutBool
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Expected: ExpectedOutBool
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DescriptorSets:
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- Resources:
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- Name: InBool
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Kind: StructuredBuffer
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DirectXBinding:
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Register: 0
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Space: 0
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VulkanBinding:
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Binding: 0
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- Name: OutBool
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Kind: RWStructuredBuffer
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DirectXBinding:
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Register: 1
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Space: 0
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VulkanBinding:
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Binding: 1
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...
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#--- end
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# https://github.com/llvm/llvm-project/issues/140824
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# XFAIL: Clang
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# RUN: split-file %s %t
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# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
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# RUN: %offloader %t/pipeline.yaml %t.o

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