Skip to content

Commit 5256cf2

Browse files
authored
add tests for sinh (#254)
add 16 and 32 bit float tests for sinh closes #130
1 parent 9643c69 commit 5256cf2

File tree

2 files changed

+134
-0
lines changed

2 files changed

+134
-0
lines changed

test/Feature/HLSLLib/sinh.16.test

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
#--- source.hlsl
2+
3+
StructuredBuffer<half4> In : register(t0);
4+
5+
RWStructuredBuffer<half4> Out : register(u1);
6+
7+
[numthreads(1,1,1)]
8+
void main() {
9+
Out[0] = sinh(In[0]);
10+
half4 Tmp = {sinh(In[1].xyz), sinh(In[1].w)};
11+
Out[1] = Tmp;
12+
half4 Tmp2 = {sinh(In[2].xy), sinh(In[2].zw)};
13+
Out[2] = Tmp2;
14+
}
15+
16+
17+
//--- pipeline.yaml
18+
19+
---
20+
Shaders:
21+
- Stage: Compute
22+
Entry: main
23+
DispatchSize: [1, 1, 1]
24+
Buffers:
25+
- Name: In
26+
Format: Float16
27+
Stride: 8
28+
Data: [ 0x7e00, 0xfc00, 0x8001, 0x8000, 0x0000, 0x0001, 0x7c00, 0x3c00, 0xbc00, 0x7e00, 0x7e00, 0x7e00,]
29+
# NaN, -Inf, -denorm, -0, 0, denorm, Inf, 1, -1,
30+
- Name: Out
31+
Format: Float16
32+
Stride: 8
33+
ZeroInitSize: 24
34+
- Name: ExpectedOut # The result we expect
35+
Format: Float16
36+
Stride: 8
37+
Data: [ 0x7e00, 0xfc00, 0x0000, 0x0000, 0x0000, 0x0000, 0x7c00, 0x3cb3, 0xbcb3, 0x7e00, 0x7e00, 0x7e00,]
38+
# NaN, -Inf, 0.0, 0.0, 0.0, 0.0, Inf, 1.175201, -1.175201,
39+
Results:
40+
- Result: Test1
41+
Rule: BufferFloatEpsilon
42+
Epsilon: 0.0008
43+
Actual: Out
44+
Expected: ExpectedOut
45+
DescriptorSets:
46+
- Resources:
47+
- Name: In
48+
Kind: StructuredBuffer
49+
DirectXBinding:
50+
Register: 0
51+
Space: 0
52+
VulkanBinding:
53+
Binding: 0
54+
- Name: Out
55+
Kind: RWStructuredBuffer
56+
DirectXBinding:
57+
Register: 1
58+
Space: 0
59+
VulkanBinding:
60+
Binding: 1
61+
...
62+
#--- end
63+
64+
# REQUIRES: Half
65+
# RUN: split-file %s %t
66+
# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
67+
# RUN: %offloader %t/pipeline.yaml %t.o

test/Feature/HLSLLib/sinh.32.test

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
#--- source.hlsl
2+
3+
StructuredBuffer<float4> In : register(t0);
4+
5+
RWStructuredBuffer<float4> Out : register(u1);
6+
7+
[numthreads(1,1,1)]
8+
void main() {
9+
Out[0] = sinh(In[0]);
10+
float4 Tmp = {sinh(In[1].xyz), sinh(In[1].w)};
11+
Out[1] = Tmp;
12+
float4 Tmp2 = {sinh(In[2].xy), sinh(In[2].zw)};
13+
Out[2] = Tmp2;
14+
}
15+
16+
17+
//--- pipeline.yaml
18+
19+
---
20+
Shaders:
21+
- Stage: Compute
22+
Entry: main
23+
DispatchSize: [1, 1, 1]
24+
Buffers:
25+
- Name: In
26+
Format: Float32
27+
Stride: 16
28+
Data: [ nan, -inf, -0x1.e7d42cp-127, -0, 0, 0x1.e7d42cp-127, inf, 1, -1, nan, nan, nan,]
29+
# NaN, -Inf, -denorm, -0, 0, denorm, Inf, 1, -1,
30+
- Name: Out
31+
Format: Float32
32+
Stride: 16
33+
ZeroInitSize: 48
34+
- Name: ExpectedOut # The result we expect
35+
Format: Float32
36+
Stride: 16
37+
Data: [ nan, -inf, 0.0, 0.0, 0.0, 0.0, inf, 1.175201, -1.175201, nan, nan, nan,]
38+
# NaN, -Inf, 0.0, 0.0, 0.0, 0.0, Inf, 1.175201, -1.175201,
39+
Results:
40+
- Result: Test1
41+
Rule: BufferFloatEpsilon
42+
Epsilon: 0.0008
43+
Actual: Out
44+
Expected: ExpectedOut
45+
DescriptorSets:
46+
- Resources:
47+
- Name: In
48+
Kind: StructuredBuffer
49+
DirectXBinding:
50+
Register: 0
51+
Space: 0
52+
VulkanBinding:
53+
Binding: 0
54+
- Name: Out
55+
Kind: RWStructuredBuffer
56+
DirectXBinding:
57+
Register: 1
58+
Space: 0
59+
VulkanBinding:
60+
Binding: 1
61+
...
62+
#--- end
63+
64+
65+
# RUN: split-file %s %t
66+
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
67+
# RUN: %offloader %t/pipeline.yaml %t.o

0 commit comments

Comments
 (0)