Add test for UAV sequential consistency (#225)

This test aims to verify that UAV accesses are performed sequentially
and that the reads and writes are consistent such that a read which
occurs after a write must observe the effect of the write.

Author: llvm-beanz

.github/workflows/build-and-test-callable.yaml

@@ -158,6 +158,11 @@ jobs:
             cd build
             cmake -G Ninja ${{ inputs.LLVM-ExtraCMakeArgs }} -DCMAKE_BUILD_TYPE=${{ inputs.BuildType }} -DLLVM_ENABLE_ASSERTIONS=On -C ${{ github.workspace }}/llvm-project/clang/cmake/caches/HLSL.cmake -C ${{ github.workspace }}/OffloadTest/cmake/caches/sccache.cmake -DDXC_DIR=${{ github.workspace }}/DXC/build/bin -DLLVM_EXTERNAL_OFFLOADTEST_SOURCE_DIR=${{ github.workspace }}/OffloadTest -DLLVM_EXTERNAL_PROJECTS="OffloadTest" -DLLVM_LIT_ARGS="--xunit-xml-output=testresults.xunit.xml -v" -DOFFLOADTEST_TEST_CLANG=${{steps.Test-Clang.outputs.TEST_CLANG || 'Off' }} -DGOLDENIMAGE_DIR=${{ github.workspace }}/golden-images ${{ github.workspace }}/llvm-project/llvm/
             ninja hlsl-test-depends
+      - name: Dump GPU Info
+        run: |
+            cd llvm-project
+            cd build
+            ./bin/api-query
       - name: Run HLSL Tests
         run: |
             cd llvm-project

test/Bugs/Adjacent-Partial-Writes.yaml

@@ -0,0 +1,74 @@
+#--- source.hlsl
+
+StructuredBuffer<int64_t4> InInt : register(t0);
+RWStructuredBuffer<uint4> OutInt : register(u1);
+
+[numthreads(1,1,1)]
+void main() {
+  // Int
+  OutInt[0] = countbits(InInt[0]);
+  OutInt[1].xyz = countbits(InInt[0].xyz);
+  OutInt[1].w = countbits(InInt[0].w);
+  OutInt[2].xy = countbits(InInt[0].xy);
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: InInt
+    Format: Int64
+    Stride: 32
+    Data: [0x2A, 0, 0x0f0f0f0f0f0f0f0f, -1]
+  - Name: OutInt
+    Format: UInt32
+    Stride: 16
+    Data: [101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112]
+  - Name: ExpectedOut # The result we expect
+    Format: UInt32
+    Stride: 16
+    Data: [3, 0, 32, 64, 3, 0, 32, 64, 3, 0, 111, 112]
+Results:
+  - Result: Test1
+    Rule: BufferExact
+    Actual: OutInt
+    Expected: ExpectedOut
+DescriptorSets:
+  - Resources:
+    - Name: InInt
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: OutInt
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+...
+#--- end
+
+# REQUIRES: Int64
+
+# When compiled with DXC this test encounters a memory coherence issue on Intel
+# UHD drivers. This issue does not reproduce when compiled with Clang because
+# LLVM's load-store optimization performs correct optimizations that hide the
+# problem.
+# Tracking issue: https://github.com/llvm/offload-test-suite/issues/226
+# XFAIL: Intel-Memory-Coherence-Issue-226 && !Clang
+
+# https://github.com/microsoft/DirectXShaderCompiler/issues/7494
+# https://github.com/llvm/llvm-project/issues/142677
+# UNSUPPORTED: Vulkan
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o

test/Bugs/UAV-Sequental-Consistency.yaml

@@ -0,0 +1,68 @@
+#--- source.hlsl
+
+StructuredBuffer<uint32_t> X : register(t0);
+RWStructuredBuffer<uint32_t> Result : register(u1);
+
+[numthreads(1,1,1)]
+void main() {
+  Result[0] = X[0] + 1;
+  Result[1] = X[1] + Result[0];
+
+  Result[2] = X[0] + 2;
+  Result[3] = X[1] + Result[2];
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: X
+    Format: Int32
+    Stride: 4
+    Data: [ 0, 1 ]
+  - Name: Result
+    Format: Int32
+    Stride: 4
+    ZeroInitSize: 16
+  - Name: ExpectedResult
+    Format: Int32
+    Stride: 4
+    Data: [ 1, 2, 2, 3 ]
+Results:
+  - Result: CheckResult
+    Rule: BufferExact
+    Actual: Result
+    Expected: ExpectedResult
+DescriptorSets:
+  - Resources:
+    - Name: X
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Result
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+...
+#--- end
+
+# When compiled with DXC this test encounters a memory coherence issue on Intel
+# UHD drivers. This issue does not reproduce when compiled with Clang because
+# LLVM's load-store optimization performs correct optimizations that hide the
+# problem.
+# Tracking issue: https://github.com/llvm/offload-test-suite/issues/226
+# XFAIL: Intel-Memory-Coherence-Issue-226 && !Clang
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o

test/lit.cfg.py

@@ -55,6 +55,12 @@ def setDeviceFeatures(config, device, compiler):
         config.available_features.add("%s-WARP" % API)
     if "Intel" in device["Description"]:
         config.available_features.add("%s-Intel" % API)
+        if "UHD Graphics" in device["Description"] and API == "DirectX":
+            # When Intel resolves the driver issue and tests XFAILing on the
+            # feature below are resolved we can resolve
+            # https://github.com/llvm/offload-test-suite/issues/226 by updating
+            # this check to only XFAIL on old driver versions.
+            config.available_features.add("Intel-Memory-Coherence-Issue-226")
     if "NVIDIA" in device["Description"]:
         config.available_features.add("%s-NV" % API)
     if "AMD" in device["Description"]:
@@ -73,6 +79,7 @@ def setDeviceFeatures(config, device, compiler):
 
     if device["API"] == "Metal":
         config.available_features.add("Int16")
+        config.available_features.add("Int64")
         config.available_features.add("Half")
         config.available_features.add("Int64")