Add test for WaveIsFirstLane (#233)

Test divergent control flow and usage of WaveIsFirstLane.
Closes #126

Author: spall

test/Feature/WaveOps/WaveIsFirstLane.test

@@ -0,0 +1,66 @@
+#--- source.hlsl
+RWBuffer<int> value;
+RWStructuredBuffer<uint> Out : register(u1);
+
+[numthreads(4, 1, 1)]
+void main(uint3 threadID : SV_DispatchThreadID) { 
+  switch (value[threadID.x]) {
+    case 0:
+      Out[threadID.x] = WaveIsFirstLane(); // threads 0 and 1; 0 is first for both
+      break;
+    case 2:
+      Out[threadID.x] = WaveIsFirstLane(); // thread 3; 3 is first
+      break;
+    default:
+      Out[threadID.x] = WaveIsFirstLane(); // thread 2; 2 is first
+      break;
+  }
+  Out[threadID.x + 4] = WaveIsFirstLane(); // 0 is first for all
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: value
+    Format: Int32
+    Data: [ 0, 0, 1, 2]
+  - Name: Out
+    Format: UInt32
+    Stride: 4
+    ZeroInitSize: 32
+  - Name: ExpectedOut
+    Format: UInt32
+    Stride: 4
+    Data: [1, 0, 1, 1, 1, 0, 0, 0]
+Results:
+  - Result: Test
+    Rule: BufferExact
+    Actual: Out
+    Expected: ExpectedOut
+DescriptorSets:
+  - Resources:
+    - Name: value
+      Kind: RWBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+...
+#--- end
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o