diff --git a/lib/Support/Pipeline.cpp b/lib/Support/Pipeline.cpp index e36d92c6..08a6a990 100644 --- a/lib/Support/Pipeline.cpp +++ b/lib/Support/Pipeline.cpp @@ -111,13 +111,26 @@ void MappingTraits::mapping(IO &I, I.mapRequired("Data", Arr); \ } else { \ int64_t ZeroInitSize; \ + int64_t Size = 0; \ + std::optional Fill; \ I.mapOptional("ZeroInitSize", ZeroInitSize, 0); \ + I.mapOptional("Fill", Fill); \ + I.mapOptional("Size", Size, 0); \ if (ZeroInitSize > 0) { \ B.Size = ZeroInitSize; \ B.Data.reset(new char[B.Size]); \ memset(B.Data.get(), 0, B.Size); \ break; \ } \ + if (Fill.has_value()) { \ + if (Size == 0) \ + return I.setError("'Size' must be provided when using 'Fill'"); \ + B.Size = Size * sizeof(Type); \ + B.Data.reset(new char[B.Size]); \ + std::fill_n(reinterpret_cast(B.Data.get()), Size, \ + Fill.value()); \ + break; \ + } \ llvm::SmallVector Arr; \ I.mapRequired("Data", Arr); \ B.Size = Arr.size() * sizeof(Type); \ @@ -139,7 +152,8 @@ void MappingTraits::mapping(IO &I, DATA_CASE(Float16, llvm::yaml::Hex16) DATA_CASE(Float32, float) DATA_CASE(Float64, double) - DATA_CASE(Bool, uint32_t) // Because sizeof(bool) is 1 but HLSL represents a bool using 4 bytes. + DATA_CASE(Bool, uint32_t) // Because sizeof(bool) is 1 but HLSL represents a + // bool using 4 bytes. } I.mapOptional("OutputProps", B.OutputProps); diff --git a/test/MemExecModel/mem_conv_atomic_device.test b/test/MemExecModel/mem_conv_atomic_device.test new file mode 100644 index 00000000..5b3d270d --- /dev/null +++ b/test/MemExecModel/mem_conv_atomic_device.test @@ -0,0 +1,62 @@ +#--- source.hlsl +RWStructuredBuffer write_val : register(u0); +RWStructuredBuffer buf : register(u1); + +[numthreads(256,1,1)] +void main(uint3 TID : SV_DispatchThreadID) { + uint tid = TID.x; + uint temp; + InterlockedExchange(write_val[0], tid, temp); + uint read_val; + InterlockedAdd(write_val[0], 0, read_val); + // Check if all threads in the wave read the same value + buf[tid] = uint(WaveActiveAllEqual(read_val)); +} +//--- pipeline.yaml +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [6553, 1, 1] +Buffers: + - Name: write_val + Format: UInt32 + Stride: 4 + Data: [0] + - Name: buf + Format: UInt32 + Stride: 4 + Fill: 0 + Size: 1677568 + - Name: expected + Format: UInt32 + Stride: 4 + Fill: 1 + Size: 1677568 +Results: + - Result: Test1 + Rule: BufferExact + Actual: buf + Expected: expected +DescriptorSets: + - Resources: + - Name: write_val + Kind: RWStructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: buf + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 +... +#--- end + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/MemExecModel/mem_conv_atomic_group.test b/test/MemExecModel/mem_conv_atomic_group.test new file mode 100644 index 00000000..76c5a077 --- /dev/null +++ b/test/MemExecModel/mem_conv_atomic_group.test @@ -0,0 +1,53 @@ +#--- source.hlsl +RWStructuredBuffer buf : register(u0); +groupshared uint loc; + +[numthreads(256,1,1)] +void main(uint3 TID : SV_DispatchThreadID) { + uint temp; + loc = 0; + GroupMemoryBarrierWithGroupSync(); + uint tid = TID.x; + InterlockedExchange(loc, tid, temp); + uint read_val; + InterlockedAdd(loc, 0, read_val); + // Check if all threads in the wave read the same value + buf[tid] = uint(WaveActiveAllEqual(read_val)); +} +//--- pipeline.yaml +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [6553, 1, 1] +Buffers: + - Name: buf + Format: UInt32 + Stride: 4 + Fill: 0 + Size: 1677568 + - Name: expected + Format: UInt32 + Stride: 4 + Fill: 1 + Size: 1677568 +Results: + - Result: Test1 + Rule: BufferExact + Actual: buf + Expected: expected +DescriptorSets: + - Resources: + - Name: buf + Kind: RWStructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 +... +#--- end + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/MemExecModel/mem_conv_device.test b/test/MemExecModel/mem_conv_device.test new file mode 100644 index 00000000..ead63fe9 --- /dev/null +++ b/test/MemExecModel/mem_conv_device.test @@ -0,0 +1,61 @@ +#--- source.hlsl +RWStructuredBuffer write_val : register(u0); +RWStructuredBuffer buf : register(u1); + +[numthreads(256,1,1)] +void main(uint3 TID : SV_DispatchThreadID) { + uint tid = TID.x; + uint temp; + InterlockedExchange(write_val[0], tid, temp); + uint read_val = write_val[0]; + // Check if all threads in the wave read the same value + buf[tid] = uint(WaveActiveAllEqual(read_val)); +} +//--- pipeline.yaml +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [6553, 1, 1] +Buffers: + - Name: write_val + Format: UInt32 + Stride: 4 + Data: [0] + - Name: buf + Format: UInt32 + Stride: 4 + Fill: 0 + Size: 1677568 + - Name: expected + Format: UInt32 + Stride: 4 + Fill: 1 + Size: 1677568 +Results: + - Result: Test1 + Rule: BufferExact + Actual: buf + Expected: expected +DescriptorSets: + - Resources: + - Name: write_val + Kind: RWStructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 + - Name: buf + Kind: RWStructuredBuffer + DirectXBinding: + Register: 1 + Space: 0 + VulkanBinding: + Binding: 1 +... +#--- end + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o diff --git a/test/MemExecModel/mem_conv_group.test b/test/MemExecModel/mem_conv_group.test new file mode 100644 index 00000000..f47d5dda --- /dev/null +++ b/test/MemExecModel/mem_conv_group.test @@ -0,0 +1,52 @@ +#--- source.hlsl +RWStructuredBuffer buf : register(u0); +groupshared uint loc; + +[numthreads(256,1,1)] +void main(uint3 TID : SV_DispatchThreadID) { + uint temp; + loc = 0; + GroupMemoryBarrierWithGroupSync(); + uint tid = TID.x; + InterlockedExchange(loc, tid, temp); + uint read_val = loc; + // Check if all threads in the wave read the same value + buf[tid] = uint(WaveActiveAllEqual(read_val)); +} +//--- pipeline.yaml +--- +Shaders: + - Stage: Compute + Entry: main + DispatchSize: [6553, 1, 1] +Buffers: + - Name: buf + Format: UInt32 + Stride: 4 + Fill: 0 + Size: 1677568 + - Name: expected + Format: UInt32 + Stride: 4 + Fill: 1 + Size: 1677568 +Results: + - Result: Test1 + Rule: BufferExact + Actual: buf + Expected: expected +DescriptorSets: + - Resources: + - Name: buf + Kind: RWStructuredBuffer + DirectXBinding: + Register: 0 + Space: 0 + VulkanBinding: + Binding: 0 +... +#--- end + +# RUN: split-file %s %t +# RUN: %dxc_target -T cs_6_0 -Fo %t.o %t/source.hlsl +# RUN: %offloader %t/pipeline.yaml %t.o