diff --git a/test/WaveOps/WaveReadLaneFirst.fp16.test b/test/WaveOps/WaveReadLaneFirst.fp16.test
new file mode 100644
index 00000000..98559968
--- /dev/null
+++ b/test/WaveOps/WaveReadLaneFirst.fp16.test
@@ -0,0 +1,189 @@
+#--- source.hlsl
+StructuredBuffer<half4> In  : register(t0);
+RWStructuredBuffer<half4> Out1 : register(u1); // test scalar
+RWStructuredBuffer<half4> Out2 : register(u2); // test half2
+RWStructuredBuffer<half4> Out3 : register(u3); // test half3
+RWStructuredBuffer<half4> Out4 : register(u4); // test half4
+RWStructuredBuffer<half4> Out5 : register(u5); // constant folding
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    half4 v = In[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    half s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0;
+    half s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0;
+    half s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0;
+    half s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0;
+
+    half2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : half2(0,0);
+    half2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : half2(0,0);
+    half2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : half2(0,0);
+    half2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : half2(0,0);
+
+    half3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0);
+    half3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0);
+    half3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0);
+    half3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : half3(0,0,0);
+
+    half4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : half4(0,0,0,0);
+    half4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : half4(0,0,0,0);
+    half4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : half4(0,0,0,0);
+    half4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : half4(0,0,0,0);
+
+    half scalars[4] = { s4, s3, s2, s1 };
+    half2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 };
+    half3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 };
+    half4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 };  
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveReadLaneFirst(half4(1,2,3,4));    
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float16
+    Stride: 8
+    # 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000
+    Data: [ 0x3c00, 0x4900, 0x5640, 0x63d0, 0x4000, 0x4d00, 0x5a40, 0x67d0, 0x4200, 0x4f80, 0x5cb0, 0x69dc, 0x4400, 0x5100, 0x5e40, 0x6bd0 ]
+  - Name: Out1
+    Format: Float16
+    Stride: 8
+    ZeroInitSize: 32  
+  - Name: Out2
+    Format: Float16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: Out3
+    Format: Float16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: Out4
+    Format: Float16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: Out5
+    Format: Float16
+    Stride: 8
+    ZeroInitSize: 8
+  - Name: ExpectedOut1
+    Format: Float16
+    Stride: 8
+    # 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0
+    Data: [ 0x3c00, 0x0, 0x0, 0x0, 0x4000, 0x0, 0x0, 0x0, 0x4200, 0x0, 0x0, 0x0, 0x4400, 0x0, 0x0, 0x0 ]
+  - Name: ExpectedOut2
+    Format: Float16
+    Stride: 8
+    # 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0
+    Data: [ 0x3c00, 0x4900, 0x0, 0x0, 0x4000, 0x4d00, 0x0, 0x0, 0x4200, 0x4f80, 0x0, 0x0, 0x4400, 0x5100, 0x0, 0x0 ]
+  - Name: ExpectedOut3
+    Format: Float16
+    Stride: 8
+    # 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0
+    Data: [ 0x3c00, 0x4900, 0x5640, 0x0, 0x4000, 0x4d00, 0x5a40, 0x0, 0x4200, 0x4f80, 0x5cb0, 0x0, 0x4400, 0x5100, 0x5e40, 0x0 ]
+  - Name: ExpectedOut4
+    Format: Float16
+    Stride: 8
+    # 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000
+    Data: [ 0x3c00, 0x4900, 0x5640, 0x63d0, 0x4000, 0x4d00, 0x5a40, 0x67d0, 0x4200, 0x4f80, 0x5cb0, 0x69dc, 0x4400, 0x5100, 0x5e40, 0x6bd0 ]
+  - Name: ExpectedOut5
+    Format: Float16
+    Stride: 8
+    # 1, 2, 3, 4
+    Data: [ 0x3C00, 0x4000, 0x4200, 0x4400 ]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+...
+#--- end
+
+# REQUIRES: Half
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/433
+# XFAIL: DirectX-WARP
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveReadLaneFirst.fp32.test b/test/WaveOps/WaveReadLaneFirst.fp32.test
new file mode 100644
index 00000000..8d2c774a
--- /dev/null
+++ b/test/WaveOps/WaveReadLaneFirst.fp32.test
@@ -0,0 +1,179 @@
+#--- source.hlsl
+StructuredBuffer<float4> In  : register(t0);
+RWStructuredBuffer<float4> Out1 : register(u1); // test scalar
+RWStructuredBuffer<float4> Out2 : register(u2); // test float2
+RWStructuredBuffer<float4> Out3 : register(u3); // test float3
+RWStructuredBuffer<float4> Out4 : register(u4); // test float4
+RWStructuredBuffer<float4> Out5 : register(u5); // constant folding
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    float4 v = In[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    float s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0;
+    float s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0;
+    float s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0;
+    float s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0;
+
+    float2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : float2(0,0);
+    float2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : float2(0,0);
+    float2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : float2(0,0);
+    float2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : float2(0,0);
+
+    float3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0);
+    float3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0);
+    float3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0);
+    float3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : float3(0,0,0);
+
+    float4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : float4(0,0,0,0);
+    float4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : float4(0,0,0,0);
+    float4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : float4(0,0,0,0);
+    float4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : float4(0,0,0,0);
+
+    float scalars[4] = { s4, s3, s2, s1 };
+    float2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 };
+    float3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 };
+    float4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 };  
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveReadLaneFirst(float4(1,2,3,4));    
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float32
+    Stride: 16    
+    Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ]
+  - Name: Out1
+    Format: Float32
+    Stride: 16
+    ZeroInitSize: 64  
+  - Name: Out2
+    Format: Float32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: Out3
+    Format: Float32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: Out4
+    Format: Float32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: Out5
+    Format: Float32
+    Stride: 16
+    ZeroInitSize: 16
+  - Name: ExpectedOut1
+    Format: Float32
+    Stride: 16
+    Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ]
+  - Name: ExpectedOut2
+    Format: Float32
+    Stride: 16
+    Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ]
+  - Name: ExpectedOut3
+    Format: Float32
+    Stride: 16
+    Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ]
+  - Name: ExpectedOut4
+    Format: Float32
+    Stride: 16
+    Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ]
+  - Name: ExpectedOut5
+    Format: Float32
+    Stride: 16
+    Data: [ 1, 2, 3, 4 ] 
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+...
+#--- end
+
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveReadLaneFirst.fp64.test b/test/WaveOps/WaveReadLaneFirst.fp64.test
new file mode 100644
index 00000000..1129646d
--- /dev/null
+++ b/test/WaveOps/WaveReadLaneFirst.fp64.test
@@ -0,0 +1,183 @@
+#--- source.hlsl
+StructuredBuffer<double4> In  : register(t0);
+RWStructuredBuffer<double4> Out1 : register(u1); // test scalar
+RWStructuredBuffer<double4> Out2 : register(u2); // test double2
+RWStructuredBuffer<double4> Out3 : register(u3); // test double3
+RWStructuredBuffer<double4> Out4 : register(u4); // test double4
+RWStructuredBuffer<double4> Out5 : register(u5); // constant folding
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    double4 v = In[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    double s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0;
+    double s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0;
+    double s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0;
+    double s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0;
+
+    double2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : double2(0,0);
+    double2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : double2(0,0);
+    double2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : double2(0,0);
+    double2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : double2(0,0);
+
+    double3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0);
+    double3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0);
+    double3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0);
+    double3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : double3(0,0,0);
+
+    double4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : double4(0,0,0,0);
+    double4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : double4(0,0,0,0);
+    double4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : double4(0,0,0,0);
+    double4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : double4(0,0,0,0);
+
+    double scalars[4] = { s4, s3, s2, s1 };
+    double2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 };
+    double3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 };
+    double4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 };  
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveReadLaneFirst(double4(1,2,3,4));    
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Float64
+    Stride: 32    
+    Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ]
+  - Name: Out1
+    Format: Float64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out2
+    Format: Float64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out3
+    Format: Float64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out4
+    Format: Float64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out5
+    Format: Float64
+    Stride: 32
+    ZeroInitSize: 32
+  - Name: ExpectedOut1
+    Format: Float64
+    Stride: 32
+    Data: [ 1.0, 0.0, 0.0, 0.0, 2.0, 0.0, 0.0, 0.0, 3.0, 0.0, 0.0, 0.0, 4.0, 0.0, 0.0, 0.0 ]
+  - Name: ExpectedOut2
+    Format: Float64
+    Stride: 32
+    Data: [ 1.0, 10.0, 0.0, 0.0, 2.0, 20.0, 0.0, 0.0, 3.0, 30.0, 0.0, 0.0, 4.0, 40.0, 0.0, 0.0 ]
+  - Name: ExpectedOut3
+    Format: Float64
+    Stride: 32
+    Data: [ 1.0, 10.0, 100.0, 0.0, 2.0, 20.0, 200.0, 0.0, 3.0, 30.0, 300.0, 0.0, 4.0, 40.0, 400.0, 0.0 ]
+  - Name: ExpectedOut4
+    Format: Float64
+    Stride: 32
+    Data: [ 1.0, 10.0, 100.0, 1000.0, 2.0, 20.0, 200.0, 2000.0, 3.0, 30.0, 300.0, 3000.0, 4.0, 40.0, 400.0, 4000.0 ]
+  - Name: ExpectedOut5
+    Format: Float64
+    Stride: 32
+    Data: [ 1, 2, 3, 4 ] 
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+...
+#--- end
+
+# REQUIRES: Double
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/433
+# XFAIL: DirectX-WARP
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveReadLaneFirst.int16.test b/test/WaveOps/WaveReadLaneFirst.int16.test
new file mode 100644
index 00000000..e6f4725b
--- /dev/null
+++ b/test/WaveOps/WaveReadLaneFirst.int16.test
@@ -0,0 +1,331 @@
+#--- source.hlsl
+StructuredBuffer<int16_t4> In  : register(t0);
+RWStructuredBuffer<int16_t4> Out1 : register(u1); // test scalar
+RWStructuredBuffer<int16_t4> Out2 : register(u2); // test int16_t2
+RWStructuredBuffer<int16_t4> Out3 : register(u3); // test int16_t3
+RWStructuredBuffer<int16_t4> Out4 : register(u4); // test int16_t4
+RWStructuredBuffer<int16_t4> Out5 : register(u5); // constant folding
+
+// uint16_ts
+StructuredBuffer<uint16_t4> UIn  : register(t6);
+RWStructuredBuffer<uint16_t4> UOut1 : register(u7);
+RWStructuredBuffer<uint16_t4> UOut2 : register(u8);
+RWStructuredBuffer<uint16_t4> UOut3 : register(u9);
+RWStructuredBuffer<uint16_t4> UOut4 : register(u10);
+RWStructuredBuffer<uint16_t4> UOut5 : register(u11);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    int16_t4 v = In[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    int16_t s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0;
+    int16_t s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0;
+    int16_t s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0;
+    int16_t s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0;
+
+    int16_t2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0);
+    int16_t2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0);
+    int16_t2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0);
+    int16_t2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int16_t2(0,0);
+
+    int16_t3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0);
+    int16_t3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0);
+    int16_t3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0);
+    int16_t3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int16_t3(0,0,0);
+
+    int16_t4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0);
+    int16_t4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0);
+    int16_t4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0);
+    int16_t4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int16_t4(0,0,0,0);
+
+    int16_t scalars[4] = { s4, s3, s2, s1 };
+    int16_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 };
+    int16_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 };
+    int16_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 };  
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveReadLaneFirst(int16_t4(1,2,3,4));    
+
+    // UINT16_t case
+
+    uint16_t4 uv = UIn[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    uint16_t us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint16_t us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint16_t us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint16_t us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0;
+
+    uint16_t2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0);
+    uint16_t2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0);
+    uint16_t2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0);
+    uint16_t2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint16_t2(0,0);
+
+    uint16_t3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0);
+    uint16_t3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0);
+    uint16_t3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0);
+    uint16_t3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint16_t3(0,0,0);
+
+    uint16_t4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0);
+    uint16_t4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0);
+    uint16_t4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0);
+    uint16_t4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint16_t4(0,0,0,0);
+
+    uint16_t uscalars[4] = { us4, us3, us2, us1 };
+    uint16_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 };
+    uint16_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 };
+    uint16_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 };
+
+    UOut1[tid.x].x   = uscalars[tid.x];
+    UOut2[tid.x].xy  = uvec2s[tid.x];
+    UOut3[tid.x].xyz = uvec3s[tid.x];
+    UOut4[tid.x]     = uvec4s[tid.x];
+
+    // constant folding case
+    UOut5[0] = WaveReadLaneFirst(uint16_t4(1,2,3,4));
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int16
+    Stride: 8    
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: Out1
+    Format: Int16
+    Stride: 8
+    ZeroInitSize: 32  
+  - Name: Out2
+    Format: Int16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: Out3
+    Format: Int16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: Out4
+    Format: Int16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: Out5
+    Format: Int16
+    Stride: 8
+    ZeroInitSize: 8
+  - Name: ExpectedOut1
+    Format: Int16
+    Stride: 8
+    Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ]
+  - Name: ExpectedOut2
+    Format: Int16
+    Stride: 8
+    Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ]
+  - Name: ExpectedOut3
+    Format: Int16
+    Stride: 8
+    Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ]
+  - Name: ExpectedOut4
+    Format: Int16
+    Stride: 8
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: ExpectedOut5
+    Format: Int16
+    Stride: 8
+    Data: [ 1, 2, 3, 4 ]
+  - Name: UIn
+    Format: UInt16
+    Stride: 8    
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: UOut1
+    Format: UInt16
+    Stride: 8
+    ZeroInitSize: 32 
+  - Name: UOut2
+    Format: UInt16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: UOut3
+    Format: UInt16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: UOut4
+    Format: UInt16
+    Stride: 8
+    ZeroInitSize: 32
+  - Name: UOut5
+    Format: UInt16
+    Stride: 8
+    ZeroInitSize: 8
+  - Name: UExpectedOut1
+    Format: UInt16
+    Stride: 8
+    Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ]
+  - Name: UExpectedOut2
+    Format: UInt16
+    Stride: 8
+    Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ]
+  - Name: UExpectedOut3
+    Format: UInt16
+    Stride: 8
+    Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ]
+  - Name: UExpectedOut4
+    Format: UInt16
+    Stride: 8
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: UExpectedOut5
+    Format: UInt16
+    Stride: 8
+    Data: [ 1, 2, 3, 4 ]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: UExpectedOut1
+    Rule: BufferExact
+    Actual: UOut1
+    Expected: UExpectedOut1
+  - Result: UExpectedOut2
+    Rule: BufferExact
+    Actual: UOut2
+    Expected: UExpectedOut2
+  - Result: UExpectedOut3
+    Rule: BufferExact
+    Actual: UOut3
+    Expected: UExpectedOut3
+  - Result: UExpectedOut4
+    Rule: BufferExact
+    Actual: UOut4
+    Expected: UExpectedOut4
+  - Result: UExpectedOut5
+    Rule: BufferExact
+    Actual: UOut5
+    Expected: UExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UOut1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: UOut2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: UOut4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: UOut5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+
+...
+#--- end
+
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -enable-16bit-types -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveReadLaneFirst.int32.test b/test/WaveOps/WaveReadLaneFirst.int32.test
new file mode 100644
index 00000000..284ff82c
--- /dev/null
+++ b/test/WaveOps/WaveReadLaneFirst.int32.test
@@ -0,0 +1,331 @@
+#--- source.hlsl
+StructuredBuffer<int4> In  : register(t0);
+RWStructuredBuffer<int4> Out1 : register(u1); // test scalar
+RWStructuredBuffer<int4> Out2 : register(u2); // test int2
+RWStructuredBuffer<int4> Out3 : register(u3); // test int3
+RWStructuredBuffer<int4> Out4 : register(u4); // test int4
+RWStructuredBuffer<int4> Out5 : register(u5); // constant folding
+
+// uints
+StructuredBuffer<uint4> UIn  : register(t6);
+RWStructuredBuffer<uint4> UOut1 : register(u7);
+RWStructuredBuffer<uint4> UOut2 : register(u8);
+RWStructuredBuffer<uint4> UOut3 : register(u9);
+RWStructuredBuffer<uint4> UOut4 : register(u10);
+RWStructuredBuffer<uint4> UOut5 : register(u11);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    int4 v = In[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    int s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0;
+    int s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0;
+    int s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0;
+    int s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0;
+
+    int2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int2(0,0);
+    int2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int2(0,0);
+    int2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int2(0,0);
+    int2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int2(0,0);
+
+    int3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0);
+    int3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0);
+    int3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0);
+    int3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int3(0,0,0);
+
+    int4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int4(0,0,0,0);
+    int4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int4(0,0,0,0);
+    int4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int4(0,0,0,0);
+    int4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int4(0,0,0,0);
+
+    int scalars[4] = { s4, s3, s2, s1 };
+    int2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 };
+    int3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 };
+    int4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 };  
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveReadLaneFirst(int4(1,2,3,4));    
+
+    // UINT case
+
+    uint4 uv = UIn[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    uint us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0;
+
+    uint2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0);
+    uint2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0);
+    uint2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0);
+    uint2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint2(0,0);
+
+    uint3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0);
+    uint3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0);
+    uint3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0);
+    uint3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint3(0,0,0);
+
+    uint4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0);
+    uint4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0);
+    uint4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0);
+    uint4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint4(0,0,0,0);
+
+    uint uscalars[4] = { us4, us3, us2, us1 };
+    uint2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 };
+    uint3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 };
+    uint4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 };
+
+    UOut1[tid.x].x   = uscalars[tid.x];
+    UOut2[tid.x].xy  = uvec2s[tid.x];
+    UOut3[tid.x].xyz = uvec3s[tid.x];
+    UOut4[tid.x]     = uvec4s[tid.x];
+
+    // constant folding case
+    UOut5[0] = WaveReadLaneFirst(uint4(1,2,3,4));
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int32
+    Stride: 16    
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: Out1
+    Format: Int32
+    Stride: 16
+    ZeroInitSize: 64  
+  - Name: Out2
+    Format: Int32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: Out3
+    Format: Int32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: Out4
+    Format: Int32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: Out5
+    Format: Int32
+    Stride: 16
+    ZeroInitSize: 16
+  - Name: ExpectedOut1
+    Format: Int32
+    Stride: 16
+    Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ]
+  - Name: ExpectedOut2
+    Format: Int32
+    Stride: 16
+    Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ]
+  - Name: ExpectedOut3
+    Format: Int32
+    Stride: 16
+    Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ]
+  - Name: ExpectedOut4
+    Format: Int32
+    Stride: 16
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: ExpectedOut5
+    Format: Int32
+    Stride: 16
+    Data: [ 1, 2, 3, 4 ]
+  - Name: UIn
+    Format: UInt32
+    Stride: 16    
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: UOut1
+    Format: UInt32
+    Stride: 16
+    ZeroInitSize: 64 
+  - Name: UOut2
+    Format: UInt32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: UOut3
+    Format: UInt32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: UOut4
+    Format: UInt32
+    Stride: 16
+    ZeroInitSize: 64
+  - Name: UOut5
+    Format: UInt32
+    Stride: 16
+    ZeroInitSize: 16
+  - Name: UExpectedOut1
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ]
+  - Name: UExpectedOut2
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ]
+  - Name: UExpectedOut3
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ]
+  - Name: UExpectedOut4
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: UExpectedOut5
+    Format: UInt32
+    Stride: 16
+    Data: [ 1, 2, 3, 4 ]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: UExpectedOut1
+    Rule: BufferExact
+    Actual: UOut1
+    Expected: UExpectedOut1
+  - Result: UExpectedOut2
+    Rule: BufferExact
+    Actual: UOut2
+    Expected: UExpectedOut2
+  - Result: UExpectedOut3
+    Rule: BufferExact
+    Actual: UOut3
+    Expected: UExpectedOut3
+  - Result: UExpectedOut4
+    Rule: BufferExact
+    Actual: UOut4
+    Expected: UExpectedOut4
+  - Result: UExpectedOut5
+    Rule: BufferExact
+    Actual: UOut5
+    Expected: UExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UOut1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: UOut2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: UOut4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: UOut5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+
+...
+#--- end
+
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o 
diff --git a/test/WaveOps/WaveReadLaneFirst.int64.test b/test/WaveOps/WaveReadLaneFirst.int64.test
new file mode 100644
index 00000000..09c8bce5
--- /dev/null
+++ b/test/WaveOps/WaveReadLaneFirst.int64.test
@@ -0,0 +1,336 @@
+#--- source.hlsl
+StructuredBuffer<int64_t4> In  : register(t0);
+RWStructuredBuffer<int64_t4> Out1 : register(u1); // test scalar
+RWStructuredBuffer<int64_t4> Out2 : register(u2); // test int64_t2
+RWStructuredBuffer<int64_t4> Out3 : register(u3); // test int64_t3
+RWStructuredBuffer<int64_t4> Out4 : register(u4); // test int64_t4
+RWStructuredBuffer<int64_t4> Out5 : register(u5); // constant folding
+
+// uint64_ts
+StructuredBuffer<uint64_t4> UIn  : register(t6);
+RWStructuredBuffer<uint64_t4> UOut1 : register(u7);
+RWStructuredBuffer<uint64_t4> UOut2 : register(u8);
+RWStructuredBuffer<uint64_t4> UOut3 : register(u9);
+RWStructuredBuffer<uint64_t4> UOut4 : register(u10);
+RWStructuredBuffer<uint64_t4> UOut5 : register(u11);
+
+[numthreads(4,1,1)]
+void main(uint3 tid : SV_GroupThreadID)
+{
+    int64_t4 v = In[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    int64_t s1 = tid.x >= 3 ? WaveReadLaneFirst( v.x ) : 0;
+    int64_t s2 = tid.x >= 2 ? WaveReadLaneFirst( v.x ) : 0;
+    int64_t s3 = tid.x >= 1 ? WaveReadLaneFirst( v.x ) : 0;
+    int64_t s4 = tid.x >= 0 ? WaveReadLaneFirst( v.x ) : 0;
+
+    int64_t2 v2_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0);
+    int64_t2 v2_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0);
+    int64_t2 v2_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0);
+    int64_t2 v2_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xy ) : int64_t2(0,0);
+
+    int64_t3 v3_1 = tid.x >= 3 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0);
+    int64_t3 v3_2 = tid.x >= 2 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0);
+    int64_t3 v3_3 = tid.x >= 1 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0);
+    int64_t3 v3_4 = tid.x >= 0 ? WaveReadLaneFirst( v.xyz ) : int64_t3(0,0,0);
+
+    int64_t4 v4_1 = tid.x >= 3 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0);
+    int64_t4 v4_2 = tid.x >= 2 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0);
+    int64_t4 v4_3 = tid.x >= 1 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0);
+    int64_t4 v4_4 = tid.x >= 0 ? WaveReadLaneFirst( v ) : int64_t4(0,0,0,0);
+
+    int64_t scalars[4] = { s4, s3, s2, s1 };
+    int64_t2 vec2s [4] = { v2_4, v2_3, v2_2, v2_1 };
+    int64_t3 vec3s [4] = { v3_4, v3_3, v3_2, v3_1 };
+    int64_t4 vec4s [4] = { v4_4, v4_3, v4_2, v4_1 };  
+
+    Out1[tid.x].x   = scalars[tid.x];
+    Out2[tid.x].xy  = vec2s[tid.x];
+    Out3[tid.x].xyz = vec3s[tid.x];
+    Out4[tid.x]     = vec4s[tid.x];
+
+    // constant folding case
+    Out5[0] = WaveReadLaneFirst(int64_t4(1,2,3,4));    
+
+    // UINT64_t case
+
+    uint64_t4 uv = UIn[tid.x];
+
+    // Mask per "active lane set": only >= N lanes contribute
+    uint64_t us1 = tid.x >= 3 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint64_t us2 = tid.x >= 2 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint64_t us3 = tid.x >= 1 ? WaveReadLaneFirst( uv.x ) : 0;
+    uint64_t us4 = tid.x >= 0 ? WaveReadLaneFirst( uv.x ) : 0;
+
+    uint64_t2 uv2_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0);
+    uint64_t2 uv2_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0);
+    uint64_t2 uv2_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0);
+    uint64_t2 uv2_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xy ) : uint64_t2(0,0);
+
+    uint64_t3 uv3_1 = tid.x >= 3 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0);
+    uint64_t3 uv3_2 = tid.x >= 2 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0);
+    uint64_t3 uv3_3 = tid.x >= 1 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0);
+    uint64_t3 uv3_4 = tid.x >= 0 ? WaveReadLaneFirst( uv.xyz ) : uint64_t3(0,0,0);
+
+    uint64_t4 uv4_1 = tid.x >= 3 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0);
+    uint64_t4 uv4_2 = tid.x >= 2 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0);
+    uint64_t4 uv4_3 = tid.x >= 1 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0);
+    uint64_t4 uv4_4 = tid.x >= 0 ? WaveReadLaneFirst( uv ) : uint64_t4(0,0,0,0);
+
+    uint64_t uscalars[4] = { us4, us3, us2, us1 };
+    uint64_t2 uvec2s [4] = { uv2_4, uv2_3, uv2_2, uv2_1 };
+    uint64_t3 uvec3s [4] = { uv3_4, uv3_3, uv3_2, uv3_1 };
+    uint64_t4 uvec4s [4] = { uv4_4, uv4_3, uv4_2, uv4_1 };
+
+    UOut1[tid.x].x   = uscalars[tid.x];
+    UOut2[tid.x].xy  = uvec2s[tid.x];
+    UOut3[tid.x].xyz = uvec3s[tid.x];
+    UOut4[tid.x]     = uvec4s[tid.x];
+
+    // constant folding case
+    UOut5[0] = WaveReadLaneFirst(uint64_t4(1,2,3,4));
+}
+
+//--- pipeline.yaml
+
+---
+Shaders:
+  - Stage: Compute
+    Entry: main
+    DispatchSize: [1, 1, 1]
+Buffers:
+  - Name: In
+    Format: Int64
+    Stride: 32    
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: Out1
+    Format: Int64
+    Stride: 32
+    ZeroInitSize: 128  
+  - Name: Out2
+    Format: Int64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out3
+    Format: Int64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out4
+    Format: Int64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: Out5
+    Format: Int64
+    Stride: 32
+    ZeroInitSize: 32
+  - Name: ExpectedOut1
+    Format: Int64
+    Stride: 32
+    Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ]
+  - Name: ExpectedOut2
+    Format: Int64
+    Stride: 32
+    Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ]
+  - Name: ExpectedOut3
+    Format: Int64
+    Stride: 32
+    Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ]
+  - Name: ExpectedOut4
+    Format: Int64
+    Stride: 32
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: ExpectedOut5
+    Format: Int64
+    Stride: 32
+    Data: [ 1, 2, 3, 4 ]
+  - Name: UIn
+    Format: UInt64
+    Stride: 32    
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: UOut1
+    Format: UInt64
+    Stride: 32
+    ZeroInitSize: 128 
+  - Name: UOut2
+    Format: UInt64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: UOut3
+    Format: UInt64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: UOut4
+    Format: UInt64
+    Stride: 32
+    ZeroInitSize: 128
+  - Name: UOut5
+    Format: UInt64
+    Stride: 32
+    ZeroInitSize: 32
+  - Name: UExpectedOut1
+    Format: UInt64
+    Stride: 32
+    Data: [ 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 4, 0, 0, 0 ]
+  - Name: UExpectedOut2
+    Format: UInt64
+    Stride: 32
+    Data: [ 1, 10, 0, 0, 2, 20, 0, 0, 3, 30, 0, 0, 4, 40, 0, 0 ]
+  - Name: UExpectedOut3
+    Format: UInt64
+    Stride: 32
+    Data: [ 1, 10, 100, 0, 2, 20, 200, 0, 3, 30, 300, 0, 4, 40, 400, 0 ]
+  - Name: UExpectedOut4
+    Format: UInt64
+    Stride: 32
+    Data: [ 1, 10, 100, 1000, 2, 20, 200, 2000, 3, 30, 300, 3000, 4, 40, 400, 4000 ]
+  - Name: UExpectedOut5
+    Format: UInt64
+    Stride: 32
+    Data: [ 1, 2, 3, 4 ]
+Results:
+  - Result: ExpectedOut1
+    Rule: BufferExact
+    Actual: Out1
+    Expected: ExpectedOut1
+  - Result: ExpectedOut2
+    Rule: BufferExact
+    Actual: Out2
+    Expected: ExpectedOut2
+  - Result: ExpectedOut3
+    Rule: BufferExact
+    Actual: Out3
+    Expected: ExpectedOut3
+  - Result: ExpectedOut4
+    Rule: BufferExact
+    Actual: Out4
+    Expected: ExpectedOut4
+  - Result: ExpectedOut5
+    Rule: BufferExact
+    Actual: Out5
+    Expected: ExpectedOut5
+  - Result: UExpectedOut1
+    Rule: BufferExact
+    Actual: UOut1
+    Expected: UExpectedOut1
+  - Result: UExpectedOut2
+    Rule: BufferExact
+    Actual: UOut2
+    Expected: UExpectedOut2
+  - Result: UExpectedOut3
+    Rule: BufferExact
+    Actual: UOut3
+    Expected: UExpectedOut3
+  - Result: UExpectedOut4
+    Rule: BufferExact
+    Actual: UOut4
+    Expected: UExpectedOut4
+  - Result: UExpectedOut5
+    Rule: BufferExact
+    Actual: UOut5
+    Expected: UExpectedOut5
+DescriptorSets:
+  - Resources:
+    - Name: In
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 0
+        Space: 0
+      VulkanBinding:
+        Binding: 0
+    - Name: Out1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 1
+        Space: 0
+      VulkanBinding:
+        Binding: 1
+    - Name: Out2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 2
+        Space: 0
+      VulkanBinding:
+        Binding: 2
+    - Name: Out3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 3
+        Space: 0
+      VulkanBinding:
+        Binding: 3
+    - Name: Out4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 4
+        Space: 0
+      VulkanBinding:
+        Binding: 4
+    - Name: Out5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 5
+        Space: 0
+      VulkanBinding:
+        Binding: 5
+    - Name: UIn
+      Kind: StructuredBuffer
+      DirectXBinding:
+        Register: 6
+        Space: 0
+      VulkanBinding:
+        Binding: 6
+    - Name: UOut1
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 7
+        Space: 0
+      VulkanBinding:
+        Binding: 7
+    - Name: UOut2
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 8
+        Space: 0
+      VulkanBinding:
+        Binding: 8
+    - Name: UOut3
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 9
+        Space: 0
+      VulkanBinding:
+        Binding: 9
+    - Name: UOut4
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 10
+        Space: 0
+      VulkanBinding:
+        Binding: 10
+    - Name: UOut5
+      Kind: RWStructuredBuffer
+      DirectXBinding:
+        Register: 11
+        Space: 0
+      VulkanBinding:
+        Binding: 11
+
+...
+#--- end
+
+# REQUIRES: Int64
+
+# Bug https://github.com/llvm/offload-test-suite/issues/393
+# XFAIL: Metal
+
+# Bug https://github.com/llvm/llvm-project/issues/156775
+# XFAIL: Clang
+
+# Bug https://github.com/llvm/offload-test-suite/issues/433
+# XFAIL: DirectX-WARP
+
+
+# RUN: split-file %s %t
+# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
+# RUN: %offloader %t/pipeline.yaml %t.o