@@ -201,7 +201,7 @@ class X86AsmBackend : public MCAsmBackend {
201201 bool padInstructionEncoding (MCRelaxableFragment &RF, MCCodeEmitter &Emitter,
202202 unsigned &RemainingSize) const ;
203203
204- bool finishLayout (const MCAssembler &Asm) const override ;
204+ void finishLayout (const MCAssembler &Asm) const override ;
205205
206206 unsigned getMaximumNopSize (const MCSubtargetInfo &STI) const override ;
207207
@@ -856,15 +856,15 @@ bool X86AsmBackend::padInstructionEncoding(MCRelaxableFragment &RF,
856856 return Changed;
857857}
858858
859- bool X86AsmBackend::finishLayout (const MCAssembler &Asm) const {
859+ void X86AsmBackend::finishLayout (MCAssembler const &Asm) const {
860860 // See if we can further relax some instructions to cut down on the number of
861861 // nop bytes required for code alignment. The actual win is in reducing
862862 // instruction count, not number of bytes. Modern X86-64 can easily end up
863863 // decode limited. It is often better to reduce the number of instructions
864864 // (i.e. eliminate nops) even at the cost of increasing the size and
865865 // complexity of others.
866866 if (!X86PadForAlign && !X86PadForBranchAlign)
867- return false ;
867+ return ;
868868
869869 // The processed regions are delimitered by LabeledFragments. -g may have more
870870 // MCSymbols and therefore different relaxation results. X86PadForAlign is
@@ -911,6 +911,9 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
911911 continue ;
912912 }
913913
914+ #ifndef NDEBUG
915+ const uint64_t OrigOffset = Asm.getFragmentOffset (F);
916+ #endif
914917 const uint64_t OrigSize = Asm.computeFragmentSize (F);
915918
916919 // To keep the effects local, prefer to relax instructions closest to
@@ -923,7 +926,8 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
923926 // Give the backend a chance to play any tricks it wishes to increase
924927 // the encoding size of the given instruction. Target independent code
925928 // will try further relaxation, but target's may play further tricks.
926- padInstructionEncoding (RF, Asm.getEmitter (), RemainingSize);
929+ if (padInstructionEncoding (RF, Asm.getEmitter (), RemainingSize))
930+ Sec.setHasLayout (false );
927931
928932 // If we have an instruction which hasn't been fully relaxed, we can't
929933 // skip past it and insert bytes before it. Changing its starting
@@ -940,6 +944,14 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
940944 if (F.getKind () == MCFragment::FT_BoundaryAlign)
941945 cast<MCBoundaryAlignFragment>(F).setSize (RemainingSize);
942946
947+ #ifndef NDEBUG
948+ const uint64_t FinalOffset = Asm.getFragmentOffset (F);
949+ const uint64_t FinalSize = Asm.computeFragmentSize (F);
950+ assert (OrigOffset + OrigSize == FinalOffset + FinalSize &&
951+ " can't move start of next fragment!" );
952+ assert (FinalSize == RemainingSize && " inconsistent size computation?" );
953+ #endif
954+
943955 // If we're looking at a boundary align, make sure we don't try to pad
944956 // its target instructions for some following directive. Doing so would
945957 // break the alignment of the current boundary align.
@@ -953,7 +965,11 @@ bool X86AsmBackend::finishLayout(const MCAssembler &Asm) const {
953965 }
954966 }
955967
956- return true ;
968+ // The layout is done. Mark every fragment as valid.
969+ for (MCSection &Section : Asm) {
970+ Asm.getFragmentOffset (*Section.curFragList ()->Tail );
971+ Asm.computeFragmentSize (*Section.curFragList ()->Tail );
972+ }
957973}
958974
959975unsigned X86AsmBackend::getMaximumNopSize (const MCSubtargetInfo &STI) const {
0 commit comments