[RISCV] Fix typo in CV_SH_rr_inc pattern (llvm#120246)

This typo in
https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td#L701:L701
caused a compiler crash in 'RISC-V Assembly Printer' because
CV_SH_ri_inc was selected, leading to `getImmOpValue` being called for a
register operand.

This bug did not affect the Assembler output and therefore does not
trigger any existing unit tests, but is visible by examining the final
MIR function.

(cherry picked from commit e8ce6c4)

Author: PhilippvK

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

@@ -694,7 +694,7 @@ let Predicates = [HasVendorXCVmem, IsRV32], AddedComplexity = 1 in {
   def : CVStriPat<post_store, CV_SW_ri_inc>;
 
   def : CVStrriPat<post_truncsti8, CV_SB_rr_inc>;
-  def : CVStrriPat<post_truncsti16, CV_SH_ri_inc>;
+  def : CVStrriPat<post_truncsti16, CV_SH_rr_inc>;
   def : CVStrriPat<post_store, CV_SW_rr_inc>;
 
   def : CVStrrPat<truncstorei8, CV_SB_rr>;