Document wb_acq_core reserved bits that exposes debug information

Author: augustofg

modules/wishbone/wb_acq_core/wb_acq_core.vhd

@@ -443,29 +443,6 @@ architecture rtl of wb_acq_core is
   signal dbg_ddr_addr_cnt_axis              : std_logic_vector(30 downto 0);
   signal dbg_ddr_addr_init                  : std_logic_vector(30 downto 0);
   signal dbg_ddr_addr_max                   : std_logic_vector(30 downto 0);
-  ------------------------------------------------------------------------------
-  -- Components
-  ------------------------------------------------------------------------------
-
-  component acq_core_regs
-  port (
-    rst_n_i                                 : in     std_logic;
-    clk_sys_i                               : in     std_logic;
-    wb_adr_i                                : in     std_logic_vector(5 downto 0);
-    wb_dat_i                                : in     std_logic_vector(31 downto 0);
-    wb_dat_o                                : out    std_logic_vector(31 downto 0);
-    wb_cyc_i                                : in     std_logic;
-    wb_sel_i                                : in     std_logic_vector(3 downto 0);
-    wb_stb_i                                : in     std_logic;
-    wb_we_i                                 : in     std_logic;
-    wb_ack_o                                : out    std_logic;
-    wb_stall_o                              : out    std_logic;
-    fs_clk_i                                : in     std_logic;
-    ext_clk_i                               : in     std_logic;
-    regs_i                                  : in     t_acq_core_in_registers;
-    regs_o                                  : out    t_acq_core_out_registers
-  );
-  end component;
 
   function to_std_logic(arg : boolean) return std_logic is
   begin
@@ -542,6 +519,8 @@ begin
     wb_we_i                                 => wb_slv_adp_out.we,
     wb_ack_o                                => wb_slv_adp_in.ack,
     wb_stall_o                              => wb_slv_adp_in.stall,
+    wb_err_o                                => wb_slv_adp_in.err,
+    wb_rty_o                                => wb_slv_adp_in.rty,
     fs_clk_i                                => fs_clk_i,
     ext_clk_i                               => ext_clk_i,
     regs_i                                  => regs_in,
@@ -587,13 +566,23 @@ begin
 
   regs_in.sta_fsm_state_i                   <= acq_fsm_state;
   regs_in.sta_fsm_acq_done_i                <= acq_end;
-  regs_in.sta_reserved1_i                   <= dbg_fifo_rd_empty & dbg_fifo_fc_rd_en & dbg_fifo_re & dbg_fifo_we;
+
+  regs_in.sta_fifo_we_i                     <= dbg_fifo_we;
+  regs_in.sta_fifo_re_i                     <= dbg_fifo_re;
+  regs_in.sta_fifo_fc_rd_en_i               <= dbg_fifo_fc_rd_en;
+  regs_in.sta_fifo_rd_empty_i               <= dbg_fifo_rd_empty;
+
   regs_in.sta_fc_trans_done_i               <= fifo_fc_all_trans_done_l;
   regs_in.sta_fc_full_i                     <= fifo_sta_full;
-  regs_in.sta_reserved2_i                   <= "00" & dbg_source_pl_stall & dbg_source_pl_dreq &
-                                               dbg_fifo_fc_valid_fwft & dbg_fifo_wr_full;
+
+  regs_in.sta_fifo_wr_full_i                <= dbg_fifo_wr_full;
+  regs_in.sta_fifo_fc_valid_fwft_i          <= dbg_fifo_fc_valid_fwft;
+  regs_in.sta_source_pl_dreq_i              <= dbg_source_pl_dreq;
+  regs_in.sta_source_pl_stall_i             <= dbg_source_pl_stall;
+  regs_in.sta_reserved2_i                   <= "00";
+
   regs_in.sta_ddr3_trans_done_i             <= ddr3_all_trans_done_l;
-  regs_in.sta_reserved3_i                   <= f_gen_std_logic_vector(regs_in.sta_reserved3_i'length-
+  regs_in.sta_fifo_wr_count_i               <= f_gen_std_logic_vector(regs_in.sta_fifo_wr_count_i'length-
                                                 dbg_fifo_wr_count'length, '0') & dbg_fifo_wr_count;
   regs_in.trig_pos_i                        <= f_gen_std_logic_vector(regs_in.trig_pos_i'length-
                                                     ddr_trig_addr'length, '0') & ddr_trig_addr;

modules/wishbone/wb_acq_core/wbgen/acq_core.wb

@@ -102,11 +102,41 @@ peripheral {
     };
 
     field {
-      name = "Reserved";
-      description = "Ignore on read, write with 0's";
-      prefix = "reserved1";
+      name = "FIFO write enable";
+      description = "FIFO write enable, used for debug only";
+      prefix = "fifo_we";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "FIFO read enable";
+      description = "FIFO read enable, used for debug only";
+      prefix = "fifo_re";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "FIFO flow control read enable";
+      description = "FIFO flow control read enable, used for debug only";
+      prefix = "fifo_fc_rd_en";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "FIFO empty";
+      description = "FIFO empty, used for debug only";
+      prefix = "fifo_rd_empty";
       type = SLV;
-      size = 4;
+      size = 1;
       access_bus = READ_ONLY;
       access_dev = WRITE_ONLY;
     };
@@ -134,12 +164,52 @@ peripheral {
       access_dev = WRITE_ONLY;
     };
 
+    field {
+      name = "FIFO write full";
+      description = "FIFO write full, used for debug only";
+      prefix = "fifo_wr_full";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "FWFT FIFO valid output";
+      description = "FWFT FIFO valid output, used for debug only";
+      prefix = "fifo_fc_valid_fwft";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "Flow control data required";
+      description = "Flow control data required, used for debug only";
+      prefix = "source_pl_dreq";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
+    field {
+      name = "Flow control stall";
+      description = "Flow control stall, used for debug only";
+      prefix = "source_pl_stall";
+      type = SLV;
+      size = 1;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+
     field {
       name = "Reserved";
       description = "Ignore on read, write with 0's";
       prefix = "reserved2";
       type = SLV;
-      size = 6;
+      size = 2;
       access_bus = READ_ONLY;
       access_dev = WRITE_ONLY;
     };
@@ -157,9 +227,9 @@ peripheral {
     };
 
     field {
-      name = "Reserved";
-      description = "Ignore on read, write with 0's";
-      prefix = "reserved3";
+      name = "FIFO write count";
+      description = "FIFO write count, used for debugging only";
+      prefix = "fifo_wr_count";
       type = SLV;
       size = 15;
       access_bus = READ_ONLY;

modules/wishbone/wb_acq_core/wbgen/acq_core_regs.vhd

@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : acq_core_regs.vhd
 -- Author         : auto-generated by wbgen2 from acq_core.wb
--- Created        : Wed Nov  1 10:46:18 2017
+-- Created        : Tue Apr  4 13:59:43 2023
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE acq_core.wb
@@ -29,6 +29,8 @@ entity acq_core_regs is
     wb_stb_i                                 : in     std_logic;
     wb_we_i                                  : in     std_logic;
     wb_ack_o                                 : out    std_logic;
+    wb_err_o                                 : out    std_logic;
+    wb_rty_o                                 : out    std_logic;
     wb_stall_o                               : out    std_logic;
     fs_clk_i                                 : in     std_logic;
     ext_clk_i                                : in     std_logic;
@@ -183,13 +185,8 @@ signal allones                                  : std_logic_vector(31 downto 0);
 signal allzeros                                 : std_logic_vector(31 downto 0);
 
 begin
--- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+-- Some internal signals assignments
   wrdata_reg <= wb_dat_i;
-  bwsel_reg <= wb_sel_i;
-  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
-  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
-  allones <= (others => '1');
-  allzeros <= (others => '0');
 -- 
 -- Main register bank access process.
   process (clk_sys_i, rst_n_i)
@@ -342,12 +339,19 @@ begin
               acq_core_sta_fsm_state_lwb_in_progress <= '1';
             end if;
             rddata_reg(3) <= acq_core_sta_fsm_acq_done_sync1;
-            rddata_reg(7 downto 4) <= regs_i.sta_reserved1_i;
+            rddata_reg(4) <= regs_i.sta_fifo_we_i;
+            rddata_reg(5) <= regs_i.sta_fifo_re_i;
+            rddata_reg(6) <= regs_i.sta_fifo_fc_rd_en_i;
+            rddata_reg(7) <= regs_i.sta_fifo_rd_empty_i;
             rddata_reg(8) <= acq_core_sta_fc_trans_done_sync1;
             rddata_reg(9) <= acq_core_sta_fc_full_sync1;
-            rddata_reg(15 downto 10) <= regs_i.sta_reserved2_i;
+            rddata_reg(10) <= regs_i.sta_fifo_wr_full_i;
+            rddata_reg(11) <= regs_i.sta_fifo_fc_valid_fwft_i;
+            rddata_reg(12) <= regs_i.sta_source_pl_dreq_i;
+            rddata_reg(13) <= regs_i.sta_source_pl_stall_i;
+            rddata_reg(15 downto 14) <= regs_i.sta_reserved2_i;
             rddata_reg(16) <= acq_core_sta_ddr3_trans_done_sync1;
-            rddata_reg(31 downto 17) <= regs_i.sta_reserved3_i;
+            rddata_reg(31 downto 17) <= regs_i.sta_fifo_wr_count_i;
             ack_sreg(5) <= '1';
             ack_in_progress <= '1';
           when "000010" => 
@@ -961,7 +965,10 @@ begin
   end process;
 
 
--- Reserved
+-- FIFO write enable
+-- FIFO read enable
+-- FIFO flow control read enable
+-- FIFO empty
 -- External flow control transfer status
 -- synchronizer chain for field : External flow control transfer status (type RO/WO, fs_clk_i -> clk_sys_i)
   process (fs_clk_i, rst_n_i)
@@ -990,6 +997,10 @@ begin
   end process;
 
 
+-- FIFO write full
+-- FWFT FIFO valid output
+-- Flow control data required
+-- Flow control stall
 -- Reserved
 -- DDR3 transfer status
 -- synchronizer chain for field : DDR3 transfer status (type RO/WO, fs_clk_i -> clk_sys_i)
@@ -1005,7 +1016,7 @@ begin
   end process;
 
 
--- Reserved
+-- FIFO write count
 -- Hardware trigger selection
 -- synchronizer chain for field : Hardware trigger selection (type RW/RO, clk_sys_i <-> fs_clk_i)
   process (fs_clk_i, rst_n_i)
@@ -1070,8 +1081,8 @@ begin
   end process;
 
 
--- Channel selection for internal trigger
--- asynchronous std_logic_vector register : Channel selection for internal trigger (type RW/RO, fs_clk_i <-> clk_sys_i)
+-- Atom selection for internal trigger (atom within the channel selected by DTRIG_WHICH)
+-- asynchronous std_logic_vector register : Atom selection for internal trigger (atom within the channel selected by DTRIG_WHICH) (type RW/RO, fs_clk_i <-> clk_sys_i)
   process (fs_clk_i, rst_n_i)
   begin
     if (rst_n_i = '0') then 
@@ -1459,6 +1470,8 @@ begin
 -- Atom width
   rwaddr_reg <= wb_adr_i;
   wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+  wb_err_o <= '0';
+  wb_rty_o <= '0';
 -- ACK signal generation. Just pass the LSB of ACK counter.
   wb_ack_o <= ack_sreg(0);
 end syn;