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There are two oscillators on the board (external to the CPU) named OSC1 and OSC3.
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### OSC1
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This is a low-power 32768 Hz oscillator notably used for maintaining the real-time clock, but is also used elsewhere. There is no way to disable this oscillator outside of putting the system into [sleep](Standby.md#sleep) mode.
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This is a low-power 32.768 kHz crystal resonator (passive oscillator) notably used for maintaining the real-time clock, but is also used elsewhere. There is no way to disable this oscillator outside of putting the system into [sleep][] mode.
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This oscillator is labeled `Y1` on the circuit board but does not have any text visible on the component itself. It's not a surface-mount component.
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This oscillator is labeled `Y1` on the circuit board and it does have text but it may not be visible; it's an engraved text `KDS` followed by a number representing the final digit of the year it was printed in then a letter representing the month (A for January up to M for December). It's not a surface-mount component, but is glued down.
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In previous documentation and code, this oscillator was once known in the community as "oscillator 2".
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Things left to discover:
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* Part number
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* Accuracy
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* Confirm that it's crystal
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#### OSC1 specs
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* Part number: [DT-26](https://www.kds.info/product/dt-26/) ([datasheet](https://datasheet.lcsc.com/lcsc/1811121541_KDS-Daishinku-DT-26-32.768K-6pF-20PPM_C127496.pdf))
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* D - Daishinku Corp (company name)
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* T - Tuning fork crystal resonator
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* 2 - 2 mm diameter
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* 6 - 6 mm height
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* Load Capacitance: unconfirmed
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* Drive Level: 1.0μW (2.0μW max.)
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* Frequency Tolerance: ±20 ppm max. (at 25℃)
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* Series Resistance: unconfirmed
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* Turnover Temperature: +25℃±5℃
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* Parabolic Coefficient: -0.04 ppm/℃² max.
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* Operating Temperature Range: -10 to +60℃
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* Storage Temperature Range: -20 to +70℃
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* Shunt Capacitance: 1.1pF typ.
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* Aging: ±5 ppm/year
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### OSC3
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This is the high-speed 4.00 MHz ceramic oscillator used for the general purpose timers. It can be disabled by writing a 0 to the OSCC register and is also disabled when the system enters [sleep](Standby.md#sleep) mode.
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This is the high-speed 4.00 MHz ceramic resonator (passive oscillator) used for the general purpose timers. It can be disabled by writing a 0 to the OSCC register and is also disabled when the system enters [sleep][] mode.
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This oscillator is labeled `Y2` on the circuit board and has text printed on the top which looks like a curved M in a box followed by `4.00` and then a single-character serial such as `L` or `J`. It is a surface-mount component.
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@@ -40,7 +72,7 @@ When switching voltages you cannot jump directly between 1.6 V and 3.2 V safely
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In previous documentation and code, this oscillator was once known in the community as "oscillator 1".
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#### OSC3 Specs
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#### OSC3 specs
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These specs are unfortunately from the 2009 datasheet, when ideally we would like a 2001 datasheet.
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## Seconds Timer
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A timer which increments once every second. It uses OSC1 as its clock source.
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A timer which increments once every second. It uses [OSC1][] as its clock source.
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This timer informs the real-time clock (RTC) in commercial games. As such, if homebrew resets or pauses the timer or sleeps the console, it will force commercial games to ask for the user to enter the time again.
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This timer informs the real-time clock (RTC) in commercial games. As such, if homebrew resets or pauses the timer or sleeps the console (TODO?), it will force commercial games to ask for the user to enter the time again.
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* Write 0 to STRUN to pause this timer or 1 to start it.
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* When reading, 0 means paused and 1 means running.
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## Clock Timer
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A timer which increments 256 times per second. It uses OSC1 as its clock source.
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A timer which increments 256 times per second. It uses [OSC1][] as its clock source.
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* Write 0 to TMRUN to pause this timer or 1 to start it.
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* When reading, 0 means paused and 1 means running.
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In previous documentation and code, this timer was once known in the community as the "256Hz Timer".
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## General Purpose Timers
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## Programmable timers
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The Pokémon mini offers 3 pairs of general purpose programmable timers. Each set can independently be used either as a single 16-bit timer or split into two 8-bit channels with their own interrupts. These timers count down at a configurable rate.
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Each of the 6 8-bit timers can individually be configured to use either OSC1 or OSC3 as its source clock. When using a pair as a 16-bit timer, it uses the clock source of the first member of the pair (for example, PTM0) and the interupt of the second member (for example, PTM1).
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In previous documentation, these timers were known as the "general purpose timers", which is still an acceptable name, but this documentation will use "programmable timers" or PTs.
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### PTM0-1
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16-bit timer comprised of PTM0 as the lower order 8 bits and PTM1 as the higher order 8 bits. That is, `PTM1:PTM0` or given PTM1 is 0x10 and PTM0 is 0xf3, the value is 0x10f3.
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In previous documentation and code, this timer has been known in the community as the "timer 1".
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### PTM2-3
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16-bit timer comprised of PTM2 as the lower order 8 bits and PTM3 as the higher order 8 bits. That is, `PTM3:PTM2` or given PTM3 is 0x10 and PTM2 is 0xf3, the value is 0x10f3.
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In previous documentation and code, this timer has been known in the community as the "timer 2".
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### PTM4-5
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16-bit timer comprised of PTM4 as the lower order 8 bits and PTM5 as the higher order 8 bits. That is, `PTM5:PTM4` or given PTM5 is 0x10 and PTM4 is 0xf3, the value is 0x10f3.
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In previous documentation and code, this timer has been known in the community as the "timer 3".
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### Programmable timer configuration
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When choosing which timer to use for some purpose, you must choose whether to use some pair as a 16-bit timer or to split it and use one of the 8-bit timers. To use the 16-bit timer, write a 1 to the respective MODE16 register (see table below) and to use one of the 8-bit timers, write a 0 to it (this is the initial value).
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| Register | pm.h | Timer L | Timer H | Timer 16 |
To set MODE16 with pm.h, use, for example, `TMR1_CTRL_L |= 0x80;`
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To unset MODE16 with pm.h, use, for example, `TMR1_CTRL_L &= ~0x80;`
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TODO
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Before you first enable a timer, you'll want to configure its basic settings. Set the clock source via PRTF*x* where *x* is the timer index. Write a 1 to use [OSC1][] and a 0 to use [OSC3][]. You likely won't change this again unless you intend to repurpose the timer. To make this selection, refer the table below.
The Pokémon mini offers 3 general purpose timer units. Each timer is broken down into several blocks to provide it with variable clock rates, the ability to be broken down into two independent 8-bit timers, and each timer can generate two unique interrupts.
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After this you configure the division ratio (prescale), reload data (preset), and compare data (pivot). This can be changed regularly while the timer is running in order to adjust when some overflow occurs.
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## Timer Control
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The prescale along with the clock source determines how quickly the counter decrements. Refer to the table below:
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Each timer is configured using 6 registers, TIM_SCALE\*, TIM_OSCI\*, TIM_CTL\*_L, TIM_CTL\*_H, TIM_PRE\*_L and TIM_PRE\*_H. These registers provide the ability to change the clock rate of both the low and high 8-bits of the counter, set if there is a borrow chain to the upper 8-bits (16-bit counter mode) as well as enable and reset the timer (load counter from the preset). Beginning with the TIM_OSCI\*, each timer has the ability to run from oscillator 1 (System Clock) or oscillator 2 (32768 Hz RTC Clock). The pre-scale is further decided by selecting one of 8 different pre-scale values from a table in the TIM_SCALE\* register.
Further more, timers must be enabled individually (by setting the enable flag in TIM_SCALE\* TIM_CTL\*_L and TIM_CTL\*_H) as well as by group (Upper half of TIM_ENA_OSCI1). TIM_ENA_OSCI1 disables oscillator 1 or 2 if either respective bit is clear ($10 and $20).
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When a timer underflows, it loads the preset into the counter as the starting value to count down from. It can also be reset to this value manually by writing a 1 to PSET*x* where *x* is the timer index.
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**Timer Prescale (Oscillator 1)**
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| Prescale | Clk Div. | Hz |
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| -------- | ---------- | -------- |
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| 0 | CPU / 2 | 2000000 |
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| 1 | CPU / 8 | 500000 |
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| 2 | CPU / 32 | 125000 |
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| 3 | CPU / 64 | 62500 |
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| 4 | CPU / 128 | 31250 |
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| 5 | CPU / 256 | 15625 |
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| 6 | CPU / 1024 | 3906.25 |
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| 7 | CPU / 4096 | 976.5625 |
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When the pivot is matched, a compare match interrupt is triggered but the timer is not reset at that point. On matching PTM4-5 (TODO: or just PTM5?), an output signal is sent to the speaker.
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**Timer Prescale (Oscillator 2)**
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| Prescale | Clk Div. | Hz |
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| -------- | ----------- | ----- |
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| 0 | 32768 / 1 | 32768 |
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| 1 | 32768 / 2 | 16384 |
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| 2 | 32768 / 4 | 8192 |
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| 3 | 32768 / 8 | 4096 |
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| 4 | 32768 / 16 | 2048 |
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| 5 | 32768 / 32 | 1024 |
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| 6 | 32768 / 64 | 512 |
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| 7 | 32768 / 128 | 256 |
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The table below lists the timers and which registers control these three values. The use of a colon between two registers indicates the values are concatenated together such that `0x10:0xa5` would become `0x10a5`. The register using the timer's name (for example, PTM0) is the data register which contains the count value for reading; for the 16-bit timers this is `PTMy:PTMx` for any `PTMx-y`.
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The timer control registers affect the values of the timers themselves. Enable must be set for timing, this means there are a total of 3 bits that must be enabled for any timer to begin counting. writing a logical 1 to a reset bit in a control register will cause that respective 8-bit section to copy the respective value out of preset. All timers count down. When any timer underflows, it's value is copied from the preset value.
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| Timer | Prescale | Preset | Pivot |
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| ------ | -------- | --------- | --------- |
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| PTM0 | PST0 | RDR0 | CDR0 |
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| PTM1 | PST1 | RDR1 | CDR1 |
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| PTM2 | PST2 | RDR2 | CDR2 |
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| PTM3 | PST3 | RDR3 | CDR3 |
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| PTM4 | PST4 | RDR4 | CDR4 |
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| PTM5 | PST5 | RDR5 | CDR5 |
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| PTM0-1 | PST0 | RDR1:RDR0| CDR1:CDR0|
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| PTM2-3 | PST2 | RDR3:RDR2| CDR3:CDR2|
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| PTM4-5 | PST4 | RDR5:RDR4| CDR5:CDR4|
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## 16-bit mode
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With pm.h:
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When a timer is operating in 16-bit mode, all the upper-8 bit settings are unceremoniously ignored. Enables, reset and and everything no longer control the behavior of the timer. They remain writable, but they no longer actively function. This includes enables, resets and pre-scale values. The lower-8 bit configuration is effective over the full 16-bit value. Additionally, all lower-8 underflow IRQs are effectively disabled. The timer only presets when the full 16-bit value underflows.
The scale registers are constructed as `PRPRTy:PSTy:PRPRTx:PSTx` where each PST register is 3 bits and y = x + 1. This means that in order to set the prescale for PTM0 you must do `TMR1_SCALE &= ~0x07;` to clear then `TMR1_SCALE |= prescale;` to assign it. For PTM1 you must do `TMR1_SCALE &= ~0x70;` to clear then `TMR1_SCALE |= prescale << 4;` to assign it. They are initialized to 0 so there's no need to clear it in startup code. PRPRT registers should always be set to 1.
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Each timer provides two irqs. These IRQs appear to be fixed function, which provides the only known difference between Timers 1-2 and Timer 3.
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### Programmable timer interrupts
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Timers 1-3 have a primary IRQ, this fires anytime the upper 8-bit of the counter underflows (16- or 8-bit operations) The secondary IRQ of Timer 1-2 occurs when the lower 8-bit counter underflows (8-bit mode only) The secondary IRQ of Timer 3 occurs when the value of the counter becomes less than or equal-to the value in it's comparator. In 8-bit mode only the upper 8-bit of the value is used.
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There are two interrupts for each timer: the underflow and the compare data interrupts. Underflow occurs the tick after a count reaches 0, causing it to preset. The compare data interrupt occurs when the count is equalto the value stored in the relevant CDR register.
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## Sound
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Although all of these interrupts exist and can be accessed by reading the count or factor flag directely, not all of them are mapped to ROM locations (that is, there's no means to make them jump to software code automatically).
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Timer 3 is also used for [sound](PM_Audio.md"wikilink") within the Pokémon mini.
For more information about how interrupts work, see [Interrupts](cpu/Interrupts.md).
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For information on using PTM4-5 for audio, see [Audio / Sound](cpu/Sound.md).
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### Enabling and pausing programmable timers
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In order to turn a timer on, the following must be done, where x is some timer index (use 0 for PTM0-1, etc):
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* CKSEL*x* should already be set to 0 by default, do not change it
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* Set PRPRT*x* register to 1
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* Set PTRUN*x* register to 1
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To pause the timer, reset PTRUN*x* register to 0. The timer will decrement once more before pausing.
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To resume the timer, set PTRUN*x* register back to 1.
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To preset the timer count, write 1 to PSET*x*.
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When using the HALT operation, the timers are not paused. When using the SLP operation, the timers will be paused and will resume from where they left off when the console reawakens.
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