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‎Timers.md‎

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## Timer Overview
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The Pokémon mini offers 3 general purpose timer units. Each timer is broken down into several blocks to provide it with variable clock rates, the ability to be broken down into two independent 8-bit timers, and each timer can generate two unique interrupts.
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## Timer Control
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Each timer is configured using 6 registers, TIM_SCALE\*, TIM_OSCI\*, TIM_CTL\*_L, TIM_CTL\*_H, TIM_PRE\*_L and TIM_PRE\*_H. These registers provide the ability to change the clock rate of both the low and high 8-bits of the counter, set if there is a borrow chain to the upper 8-bits (16-bit counter mode) as well as enable and reset the timer (load counter from the preset). Beginning with the TIM_OSCI\*, each timer has the ability to run from oscillator 1 (System Clock) or oscillator 2 (32768 Hz RTC Clock). The pre-scale is further decided by selecting one of 8 different pre-scale values from a table in the TIM_SCALE\* register.
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Further more, timers must be enabled individually (by setting the enable flag in TIM_SCALE\* TIM_CTL\*_L and TIM_CTL\*_H) as well as by group (Upper half of TIM_ENA_OSCI1). TIM_ENA_OSCI1 disables oscillator 1 or 2 if either respective bit is clear ($10 and $20).
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**Timer Prescale (Oscillator 1)**
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| Prescale | Clk Div. | Hz |
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| -------- | ---------- | -------- |
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| 0 | CPU / 2 | 2000000 |
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| 1 | CPU / 8 | 500000 |
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| 2 | CPU / 32 | 125000 |
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| 3 | CPU / 64 | 62500 |
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| 4 | CPU / 128 | 31250 |
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| 5 | CPU / 256 | 15625 |
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| 6 | CPU / 1024 | 3906.25 |
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| 7 | CPU / 4096 | 976.5625 |
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**Timer Prescale (Oscillator 2)**
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| Prescale | Clk Div. | Hz |
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| -------- | ----------- | ----- |
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| 0 | 32768 / 1 | 32768 |
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| 1 | 32768 / 2 | 16384 |
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| 2 | 32768 / 4 | 8192 |
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| 3 | 32768 / 8 | 4096 |
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| 4 | 32768 / 16 | 2048 |
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| 5 | 32768 / 32 | 1024 |
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| 6 | 32768 / 64 | 512 |
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| 7 | 32768 / 128 | 256 |
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The timer control registers affect the values of the timers themselves. Enable must be set for timing, this means there are a total of 3 bits that must be enabled for any timer to begin counting. writing a logical 1 to a reset bit in a control register will cause that respective 8-bit section to copy the respective value out of preset. All timers count down. When any timer underflows, it's value is copied from the preset value.
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## 16-bit mode
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When a timer is operating in 16-bit mode, all the upper-8 bit settings are unceremoniously ignored. Enables, reset and and everything no longer control the behavior of the timer. They remain writable, but they no longer actively function. This includes enables, resets and pre-scale values. The lower-8 bit configuration is effective over the full 16-bit value. Additionally, all lower-8 underflow IRQs are effectively disabled. The timer only presets when the full 16-bit value underflows.
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## IRQ Operation
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Each timer provides two irqs. These IRQs appear to be fixed function, which provides the only known difference between Timers 1-2 and Timer 3.
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Timers 1-3 have a primary IRQ, this fires anytime the upper 8-bit of the counter underflows (16- or 8-bit operations) The secondary IRQ of Timer 1-2 occurs when the lower 8-bit counter underflows (8-bit mode only) The secondary IRQ of Timer 3 occurs when the value of the counter becomes less than or equal-to the value in it's comparator. In 8-bit mode only the upper 8-bit of the value is used.
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## Sound
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Timer 3 is also used for [sound](PM_Audio.md "wikilink") within the Pokémon mini.
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# Timers & Oscillators
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- [Seconds Timer](#seconds-timer)
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- [Clock Timer](#clock-timer)
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- [General Purpose Timers](#general-purpose-timers)
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## Oscillators
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There are two oscillators on the board (external to the CPU) named OSC1 and OSC3.
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### OSC1
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This is a low-power 32768 Hz oscillator notably used for maintaining the real-time clock, but is also used elsewhere. There is no way to disable this oscillator outside of putting the system into [sleep](Standby.md#sleep) mode.
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This oscillator is labeled `Y1` on the circuit board but does not have any text visible on the component itself. It's not a surface-mount component.
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In previous documentation and code, this oscillator was once known in the community as "oscillator 2".
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Things left to discover:
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* Part number
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* Accuracy
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* Confirm that it's crystal
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### OSC3
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This is the high-speed 4.00 MHz ceramic oscillator used for the general purpose timers. It can be disabled by writing a 0 to the OSCC register and is also disabled when the system enters [sleep](Standby.md#sleep) mode.
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This oscillator is labeled `Y2` on the circuit board and has text printed on the top which looks like a curved M in a box followed by `4.00` and then a single-character serial such as `L` or `J`. It is a surface-mount component.
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Disabling this oscillator when not needed can save power. You can also adjust the speed this runs at by writing to register VD1C according to the following table:
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| VD1C1 | VD1C0 | Operating voltage | Oscillation |
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|:-----:|:-----:| ----------------- | ------------------ |
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| 1 | 1/0 | 3.2 V | 0.03~8.2 MHz |
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| 0 | 1 | 1.6 V | 0.03~1.1 MHz / off |
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| 0 | 0 | 2.4 V | 0.03~4.4 MHz |
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When switching voltages you cannot jump directly between 1.6 V and 3.2 V safely and you must wait some time after switching. See the VD1C register details for usage information. Note that the BIOS will switch between 1.6 V and 2.4 V during some operations.
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In previous documentation and code, this oscillator was once known in the community as "oscillator 1".
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#### OSC3 Specs
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These specs are unfortunately from the 2009 datasheet, when ideally we would like a 2001 datasheet.
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* Part number: [EFOS4004E5](https://www.digikey.com/en/products/detail/panasonic-electronic-components/EFO-S4004E5/160457) ([datasheet](https://media.digikey.com/pdf/Data%20Sheets/Panasonic%20Capacitors%20PDFs/EFO_3Array.pdf))
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* EFO - Ceramic resonator
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* S - 2 to 13 MHz type with built-in capacitors and 3 terminals
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* 4004 - 4.00 MHz nominal oscillation frequency
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* E - Embossed taping style packaging
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* 5 - ±0.5% frequency tolerance
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* Built-in Capacitors: 33 pF
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* Oscillation frequency drift: ±0.2% overall stability
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* -20°C ≈ -0.1
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* 20°C ≈ 0.0
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* 40°C ≈ 0.02
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* 60°C ≈ 0.0
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* 80°C ≈ -0.04
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## Seconds Timer
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A timer which increments once every second. It uses OSC1 as its clock source.
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This timer informs the real-time clock (RTC) in commercial games. As such, if homebrew resets or pauses the timer or sleeps the console, it will force commercial games to ask for the user to enter the time again.
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* Write 0 to STRUN to pause this timer or 1 to start it.
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* When reading, 0 means paused and 1 means running.
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* In pm.h, STRST is bit 0 of SEC_CTRL
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* Write 1 to STRST to reset this timer.
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* In pm.h, STRST is bit 1 of SEC_CTRL
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* Read the count from the STD register
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* In pm.h, STD is called SEC_CNT
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There are no interrupts related to this timer.
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## Clock Timer
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A timer which increments 256 times per second. It uses OSC1 as its clock source.
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* Write 0 to TMRUN to pause this timer or 1 to start it.
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* When reading, 0 means paused and 1 means running.
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* In pm.h, TMRUN is bit 0 of TMR256_CTRL
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* Write 1 to TMRST to reset this timer.
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* In pm.h, TMRST is bit 1 of TMR256_CTRL
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* Read the count from the TMD register
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* The individual bits decompose into different counts for different Hz. That is, each bit increments at a different Hz by nature of the whole byte incrementing 256 times per second.
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* TMD7 - overflows every 1 Hz, increments every 2 Hz
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* TMD6 - overflows every 2 Hz, increments every 4 Hz
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* TMD5 - overflows every 4 Hz, increments every 8 Hz
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* TMD4 - overflows every 8 Hz, increments every 16 Hz
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* TMD3 - overflows every 16 Hz, increments every 32 Hz
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* TMD2 - overflows every 32 Hz, increments every 64 Hz
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* TMD1 - overflows every 64 Hz, increments every 128 Hz
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* TMD0 - overflows every 128 Hz, increments every 256 Hz
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* In pm.h, TMD is called TMR256_CNT
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There are four interrupts tripped by this timer at different Hz.
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* Clock timer 1 Hz interrupt
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* Triggers every second, when TMD7 overflows.
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* Write 1 to ECTM1 to enable, 0 to disable.
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* When reading, 1 means enabled and 0 means disabled.
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* With pm.h, use `IRQ_ENA2 |= IRQ2_1HZ;` to enable, `IRQ_ENA2 &= ~IRQ2_1HZ;` to disable.
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* Write 1 to FCTM1 to reset the activation.
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* When reading, 1 means the interrupt is active (ready to trigger), 0 otherwise.
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* With pm.h, use `IRQ_ACT2 |= IRQ2_1HZ;` to reset, use `IRQ_ACT2 & IRQ2_1HZ` as a boolean to read.
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* Clock timer 2 Hz interrupt
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* Triggers every 500 ms, when TMD6 overflows.
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* Registers are: ECTM2, FCTM2, and IRQ2_2HZ in pm.h
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* Clock timer 8 Hz interrupt
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* Triggers every 125 ms, when TMD4 overflows.
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* Registers are: ECTM8, FCTM8, and IRQ2_8HZ in pm.h
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* Clock timer 32 Hz interrupt
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* Triggers every 31250 µs, when TMD2 overflows.
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* Registers are: ECTM32, FCTM32, and IRQ2_32HZ in pm.h
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* Write to PCTM to set the priority for all clock timer interrupts.
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* You can read out the current priority as well.
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* With pm.h, use `IRQ_PRI2 &= ~PRI2_TIM256(3);` to clear it then `IRQ_PRI2 |= PRI2_TIM256(x);` to set the new priority, where x can be 0-3 (0 = disabled).
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* When setting priorities in initial setup, you don't need to clear anything and can instead use `IRQ_PRI2 = PRI2_TIM256(x) | ...;` where `...` is anything else that needs to be set in IRQ_PRI2.
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In previous documentation and code, this timer was once known in the community as the "256Hz Timer".
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## General Purpose Timers
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TODO
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## Timer Overview
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The Pokémon mini offers 3 general purpose timer units. Each timer is broken down into several blocks to provide it with variable clock rates, the ability to be broken down into two independent 8-bit timers, and each timer can generate two unique interrupts.
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## Timer Control
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Each timer is configured using 6 registers, TIM_SCALE\*, TIM_OSCI\*, TIM_CTL\*_L, TIM_CTL\*_H, TIM_PRE\*_L and TIM_PRE\*_H. These registers provide the ability to change the clock rate of both the low and high 8-bits of the counter, set if there is a borrow chain to the upper 8-bits (16-bit counter mode) as well as enable and reset the timer (load counter from the preset). Beginning with the TIM_OSCI\*, each timer has the ability to run from oscillator 1 (System Clock) or oscillator 2 (32768 Hz RTC Clock). The pre-scale is further decided by selecting one of 8 different pre-scale values from a table in the TIM_SCALE\* register.
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Further more, timers must be enabled individually (by setting the enable flag in TIM_SCALE\* TIM_CTL\*_L and TIM_CTL\*_H) as well as by group (Upper half of TIM_ENA_OSCI1). TIM_ENA_OSCI1 disables oscillator 1 or 2 if either respective bit is clear ($10 and $20).
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**Timer Prescale (Oscillator 1)**
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| Prescale | Clk Div. | Hz |
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| -------- | ---------- | -------- |
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| 0 | CPU / 2 | 2000000 |
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| 1 | CPU / 8 | 500000 |
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| 2 | CPU / 32 | 125000 |
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| 3 | CPU / 64 | 62500 |
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| 4 | CPU / 128 | 31250 |
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| 5 | CPU / 256 | 15625 |
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| 6 | CPU / 1024 | 3906.25 |
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| 7 | CPU / 4096 | 976.5625 |
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**Timer Prescale (Oscillator 2)**
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| Prescale | Clk Div. | Hz |
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| -------- | ----------- | ----- |
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| 0 | 32768 / 1 | 32768 |
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| 1 | 32768 / 2 | 16384 |
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| 2 | 32768 / 4 | 8192 |
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| 3 | 32768 / 8 | 4096 |
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| 4 | 32768 / 16 | 2048 |
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| 5 | 32768 / 32 | 1024 |
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| 6 | 32768 / 64 | 512 |
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| 7 | 32768 / 128 | 256 |
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The timer control registers affect the values of the timers themselves. Enable must be set for timing, this means there are a total of 3 bits that must be enabled for any timer to begin counting. writing a logical 1 to a reset bit in a control register will cause that respective 8-bit section to copy the respective value out of preset. All timers count down. When any timer underflows, it's value is copied from the preset value.
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## 16-bit mode
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When a timer is operating in 16-bit mode, all the upper-8 bit settings are unceremoniously ignored. Enables, reset and and everything no longer control the behavior of the timer. They remain writable, but they no longer actively function. This includes enables, resets and pre-scale values. The lower-8 bit configuration is effective over the full 16-bit value. Additionally, all lower-8 underflow IRQs are effectively disabled. The timer only presets when the full 16-bit value underflows.
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## IRQ Operation
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Each timer provides two irqs. These IRQs appear to be fixed function, which provides the only known difference between Timers 1-2 and Timer 3.
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Timers 1-3 have a primary IRQ, this fires anytime the upper 8-bit of the counter underflows (16- or 8-bit operations) The secondary IRQ of Timer 1-2 occurs when the lower 8-bit counter underflows (8-bit mode only) The secondary IRQ of Timer 3 occurs when the value of the counter becomes less than or equal-to the value in it's comparator. In 8-bit mode only the upper 8-bit of the value is used.
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## Sound
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Timer 3 is also used for [sound](PM_Audio.md "wikilink") within the Pokémon mini.

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