Fix linting errors pointed by ruff

Signed-off-by: Douglas Reis <doreis@lowrisc.org>

Author: engdoreis

pyproject.toml

@@ -36,8 +36,8 @@ select = ["ALL"]
 extend-select = ["W391", "E303"]
 allowed-confusables = ["−"]
 ignore = [
-    "D203", "D213", "COM812", "ISC001",
-    "FIX", "TD",
+    "D203", "D213", "COM812", "ISC001", "FIX", "TD", "T201", "S101", "C901", "D401",
+    "PLR0911", "PLR0915", "INP001", "RUF012", "EXE001", "S701"
 ]
 
 [tool.uv.workspace]

rdl2ot/src/rdl2ot/__init__.py

@@ -1,3 +1,5 @@
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
+
+"""Init."""

rdl2ot/src/rdl2ot/__main__.py

@@ -2,6 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Main."""
+
 from cli import main
 
 if __name__ == "__main__":

rdl2ot/src/rdl2ot/cli.py

@@ -3,43 +3,50 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+
+"""Cli."""
+
 from pathlib import Path
 
 import click
+import export_rtl as rtl_exporter
+from systemrdl import RDLCompiler
 
 
 @click.group()
-def main():
-    pass
+def main() -> None:
+    """Cli."""
 
 
 @main.command()
 @click.argument(
     "input_file",
     type=click.Path(writable=True),
-    # help="The input RDL.",
 )
 @click.argument(
     "out_dir",
     default="./result",
     type=click.Path(writable=True),
-    # help="The destination dir to generate the output.",
 )
-def export_rtl(input_file: str, out_dir: str):
-    from systemrdl import RDLCompiler
+def export_rtl(input_file: str, out_dir: str) -> None:
+    """Export opentitan rtl.
 
+    INPUT_FILE: The input RDL
+    HELP: The destination dir to generate the output
+
+    """
     rdlc = RDLCompiler()
     try:
         rdlc.compile_file(input_file)
         root = rdlc.elaborate()
     except Exception as e:
-        raise RuntimeError(f"In file {input_file}") from e
-
-    import export_rtl
+        error_msg = f"In file {input_file}"
+        raise RuntimeError(error_msg) from e
 
     try:
-        export_rtl.run(rdlc, root, Path(out_dir))
+        rtl_exporter.run(rdlc, root, Path(out_dir))
     except Exception as e:
-        raise RuntimeError(f"In file {input_file}") from e
+        error_msg = f"In file {input_file}"
+        raise RuntimeError(error_msg) from e
 
     print("Successfully finished!\n")

rdl2ot/src/rdl2ot/export_rtl.py

@@ -2,6 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Export RDL to opentitan RTL."""
+
 import json
 from pathlib import Path
 
@@ -14,18 +16,18 @@
 DEFAULT_INTERFACE_NAME = "regs"
 
 
-def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path):
+def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path) -> None:
+    """Export RDL to opentitan RTL."""
     factory = OtInterfaceBuilder(rdlc)
     data = factory.parse_root(obj.top)
-    with open("/tmp/reg.json", "w", encoding="utf-8") as f:
+    with (out_dir / "rdl.json").open("w", encoding="utf-8") as f:
         json.dump(data, f, indent=2)
 
     file_loader = FileSystemLoader(TEMPLATES_DIR)
     env = Environment(loader=file_loader)
 
     ip_name = data["ip_name"]
     reg_pkg_tpl = env.get_template("reg_pkg.sv.tpl")
-    # stream = reg_pkg_tpl.stream(data)
     stream = reg_pkg_tpl.render(data)
     path = out_dir / f"{ip_name}_reg_pkg.sv"
     path.open("w").write(stream)
@@ -35,14 +37,15 @@ def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path):
     for interface in data["interfaces"]:
         name = "_{}".format(interface["name"].lower()) if "name" in interface else ""
         data_ = {"ip_name": ip_name, "interface": interface}
-        # stream = reg_top_tpl.stream(data_)
         stream = reg_top_tpl.render(data_).replace(" \n", "\n")
         path = out_dir / f"{ip_name}{name}_reg_top.sv"
         path.open("w").write(stream)
         print(f"Generated {path}.")
 
 
 class OtInterfaceBuilder:
+    """Opentitan Interface Builder."""
+
     num_regs: int = 0  # The number of registers of an interface
     num_windows: int = 0  # The number of registers of an interface
     any_async_clk: bool = False  # Whether is there any register with async clock in the interface
@@ -52,13 +55,13 @@ class OtInterfaceBuilder:
     reg_index: int = 0
     rdlc: RDLCompiler
 
-    def __init__(self, rdlc: RDLCompiler):
+    def __init__(self, rdlc: RDLCompiler) -> None:
+        """Constructor."""
         self.rdlc = rdlc
 
     def get_field(self, field: node.FieldNode) -> dict:
-        """Parse a field and return a dictionary.
-        """
-        obj = dict()
+        """Parse a field and return a dictionary."""
+        obj = {}
         obj["name"] = field.inst_name
         obj["type"] = "field"
         obj["desc"] = field.get_property("desc", default="")
@@ -91,9 +94,8 @@ def get_field(self, field: node.FieldNode) -> dict:
         return obj
 
     def get_mem(self, mem: node.FieldNode) -> dict:
-        """Parse a memory and return a dictionary representing a window.
-        """
-        obj = dict()
+        """Parse a memory and return a dictionary representing a window."""
+        obj = {}
         obj["name"] = mem.inst_name
         obj["entries"] = mem.get_property("mementries")
         obj["sw_writable"] = mem.is_sw_writable
@@ -107,9 +109,8 @@ def get_mem(self, mem: node.FieldNode) -> dict:
         return obj
 
     def get_reg(self, reg: node.RegNode) -> dict:
-        """Parse a register and return a dictionary.
-        """
-        obj = dict()
+        """Parse a register and return a dictionary."""
+        obj = {}
         obj["name"] = reg.inst_name
         obj["type"] = "reg"
         obj["width"] = reg.get_property("regwidth")
@@ -140,8 +141,8 @@ def get_reg(self, reg: node.RegNode) -> dict:
         msb = 0
         reset_val = 0
         bitmask = 0
-        for field in reg.fields():
-            field = self.get_field(field)
+        for f in reg.fields():
+            field = self.get_field(f)
             obj["fields"].append(field)
             sw_write_en |= field["sw_write_en"]
             msb = max(msb, field["msb"])
@@ -175,17 +176,14 @@ def get_reg(self, reg: node.RegNode) -> dict:
         return obj
 
     def get_paramesters(self, obj: node.AddrmapNode | node.RegfileNode) -> [dict]:
-        """Parse the custom property localparams and return a list of  dictionaries.
-        """
-        res = [
+        """Parse the custom property localparams and return a list of  dictionaries."""
+        return [
             {"name": param.name, "type": "int", "value": param.get_value()}
             for param in obj.inst.parameters
         ]
-        return res
 
     def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = None) -> dict:
-        """Parse an interface and return a dictionary.
-        """
+        """Parse an interface and return a dictionary."""
         self.num_regs = 0
         self.num_windows = 0
         self.any_async_clk = False
@@ -196,7 +194,7 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
         if addrmap.is_array:
             print(f"WARNING: Unsupported array type: {type(addrmap)}, skiping...")
 
-        interface = dict()
+        interface = {}
         if defalt_name:
             interface["name"] = addrmap.inst_name or defalt_name
 
@@ -233,21 +231,20 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
         interface["all_async_clk"] = self.all_async_clk
         interface["any_shadowed_reg"] = self.any_shadowed_reg
         interface["any_integrity_bypass"] = any(
-            [win["integrity_bypass"] for win in interface["windows"]]
+            win["integrity_bypass"] for win in interface["windows"]
         )
         return interface
 
     def parse_root(self, root: node.AddrmapNode) -> dict:
-        """Parse the root node and return a dictionary representing a window.
-        """
+        """Parse the root node and return a dictionary representing a window."""
         if root.is_array:
             print("Error: Unsupported array type on the top")
             raise RuntimeError
         if not isinstance(root, node.AddrmapNode):
             print("Error: Top level must be an addrmap")
-            raise RuntimeError
+            raise TypeError
 
-        obj = dict()
+        obj = {}
         params = self.get_paramesters(root)
         if params:
             obj["parameters"] = params
@@ -263,10 +260,10 @@ def parse_root(self, root: node.AddrmapNode) -> dict:
                 continue
             else:
                 print(
-                    f"""Error: Unsupported type: {type(child)}, top level only supports 
+                    f"""Error: Unsupported type: {type(child)}, top level only supports
                       addrmap and reg components."""
                 )
-                raise RuntimeError
+                raise TypeError
 
         # If the root contain imediate registers, use a default interface name
         if len(root.registers()) > 0:

rdl2ot/src/rdl2ot/opentitan.py

@@ -2,27 +2,28 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Functions with opentitan specific logic."""
+
 import re
 
 from systemrdl import node
 from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
 
 
 def register_permit_mask(reg: dict) -> int:
-    """One bit presents one byte in the register, so in total 4 bits are used.
-    """
+    """One bit presents one byte in the register, so in total 4 bits are used."""
     w = reg["msb"] + 1
-    if w > 24:
+    if w > 24:  # noqa: PLR2004
         return 0b1111
-    if w > 16:
+    if w > 16:  # noqa: PLR2004
         return 0b0111
-    if w > 8:
+    if w > 8:  # noqa: PLR2004
         return 0b0011
     return 0b0001
 
 
-def needs_read_en(reg: dict()) -> bool:
-    """Return true if at least one field needs a read-enable
+def needs_read_en(reg: dict) -> bool:
+    """Return true if at least one field needs a read-enable.
 
     This is true if any of the following are true:
 
@@ -40,44 +41,42 @@ def needs_read_en(reg: dict()) -> bool:
         side might need the re signal)
     """
     return reg["shadowed"] or any(
-        [
-            (field["clear_onread"] or (reg["external"] and field["sw_readable"]))
-            for field in reg["fields"]
-        ]
+        (field["clear_onread"] or (reg["external"] and field["sw_readable"]))
+        for field in reg["fields"]
     )
 
 
-def needs_write_en(reg: dict()) -> bool:
-    """Should the register for this field have a write-enable signal?
+def needs_write_en(reg: dict) -> bool:
+    """Return register for this field should have a write-enable signal.
 
     This is almost the same as allows_write(), but doesn't return true for
     RC registers, which should use a read-enable signal (connected to their
     prim_subreg's we port).
     """
-    return any([(not field["clear_onread"] and field["sw_writable"]) for field in reg["fields"]])
+    return any((not field["clear_onread"] and field["sw_writable"]) for field in reg["fields"])
+
 
+def needs_qe(reg: dict) -> bool:
+    """Return true if the register or at least one field needs a q-enable."""
+    return any(field["swmod"] for field in reg["fields"])
 
-def needs_qe(reg: dict()) -> bool:
-    """Return true if the register or at least one field needs a q-enable"""
-    return any([field["swmod"] for field in reg["fields"]])
 
+def needs_int_qe(reg: dict) -> bool:
+    """Return true if the register or at least one field needs an internal q-enable.
 
-def needs_int_qe(reg: dict()) -> bool:
-    """Return true if the register or at least one field needs an
-    internal q-enable.  An internal q-enable means the net
-    may be consumed by other reg logic but will not be exposed
-    in the package file.
+    An internal q-enable means the net may be consumed by other reg logic but will
+    not be exposed in the package file.
     """
     return (bool(reg["async_clk"]) and reg["hw_writable"]) or needs_qe(reg)
 
 
 def get_bit_width(offset: int) -> int:
-    """Calculate the number of bits to address every byte of the block"""
+    """Calculate the number of bits to address every byte of the block."""
     return (offset - 1).bit_length()
 
 
 def get_sw_access_enum(field: node.FieldNode) -> str:
-    """Map the rdl access permissions to reggen SwAccess enum"""
+    """Map the rdl access permissions to reggen SwAccess enum."""
     sw = field.get_property("sw")
     onwrite = field.get_property("onwrite")
     onread = field.get_property("onread")
@@ -99,15 +98,17 @@ def get_sw_access_enum(field: node.FieldNode) -> str:
     return "NONE"
 
 
-def fields_no_write_en(reg: dict()) -> int:
+def fields_no_write_en(reg: dict) -> int:
+    """Count how many fields has write enable."""
     res = 0
     for idx, field in enumerate(reg["fields"]):
         res |= (not needs_we(field)) << idx
     return res
 
 
 def needs_we(field: dict) -> bool:
-    """Should the register for this field have a write-enable signal?
+    """True if the register for this field should have a write-enable signal.
+
     This is almost the same as allows_write(), but doesn't return true for
     RC registers, which should use a read-enable signal (connected to their
     prim_subreg's we port).
@@ -116,8 +117,9 @@ def needs_we(field: dict) -> bool:
 
 
 def is_homogeneous(reg: dict) -> bool:
-    """Return true if all fields of a register are equal. The offset are excluded from
-    the comparison.
+    """Return true if all fields of a register are equal.
+
+    The offset are excluded from the comparison.
     """
     exclude = ["name", "msb", "lsb", "bitmask", "type"]
     unamed_fields = [