Merge pull request #12 from lowRISC/develop

Add new features

Author: engdoreis

flake.nix

@@ -56,7 +56,7 @@
       env = pythonSet.mkVirtualEnv "python-env" workspace.deps.default;
   in {
     devShells.x86_64-linux.default = pkgs.mkShell {
-      packages = [env];
+      packages = [env pkgs.uv];
       buildInputs = [peakrdl];
     };
     formatter.x86_64-linux = nixpkgs.legacyPackages.x86_64-linux.alejandra;

pyproject.toml

@@ -37,7 +37,7 @@ extend-select = ["W391", "E303"]
 allowed-confusables = ["−"]
 ignore = [
     "D203", "D213", "COM812", "ISC001", "FIX", "TD", "T201", "S101", "C901", "D401",
-    "PLR0911", "PLR0915", "INP001", "RUF012", "EXE001", "S701"
+    "PLR0911", "PLR0915", "INP001", "RUF012", "EXE001", "S701", "FBT001", "FBT002"
 ]
 
 [tool.uv.workspace]

rdl2ot/src/rdl2ot/cli.py

@@ -29,18 +29,23 @@ def main() -> None:
     default="./result",
     type=click.Path(writable=True),
 )
-def export_rtl(input_file: str, out_dir: str) -> None:
+@click.option(
+    "--soc",
+    is_flag=True,
+)
+def export_rtl(input_file: str, out_dir: str, soc: bool = False) -> None:
     """Export opentitan rtl.
 
     INPUT_FILE: The input RDL
     OUT_DIR: The destination dir to generate the output
+    SOC: Indicates that the input RDL is a SoC top
 
     """
-    print("Compiling file: {input_file}...")
+    print(f"Compiling file: {input_file}...")
     rdlc = RDLCompiler()
     rdlc.compile_file(input_file)
     root = rdlc.elaborate()
 
-    rtl_exporter.run(root.top, Path(out_dir))
+    rtl_exporter.run(root.top, Path(out_dir), soc)
 
     print("Successfully finished!\n")

rdl2ot/src/rdl2ot/rtl_exporter.py

@@ -17,25 +17,43 @@
 DEFAULT_INTERFACE_NAME = "regs"
 
 
-def run(root_node: node.AddrmapNode, out_dir: Path) -> None:
-    """Export RDL to opentitan RTL."""
+def _camelcase(value: str) -> str:
+    words = value.split("_")
+    return "".join(word.capitalize() for word in words)
+
+
+def run(root_node: node.AddrmapNode, out_dir: Path, is_soc: bool = False) -> None:
+    """Export RDL to opentitan RTL.
+
+    IS_SOC: True if the root node is a SoC with peripherals/devices.
+    """
     factory = OtInterfaceBuilder()
-    data = factory.parse_root(root_node)
+    data = factory.parse_soc(root_node) if is_soc else factory.parse_ip_block(root_node)
 
     Path(out_dir / "rdl.json").write_text(json.dumps(data, indent=2), encoding="utf-8")
 
+    if not is_soc:
+        _export(data, out_dir)
+        return
+
+    for ip_block in data["devices"]:
+        _export(ip_block, out_dir)
+
+
+def _export(ip_block: dict, out_dir: Path) -> None:
     file_loader = FileSystemLoader(TEMPLATES_DIR)
     env = Environment(loader=file_loader)
+    env.filters["camelcase"] = _camelcase
 
-    ip_name = data["ip_name"]
+    ip_name = ip_block["ip_name"].lower()
     reg_pkg_tpl = env.get_template("reg_pkg.sv.tpl")
-    stream = reg_pkg_tpl.render(data)
+    stream = reg_pkg_tpl.render(ip_block)
     path = out_dir / f"{ip_name}_reg_pkg.sv"
     path.open("w").write(stream)
     print(f"Generated {path}.")
 
     reg_top_tpl = env.get_template("reg_top.sv.tpl")
-    for interface in data["interfaces"]:
+    for interface in ip_block["interfaces"]:
         name = "_{}".format(interface["name"].lower()) if "name" in interface else ""
         data_ = {"ip_name": ip_name, "interface": interface}
         stream = reg_top_tpl.render(data_).replace(" \n", "\n")
@@ -187,14 +205,10 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
         self.any_shadowed_reg = False
         self.async_registers.clear()
 
-        if addrmap.is_array:
-            print(f"WARNING: Unsupported array type: {type(addrmap)}, skiping...")
-
         interface = {}
         if defalt_name:
             interface["name"] = addrmap.inst_name or defalt_name
 
-        interface["offset"] = addrmap.address_offset
         interface["regs"] = []
         interface["windows"] = []
         for child in addrmap.children():
@@ -233,29 +247,38 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
         interface["any_integrity_bypass"] = any(
             win["integrity_bypass"] for win in interface["windows"]
         )
+        interface["alerts"] = [
+            f["name"]
+            for reg in interface["regs"]
+            for f in reg["fields"]
+            if reg["name"] == "ALERT_TEST"
+        ]
         return interface
 
-    def parse_root(self, root: node.AddrmapNode) -> dict:
-        """Parse the root node and return a dictionary representing a window."""
-        if root.is_array:
-            print("Error: Unsupported array type on the top")
-            raise RuntimeError
-        if not isinstance(root, node.AddrmapNode):
-            print("Error: Top level must be an addrmap")
-            raise TypeError
-
+    def parse_ip_block(self, ip_block: node.AddrmapNode) -> dict:
+        """Parse the ip_block node of an IP block and return a dictionary."""
         obj = {}
-        params = self.get_paramesters(root)
+        params = self.get_paramesters(ip_block)
         if params:
             obj["parameters"] = params
-        obj["ip_name"] = root.inst_name
-        obj["offset"] = root.address_offset
+        obj["ip_name"] = ip_block.inst_name
+
+        obj["offsets"] = []
+        if ip_block.is_array:
+            offset = ip_block.raw_address_offset
+            for _idx in range(ip_block.array_dimensions[0]):
+                obj["offsets"].append(offset)
+                offset += ip_block.array_stride
+        else:
+            obj["offsets"].append(ip_block.address_offset)
 
         obj["interfaces"] = []
-        for child in root.children():
+        obj["alerts"] = []
+        for child in ip_block.children():
             if isinstance(child, node.AddrmapNode):
                 child_obj = self.get_interface(child, DEFAULT_INTERFACE_NAME)
                 obj["interfaces"].append(child_obj)
+                obj["alerts"].extend(child_obj["alerts"])
             elif isinstance(child, node.RegNode | node.MemNode | node.RegfileNode):
                 continue
             else:
@@ -265,9 +288,24 @@ def parse_root(self, root: node.AddrmapNode) -> dict:
                 )
                 raise TypeError
 
-        # If the root contain imediate registers, use a default interface name
-        if len(root.registers()) > 0:
-            interface = self.get_interface(root)
+        # If the ip_block contain imediate registers, use a default interface name
+        if len(ip_block.registers()) > 0:
+            interface = self.get_interface(ip_block)
             obj["interfaces"].append(interface)
+            obj["alerts"].extend(interface["alerts"])
+
+        return obj
 
+    def parse_soc(self, root: node.AddrmapNode) -> dict:
+        """Parse the SoC root node and return a dictionary."""
+        if root.is_array:
+            print("Error: Unsupported array type on the top")
+            raise RuntimeError
+        if not isinstance(root, node.AddrmapNode):
+            print("Error: Top level must be an addrmap")
+            raise TypeError
+
+        obj = {"devices": []}
+        for child in root.children():
+            obj["devices"].append(self.parse_ip_block(child))
         return obj

rdl2ot/src/templates/reg_pkg.sv.tpl

@@ -25,6 +25,17 @@ package {{ ip_name }}_reg_pkg;
   parameter int NumRegs{{ interface.name|title }} = {{ interface.num_regs }};
 {%- endfor %}
 
+
+{%- if alerts|length > 0 %}
+
+  // Alert indices
+  typedef enum int {
+{%- for alert in alerts %}
+    Alert{{ alert | camelcase  }}Idx = {{ loop.index0 }}{{ "," if not loop.last }}
+{%- endfor %}
+  } {{ ip_name | lower }}_alert_idx_t;
+{%- endif %}
+
 {%- for interface in interfaces %}
   {%- set registers = interface.regs %}
   {%- set interface_name = ("_" + interface.name)|lower if interface.name %}

rdl2ot/src/templates/reg_top.sv.tpl

@@ -35,7 +35,6 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
 {%- endif %}
 
 {%- if has_regs %}
-
   // To HW
   output {{ ip_name|lower }}_reg_pkg::{{ ip_name|lower }}{{interface_name}}_reg2hw_t reg2hw, // Write
   input  {{ ip_name|lower }}_reg_pkg::{{ ip_name|lower }}{{interface_name}}_hw2reg_t hw2reg, // Read
@@ -174,9 +173,11 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
 {%- set num_dsp = (interface.num_regs > 0)|int + interface.num_windows %}
 {%- if (num_dsp) <= 1 %}
   {%- if interface.num_windows == 0 %}
+
   assign tl_reg_h2d = tl_i;
   assign tl_o_pre   = tl_reg_d2h;
   {%- else %}
+
   assign tl_win_o = tl_i;
   assign tl_o_pre = tl_win_i;
   {%- endif %}
@@ -413,12 +414,13 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
 {%- endif %}
 
 {%- if has_regs %}
-{{- space }}
+{{ space }}
   // Register instances
 {%- endif %}
 
 {%- set assign = namespace(expr="") %}
 {%- for reg in registers  %}
+{{- space }}
   {%- for offset in reg.offsets %}
     {%- set multireg_idx = loop.index0 if reg.is_multireg %}
     {%- set multireg_suffix = "_{}".format(multireg_idx) if reg.offsets|length > 1 %}
@@ -442,8 +444,9 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
   logic unused_{{ reg.name|lower }}_flds_we;
   assign unused_{{ reg.name|lower }}_flds_we = {{ "^({}_flds_we & {}'h{:x})".format(reg.name|lower, reg.fields|length, reg.fields_no_write_en ) }};
       {%- endif %}
-      {%- set opt_expr = " | {}'h{:x}".format(reg.fields|length, reg.fields_no_write_en ) if reg.fields_no_write_en > 0 %}
-  assign {{regname }}_qe = &{{ "({}_flds_we{})".format(regname, opt_expr) }};
+      {%- set right_expr = "{}_flds_we".format(regname) %}
+      {%- set right_expr = right_expr ~ (" | {}'h{:x}".format(reg.fields|length, reg.fields_no_write_en ) if reg.fields_no_write_en > 0) %}
+  assign {{regname }}_qe = &{{ "({})".format(right_expr) if reg.fields_no_write_en > 0 else "{}".format(right_expr) }};
       {%- else %}
   prim_flop #(
     .Width(1),
@@ -482,7 +485,7 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
   //   F{{ '[{}{}]: {}:{}'.format(field.name, multireg_suffix, field.msb, field.lsb)|lower }}
       {%- endif %}
   prim_subreg{{ '_ext' if reg.external else ('_shadow' if reg.shadowed) }} #(
-    .DW      ({{ field.width }})
+    .DW    ({{ field.width }})
       {%- if not reg.external -%}
     ,
     .SwAccess(prim_subreg_pkg::SwAccess{{ field.reggen_sw_access }}),
@@ -539,8 +542,8 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
 {{- space }}
 {{ space }}
     {%- endfor %}
+{{ space }}
   {%- endfor %}
-{{ space }}  
 {%- endfor %}
 
 {%- if has_regs %}
@@ -569,7 +572,7 @@ module {{ ip_name|lower }}{{interface_name}}_reg_top (
     {%- for offset in reg.offsets %}
       {%- set index = "{num:>{width}}".format(num=ns.counter, width=num_regs_digits) %}
       {%- set ns.counter = ns.counter + 1 %}
-      {%- if loop.first and outer_loop.first -%} ( {%- endif %}
+              {{"(" if loop.first and outer_loop.first else " " -}}
                (addr_hit[{{ index }}] & (|({{ (ip_name ~ interface_name)|upper}}_PERMIT[{{ index }}] & ~reg_be))) 
       {%- if loop.last and outer_loop.last %}));{% else %} |{% endif %}
     {%- endfor %}

rdl2ot/tests/snapshots/lc_ctrl_dmi_reg_top.sv

@@ -46,6 +46,7 @@ module lc_ctrl_dmi_reg_top (
     .tl_i(tl_o_pre),
     .tl_o(tl_o)
   );
+
   assign tl_win_o = tl_i;
   assign tl_o_pre = tl_win_i;
 

rdl2ot/tests/snapshots/lc_ctrl_reg_pkg.sv

@@ -28,6 +28,13 @@ package lc_ctrl_reg_pkg;
   parameter int NumRegsRegs = 35;
   parameter int NumRegsDmi = 0;
 
+  // Alert indices
+  typedef enum int {
+    AlertFatalProgErrorIdx = 0,
+    AlertFatalStateErrorIdx = 1,
+    AlertFatalBusIntegErrorIdx = 2
+  } lc_ctrl_alert_idx_t;
+
   ///////////////////////////////////////////////
   // Typedefs for registers for regs interface //
   ///////////////////////////////////////////////