diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 3554812..7363075 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -33,6 +33,5 @@ jobs:
       run: uv run pytest        
       working-directory: rdlexporter
 
-    - name: Build rdlexporter package 
-      run: uv run python -m build        
-      working-directory: rdlexporter
+    - name: Build packages 
+      run: uv build --all        
diff --git a/README.md b/README.md
index d59a1e1..6d13b62 100644
--- a/README.md
+++ b/README.md
@@ -18,6 +18,8 @@ nix develop
 ## rdl2ot cli tool
 A PeakRDL extension to generate Opentitan style source files from SystemRDL files.
 
+For more details, refer to [rdl2ot](./rdl2ot)
+
 ### How to run tests
 ```sh
 cd rdl2ot
@@ -33,6 +35,8 @@ python src/rdl2ot export-rtl tests/snapshots/lc_ctrl.rdl /tmp/
 ## Rdl-exporter
 A library to generate SystemRDL files from the Hierarchical Register Model.
 
+For more details, refer to [rdlexporter](./rdlexporter)
+
 ### How to run tests
 ```sh
 cd rdl-exporter
@@ -46,8 +50,7 @@ uv sync --all-extras
 ```
 Build package
 ```sh
-cd rdl-exporter
-uv run python -m build
+uv build --all
 ```
 Install the package locally
 ```sh
diff --git a/pyproject.toml b/pyproject.toml
index 082fdef..1485f52 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,29 +1,22 @@
 [project]
 name = "benevisrdl"
-version = "0.0.0"
+version = "0.1.0"
 description = "Houses PeakRDL pluggins."
 requires-python = ">=3.10"
-readme = "README.md"        # Path to your README file
-license = { file = "LICENSE" } # Path to your LICENSE file
+readme = "README.md"      
+license = { file = "LICENSE" }
 dependencies = [
-  "uv==0.6.1",
-  "isort==5.10.1",
-  "yapf==0.32.0",
-  "click>=8.2.1",
-  "jinja2>=3.1.6",
-  "peakrdl>=1.4.0",
 ]
+
 [project.optional-dependencies]
 linting = [
+  "pyright>=1.1.403",
   "ruff>=0.9.6",
-  "mypy==0.971",
-  "flake8 ~= 7.1",
 ]
 dev = [
   "pytest>=8.4.1",
-  "hatch>=1.4.1",
   "twine>=6.1.0",
-  "build>=1.2.2",
+  "uv-build>=0.8.4",
 ]
 ci = ["benevisrdl[linting,dev]"]
 
@@ -33,11 +26,25 @@ py-modules = []
 [tool.ruff]
 target-version = "py310"
 line-length = 100
+extend-exclude = [
+]
 
 [tool.ruff.lint]
 preview = true
 explicit-preview-rules = true
-extend-select = ["E", "E303", "W391"]
+select = ["ALL"]
+extend-select = ["W391", "E303"]
+allowed-confusables = ["−"]
+ignore = [
+    "D203", "D213", "COM812", "ISC001", "FIX", "TD", "T201", "S101", "C901", "D401",
+    "PLR0911", "PLR0915", "INP001", "RUF012", "EXE001", "S701"
+]
 
 [tool.uv.workspace]
 members = [ "rdl2ot", "rdlexporter"]
+
+[[tool.uv.index]]
+name = "testpypi"
+url = "https://test.pypi.org/simple/"
+publish-url = "https://test.pypi.org/legacy/"
+explicit = true
diff --git a/rdl2ot/README.md b/rdl2ot/README.md
new file mode 100644
index 0000000..7f82002
--- /dev/null
+++ b/rdl2ot/README.md
@@ -0,0 +1,21 @@
+# rdl2ot cli tool
+A PeakRDL extension to generate Opentitan style source files from SystemRDL files.
+
+## How to generate the Opentitan register interfaces from a RDL file
+```sh
+rdl2ot export-rtl <input_rdl> <output_dir>
+```
+
+Example:
+```sh
+mkdir -p /tmp/lc_ctrl
+rdl2ot export-rtl tests/snapshots/lc_ctrl.rdl /tmp/lc_ctrl/
+```
+
+## Contributing
+### How to run tests
+```sh
+cd rdl2ot
+pytest
+```
+
diff --git a/rdl2ot/pyproject.toml b/rdl2ot/pyproject.toml
index 4dbb87d..fbf78cd 100644
--- a/rdl2ot/pyproject.toml
+++ b/rdl2ot/pyproject.toml
@@ -3,9 +3,38 @@ name = "rdl2ot"
 version = "0.1.0"
 description = "An extension of PeakRDL to generate Opentitan RTL."
 requires-python = ">=3.10"
+keywords = ["SystemRDL", "Opentitan", "Codegen"]
+readme = "README.md"
 dependencies = [
+  "click>=8.2.1",
+  "jinja2>=3.1.6",
+  "peakrdl>=1.4.0",
 ]
 
+authors = [
+    { name = "lowRISC contributors"},
+]
+
+[project.scripts]
+rdl2ot = "rdl2ot.cli:main"
+
+[project.urls]
+Homepage = "https://github.com/lowrisc/benevisrdl"
+Issues = "https://github.com/lowrisc/benevisrdl/issues"
+Documentation = "https://github.com/lowrisc/benevisrdl"
+
 [build-system]
 requires = ["hatchling"]
 build-backend = "hatchling.build"
+
+[tool.pyright]
+include = ["src"]
+reportMissingImports = "error"
+reportMissingTypeStubs = false
+venv = ".venv"
+executionEnvironments = [
+    { root = "src" },
+]
+
+[tool.hatch.build.targets.wheel]
+packages = ["src/rdl2ot", "src/templates"]
diff --git a/rdl2ot/src/rdl2ot/__init__.py b/rdl2ot/src/rdl2ot/__init__.py
index 3e8bb41..d532460 100644
--- a/rdl2ot/src/rdl2ot/__init__.py
+++ b/rdl2ot/src/rdl2ot/__init__.py
@@ -1,3 +1,5 @@
 # Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
+
+"""Init."""
diff --git a/rdl2ot/src/rdl2ot/__main__.py b/rdl2ot/src/rdl2ot/__main__.py
index de9d849..fef943a 100644
--- a/rdl2ot/src/rdl2ot/__main__.py
+++ b/rdl2ot/src/rdl2ot/__main__.py
@@ -2,6 +2,8 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Main."""
+
 from cli import main
 
 if __name__ == "__main__":
diff --git a/rdl2ot/src/rdl2ot/cli.py b/rdl2ot/src/rdl2ot/cli.py
index 40ff2ec..34f2b56 100644
--- a/rdl2ot/src/rdl2ot/cli.py
+++ b/rdl2ot/src/rdl2ot/cli.py
@@ -3,42 +3,44 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-import click
+
+"""Cli."""
+
 from pathlib import Path
 
+import click
+from systemrdl import RDLCompiler
+
+from rdl2ot import rtl_exporter
+
 
 @click.group()
-def main():
-    pass
+def main() -> None:
+    """Cli."""
 
 
 @main.command()
 @click.argument(
     "input_file",
     type=click.Path(writable=True),
-    # help="The input RDL.",
 )
 @click.argument(
     "out_dir",
     default="./result",
     type=click.Path(writable=True),
-    # help="The destination dir to generate the output.",
 )
-def export_rtl(input_file: str, out_dir: str):
-    from systemrdl import RDLCompiler
+def export_rtl(input_file: str, out_dir: str) -> None:
+    """Export opentitan rtl.
 
+    INPUT_FILE: The input RDL
+    OUT_DIR: The destination dir to generate the output
+
+    """
+    print("Compiling file: {input_file}...")
     rdlc = RDLCompiler()
-    try:
-        rdlc.compile_file(input_file)
-        root = rdlc.elaborate()
-    except Exception as e:
-        raise RuntimeError(f"In file {input_file}") from e
-
-    import export_rtl
-
-    try:
-        export_rtl.run(rdlc, root, Path(out_dir))
-    except Exception as e:
-        raise RuntimeError(f"In file {input_file}") from e
+    rdlc.compile_file(input_file)
+    root = rdlc.elaborate()
+
+    rtl_exporter.run(rdlc, root, Path(out_dir))
 
     print("Successfully finished!\n")
diff --git a/rdl2ot/src/rdl2ot/opentitan.py b/rdl2ot/src/rdl2ot/opentitan.py
index b551696..eb526fe 100644
--- a/rdl2ot/src/rdl2ot/opentitan.py
+++ b/rdl2ot/src/rdl2ot/opentitan.py
@@ -2,27 +2,28 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-from systemrdl.rdltypes import OnReadType, OnWriteType, AccessType
-from systemrdl import node
+"""Functions with opentitan specific logic."""
+
 import re
 
+from systemrdl import node
+from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
+
 
 def register_permit_mask(reg: dict) -> int:
-    """
-    One bit presents one byte in the register, so in total 4 bits are used.
-    """
+    """One bit presents one byte in the register, so in total 4 bits are used."""
     w = reg["msb"] + 1
-    if w > 24:
+    if w > 24:  # noqa: PLR2004
         return 0b1111
-    if w > 16:
+    if w > 16:  # noqa: PLR2004
         return 0b0111
-    if w > 8:
+    if w > 8:  # noqa: PLR2004
         return 0b0011
     return 0b0001
 
 
-def needs_read_en(reg: dict()) -> bool:
-    """Return true if at least one field needs a read-enable
+def needs_read_en(reg: dict) -> bool:
+    """Return true if at least one field needs a read-enable.
 
     This is true if any of the following are true:
 
@@ -40,43 +41,42 @@ def needs_read_en(reg: dict()) -> bool:
         side might need the re signal)
     """
     return reg["shadowed"] or any(
-        [
-            (field["clear_onread"] or (reg["external"] and field["sw_readable"]))
-            for field in reg["fields"]
-        ]
+        (field["clear_onread"] or (reg["external"] and field["sw_readable"]))
+        for field in reg["fields"]
     )
 
 
-def needs_write_en(reg: dict()) -> bool:
-    """Should the register for this field have a write-enable signal?
+def needs_write_en(reg: dict) -> bool:
+    """Return register for this field should have a write-enable signal.
 
     This is almost the same as allows_write(), but doesn't return true for
     RC registers, which should use a read-enable signal (connected to their
     prim_subreg's we port).
     """
-    return any([(not field["clear_onread"] and field["sw_writable"]) for field in reg["fields"]])
+    return any((not field["clear_onread"] and field["sw_writable"]) for field in reg["fields"])
+
 
+def needs_qe(reg: dict) -> bool:
+    """Return true if the register or at least one field needs a q-enable."""
+    return any(field["swmod"] for field in reg["fields"])
 
-def needs_qe(reg: dict()) -> bool:
-    """Return true if the register or at least one field needs a q-enable"""
-    return any([field["swmod"] for field in reg["fields"]])
 
+def needs_int_qe(reg: dict) -> bool:
+    """Return true if the register or at least one field needs an internal q-enable.
 
-def needs_int_qe(reg: dict()) -> bool:
-    """Return true if the register or at least one field needs an
-    internal q-enable.  An internal q-enable means the net
-    may be consumed by other reg logic but will not be exposed
-    in the package file."""
+    An internal q-enable means the net may be consumed by other reg logic but will
+    not be exposed in the package file.
+    """
     return (bool(reg["async_clk"]) and reg["hw_writable"]) or needs_qe(reg)
 
 
 def get_bit_width(offset: int) -> int:
-    """Calculate the number of bits to address every byte of the block"""
+    """Calculate the number of bits to address every byte of the block."""
     return (offset - 1).bit_length()
 
 
 def get_sw_access_enum(field: node.FieldNode) -> str:
-    """Map the rdl access permissions to reggen SwAccess enum"""
+    """Map the rdl access permissions to reggen SwAccess enum."""
     sw = field.get_property("sw")
     onwrite = field.get_property("onwrite")
     onread = field.get_property("onread")
@@ -98,7 +98,8 @@ def get_sw_access_enum(field: node.FieldNode) -> str:
     return "NONE"
 
 
-def fields_no_write_en(reg: dict()) -> int:
+def fields_no_write_en(reg: dict) -> int:
+    """Count how many fields has write enable."""
     res = 0
     for idx, field in enumerate(reg["fields"]):
         res |= (not needs_we(field)) << idx
@@ -106,7 +107,8 @@ def fields_no_write_en(reg: dict()) -> int:
 
 
 def needs_we(field: dict) -> bool:
-    """Should the register for this field have a write-enable signal?
+    """True if the register for this field should have a write-enable signal.
+
     This is almost the same as allows_write(), but doesn't return true for
     RC registers, which should use a read-enable signal (connected to their
     prim_subreg's we port).
@@ -115,8 +117,9 @@ def needs_we(field: dict) -> bool:
 
 
 def is_homogeneous(reg: dict) -> bool:
-    """Return true if all fields of a register are equal. The offset are excluded from
-    the comparison.
+    """Return true if all fields of a register are equal.
+
+    The offset are excluded from the comparison.
     """
     exclude = ["name", "msb", "lsb", "bitmask", "type"]
     unamed_fields = [
diff --git a/rdl2ot/src/rdl2ot/export_rtl.py b/rdl2ot/src/rdl2ot/rtl_exporter.py
similarity index 85%
rename from rdl2ot/src/rdl2ot/export_rtl.py
rename to rdl2ot/src/rdl2ot/rtl_exporter.py
index 5fc206a..deac8eb 100644
--- a/rdl2ot/src/rdl2ot/export_rtl.py
+++ b/rdl2ot/src/rdl2ot/rtl_exporter.py
@@ -2,30 +2,33 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Export RDL to opentitan RTL."""
+
 import json
 from pathlib import Path
-from systemrdl import RDLCompiler
-from systemrdl import node
-from systemrdl.rdltypes import OnReadType
+
 from jinja2 import Environment, FileSystemLoader
-import opentitan
+from systemrdl import RDLCompiler, node
+from systemrdl.rdltypes import OnReadType
+
+from rdl2ot import opentitan
 
-TEMPLATES_DIR = "./src/templates"
+TEMPLATES_DIR = Path(__file__).parent.parent / "templates"
 DEFAULT_INTERFACE_NAME = "regs"
 
 
-def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path):
+def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path) -> None:
+    """Export RDL to opentitan RTL."""
     factory = OtInterfaceBuilder(rdlc)
     data = factory.parse_root(obj.top)
-    with open("/tmp/reg.json", "w", encoding="utf-8") as f:
-        json.dump(data, f, indent=2)
+
+    Path(out_dir / "rdl.json").write_text(json.dumps(data, indent=2), encoding="utf-8")
 
     file_loader = FileSystemLoader(TEMPLATES_DIR)
     env = Environment(loader=file_loader)
 
     ip_name = data["ip_name"]
     reg_pkg_tpl = env.get_template("reg_pkg.sv.tpl")
-    # stream = reg_pkg_tpl.stream(data)
     stream = reg_pkg_tpl.render(data)
     path = out_dir / f"{ip_name}_reg_pkg.sv"
     path.open("w").write(stream)
@@ -35,7 +38,6 @@ def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path):
     for interface in data["interfaces"]:
         name = "_{}".format(interface["name"].lower()) if "name" in interface else ""
         data_ = {"ip_name": ip_name, "interface": interface}
-        # stream = reg_top_tpl.stream(data_)
         stream = reg_top_tpl.render(data_).replace(" \n", "\n")
         path = out_dir / f"{ip_name}{name}_reg_top.sv"
         path.open("w").write(stream)
@@ -43,6 +45,8 @@ def run(rdlc: RDLCompiler, obj: node.RootNode, out_dir: Path):
 
 
 class OtInterfaceBuilder:
+    """Opentitan Interface Builder."""
+
     num_regs: int = 0  # The number of registers of an interface
     num_windows: int = 0  # The number of registers of an interface
     any_async_clk: bool = False  # Whether is there any register with async clock in the interface
@@ -52,14 +56,13 @@ class OtInterfaceBuilder:
     reg_index: int = 0
     rdlc: RDLCompiler
 
-    def __init__(self, rdlc: RDLCompiler):
+    def __init__(self, rdlc: RDLCompiler) -> None:
+        """Constructor."""
         self.rdlc = rdlc
 
     def get_field(self, field: node.FieldNode) -> dict:
-        """
-        Parse a field and return a dictionary.
-        """
-        obj = dict()
+        """Parse a field and return a dictionary."""
+        obj = {}
         obj["name"] = field.inst_name
         obj["type"] = "field"
         obj["desc"] = field.get_property("desc", default="")
@@ -92,10 +95,8 @@ def get_field(self, field: node.FieldNode) -> dict:
         return obj
 
     def get_mem(self, mem: node.FieldNode) -> dict:
-        """
-        Parse a memory and return a dictionary representing a window.
-        """
-        obj = dict()
+        """Parse a memory and return a dictionary representing a window."""
+        obj = {}
         obj["name"] = mem.inst_name
         obj["entries"] = mem.get_property("mementries")
         obj["sw_writable"] = mem.is_sw_writable
@@ -109,10 +110,8 @@ def get_mem(self, mem: node.FieldNode) -> dict:
         return obj
 
     def get_reg(self, reg: node.RegNode) -> dict:
-        """
-        Parse a register and return a dictionary.
-        """
-        obj = dict()
+        """Parse a register and return a dictionary."""
+        obj = {}
         obj["name"] = reg.inst_name
         obj["type"] = "reg"
         obj["width"] = reg.get_property("regwidth")
@@ -131,7 +130,7 @@ def get_reg(self, reg: node.RegNode) -> dict:
             obj["is_multireg"] = True
             self.num_regs += reg.array_dimensions[0]
             offset = reg.raw_address_offset
-            for _idx in range(0, reg.array_dimensions[0]):
+            for _idx in range(reg.array_dimensions[0]):
                 obj["offsets"].append(offset)
                 offset += reg.array_stride
         else:
@@ -143,8 +142,8 @@ def get_reg(self, reg: node.RegNode) -> dict:
         msb = 0
         reset_val = 0
         bitmask = 0
-        for field in reg.fields():
-            field = self.get_field(field)
+        for f in reg.fields():
+            field = self.get_field(f)
             obj["fields"].append(field)
             sw_write_en |= field["sw_write_en"]
             msb = max(msb, field["msb"])
@@ -171,27 +170,21 @@ def get_reg(self, reg: node.RegNode) -> dict:
 
         array_size = len(obj["offsets"])
         if bool(obj["async_clk"]):
-            for index in range(0, array_size):
+            for index in range(array_size):
                 reg_name = reg.inst_name + (f"_{index}" if array_size > 1 else "")
                 self.async_registers.append((self.reg_index + index, reg_name))
         self.reg_index += array_size
         return obj
 
     def get_paramesters(self, obj: node.AddrmapNode | node.RegfileNode) -> [dict]:
-        """
-        Parse the custom property localparams and return a list of  dictionaries.
-        """
-
-        res = [
+        """Parse the custom property localparams and return a list of  dictionaries."""
+        return [
             {"name": param.name, "type": "int", "value": param.get_value()}
             for param in obj.inst.parameters
         ]
-        return res
 
     def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = None) -> dict:
-        """
-        Parse an interface and return a dictionary.
-        """
+        """Parse an interface and return a dictionary."""
         self.num_regs = 0
         self.num_windows = 0
         self.any_async_clk = False
@@ -202,7 +195,7 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
         if addrmap.is_array:
             print(f"WARNING: Unsupported array type: {type(addrmap)}, skiping...")
 
-        interface = dict()
+        interface = {}
         if defalt_name:
             interface["name"] = addrmap.inst_name or defalt_name
 
@@ -213,6 +206,10 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
             if isinstance(child, node.RegNode):
                 child_obj = self.get_reg(child)
                 interface["regs"].append(child_obj)
+            elif isinstance(child, node.RegfileNode):
+                for reg in child.children():
+                    child_obj = self.get_reg(reg)
+                    interface["regs"].append(child_obj)
             elif isinstance(child, node.MemNode):
                 child_obj = self.get_mem(child)
                 interface["windows"].append(child_obj)
@@ -239,22 +236,20 @@ def get_interface(self, addrmap: node.AddrmapNode, defalt_name: None | str = Non
         interface["all_async_clk"] = self.all_async_clk
         interface["any_shadowed_reg"] = self.any_shadowed_reg
         interface["any_integrity_bypass"] = any(
-            [win["integrity_bypass"] for win in interface["windows"]]
+            win["integrity_bypass"] for win in interface["windows"]
         )
         return interface
 
     def parse_root(self, root: node.AddrmapNode) -> dict:
-        """
-        Parse the root node and return a dictionary representing a window.
-        """
+        """Parse the root node and return a dictionary representing a window."""
         if root.is_array:
             print("Error: Unsupported array type on the top")
             raise RuntimeError
         if not isinstance(root, node.AddrmapNode):
             print("Error: Top level must be an addrmap")
-            raise RuntimeError
+            raise TypeError
 
-        obj = dict()
+        obj = {}
         params = self.get_paramesters(root)
         if params:
             obj["parameters"] = params
@@ -266,14 +261,14 @@ def parse_root(self, root: node.AddrmapNode) -> dict:
             if isinstance(child, node.AddrmapNode):
                 child_obj = self.get_interface(child, DEFAULT_INTERFACE_NAME)
                 obj["interfaces"].append(child_obj)
-            elif isinstance(child, node.RegNode | node.MemNode):
+            elif isinstance(child, node.RegNode | node.MemNode | node.RegfileNode):
                 continue
             else:
                 print(
-                    f"""Error: Unsupported type: {type(child)}, top level only supports 
+                    f"""Error: Unsupported type: {type(child)}, top level only supports
                       addrmap and reg components."""
                 )
-                raise RuntimeError
+                raise TypeError
 
         # If the root contain imediate registers, use a default interface name
         if len(root.registers()) > 0:
diff --git a/rdl2ot/tests/snapshots/uart.rdl b/rdl2ot/tests/snapshots/uart.rdl
index 4588269..b290198 100644
--- a/rdl2ot/tests/snapshots/uart.rdl
+++ b/rdl2ot/tests/snapshots/uart.rdl
@@ -1,129 +1,116 @@
 addrmap uart {
-    reg {
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if the transmit FIFO is past the high-water mark.";
-        } TX_WATERMARK[0:0];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if the receive FIFO is past the high-water mark.";
-        } RX_WATERMARK[1:1];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if the transmit FIFO has emptied and no transmit is ongoing.";
-        } TX_EMPTY[2:2];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if the receive FIFO has overflowed.";
-        } RX_OVERFLOW[3:3];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if a framing error has been detected on receive.";
-        } RX_FRAME_ERR[4:4];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if break condition has been detected on receive.";
-        } RX_BREAK_ERR[5:5];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if RX FIFO has characters remaining in the FIFO without being
-            retrieved for the programmed time period.";
-        } RX_TIMEOUT[6:6];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "raised if the receiver has detected a parity error.";
-        } RX_PARITY_ERR[7:7];
-    } INTERRUPT_STATE @ 0x0;
-    reg {
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when tx_watermark is set.";
-        } TX_WATERMARK[0:0];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when rx_watermark is set.";
-        } RX_WATERMARK[1:1];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when tx_empty is set.";
-        } TX_EMPTY[2:2];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when rx_overflow is set.";
-        } RX_OVERFLOW[3:3];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when rx_frame_err is set.";
-        } RX_FRAME_ERR[4:4];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when rx_break_err is set.";
-        } RX_BREAK_ERR[5:5];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when rx_timeout is set.";
-        } RX_TIMEOUT[6:6];
-        field {
-            sw = rw;
-            onwrite = woclr;
-            desc = "Enable interrupt when rx_parity_err is set.";
-        } RX_PARITY_ERR[7:7];
-    } INTERRUPT_ENABLE @ 0x4;
-    reg {
-        field {
-            sw = w;
-            desc = "Write 1 to force tx_watermark to 1.";
-        } TX_WATERMARK[0:0];
-        field {
-            sw = w;
-            desc = "Write 1 to force rx_watermark to 1.";
-        } RX_WATERMARK[1:1];
-        field {
-            sw = w;
-            desc = "Write 1 to force tx_empty to 1.";
-        } TX_EMPTY[2:2];
-        field {
-            sw = w;
-            desc = "Write 1 to force rx_overflow to 1.";
-        } RX_OVERFLOW[3:3];
-        field {
-            sw = w;
-            desc = "Write 1 to force rx_frame_err to 1.";
-        } RX_FRAME_ERR[4:4];
-        field {
-            sw = w;
-            desc = "Write 1 to force rx_break_err to 1.";
-        } RX_BREAK_ERR[5:5];
-        field {
-            sw = w;
-            desc = "Write 1 to force rx_timeout to 1.";
-        } RX_TIMEOUT[6:6];
-        field {
-            sw = w;
-            desc = "Write 1 to force rx_parity_err to 1.";
-        } RX_PARITY_ERR[7:7];
-    } INTERRUPT_TEST @ 0x8;
-    reg {
-        field {
-            sw = w;
-            desc = "Write 1 to trigger one alert event of this kind.";
-        } FATAL_FAULT[0:0];
-    } ALERT_TEST @ 0xC;
+    regfile signals {
+      default sw = rw;
+      reg {
+            field {
+              onwrite = woclr;
+              desc = "raised if the transmit FIFO is past the high-water mark.";
+          } TX_WATERMARK[0:0];
+          field {
+              onwrite = woclr;
+              desc = "raised if the receive FIFO is past the high-water mark.";
+          } RX_WATERMARK[1:1];
+          field {
+              onwrite = woclr;
+              desc = "raised if the transmit FIFO has emptied and no transmit is ongoing.";
+          } TX_EMPTY[2:2];
+          field {
+              onwrite = woclr;
+              desc = "raised if the receive FIFO has overflowed.";
+          } RX_OVERFLOW[3:3];
+          field {
+              onwrite = woclr;
+              desc = "raised if a framing error has been detected on receive.";
+          } RX_FRAME_ERR[4:4];
+          field {
+              onwrite = woclr;
+              desc = "raised if break condition has been detected on receive.";
+          } RX_BREAK_ERR[5:5];
+          field {
+              onwrite = woclr;
+              desc = "raised if RX FIFO has characters remaining in the FIFO without being
+              retrieved for the programmed time period.";
+          } RX_TIMEOUT[6:6];
+          field {
+              onwrite = woclr;
+              desc = "raised if the receiver has detected a parity error.";
+          } RX_PARITY_ERR[7:7];
+      } INTERRUPT_STATE @ 0x0;
+      reg {
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when tx_watermark is set.";
+          } TX_WATERMARK[0:0];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when rx_watermark is set.";
+          } RX_WATERMARK[1:1];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when tx_empty is set.";
+          } TX_EMPTY[2:2];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when rx_overflow is set.";
+          } RX_OVERFLOW[3:3];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when rx_frame_err is set.";
+          } RX_FRAME_ERR[4:4];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when rx_break_err is set.";
+          } RX_BREAK_ERR[5:5];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when rx_timeout is set.";
+          } RX_TIMEOUT[6:6];
+          field {
+              onwrite = woclr;
+              desc = "Enable interrupt when rx_parity_err is set.";
+          } RX_PARITY_ERR[7:7];
+      } INTERRUPT_ENABLE @ 0x4;
+      reg {
+          field {
+              sw = w;
+              desc = "Write 1 to force tx_watermark to 1.";
+          } TX_WATERMARK[0:0];
+          field {
+              sw = w;
+              desc = "Write 1 to force rx_watermark to 1.";
+          } RX_WATERMARK[1:1];
+          field {
+              sw = w;
+              desc = "Write 1 to force tx_empty to 1.";
+          } TX_EMPTY[2:2];
+          field {
+              sw = w;
+              desc = "Write 1 to force rx_overflow to 1.";
+          } RX_OVERFLOW[3:3];
+          field {
+              sw = w;
+              desc = "Write 1 to force rx_frame_err to 1.";
+          } RX_FRAME_ERR[4:4];
+          field {
+              sw = w;
+              desc = "Write 1 to force rx_break_err to 1.";
+          } RX_BREAK_ERR[5:5];
+          field {
+              sw = w;
+              desc = "Write 1 to force rx_timeout to 1.";
+          } RX_TIMEOUT[6:6];
+          field {
+              sw = w;
+              desc = "Write 1 to force rx_parity_err to 1.";
+          } RX_PARITY_ERR[7:7];
+      } INTERRUPT_TEST @ 0x8;
+      reg {
+          field {
+              sw = w;
+              desc = "Write 1 to trigger one alert event of this kind.";
+          } FATAL_FAULT[0:0];
+      } ALERT_TEST @ 0xC;
+    }sig;
     reg {
         field {
             desc = "TX enable";
@@ -266,4 +253,4 @@ addrmap uart {
             sw = rw;
         } EN[31:31];
     } TIMEOUT_CTRL @ 0x30;
-};
\ No newline at end of file
+};
diff --git a/rdl2ot/tests/test_rdl2ot.py b/rdl2ot/tests/test_rdl2ot.py
index f2b4361..11f496e 100644
--- a/rdl2ot/tests/test_rdl2ot.py
+++ b/rdl2ot/tests/test_rdl2ot.py
@@ -2,15 +2,19 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-from pathlib import Path
-import sys
+"""Tests."""
+
 import subprocess
+import sys
+from pathlib import Path
+
+import pytest
 
 CLI_TOOL_PATH = Path(__file__).parent.parent / "src/rdl2ot"
 SNAPSHOTS_DIR = Path(__file__).parent / "snapshots"
 
 
-def run_cli_tool(input_file_path: Path, output_dir_path: Path):
+def _run_cli_tool(input_file_path: Path, output_dir_path: Path) -> subprocess.CompletedProcess:
     command = [
         sys.executable,  # Use the current Python interpreter
         str(CLI_TOOL_PATH),
@@ -18,13 +22,14 @@ def run_cli_tool(input_file_path: Path, output_dir_path: Path):
         str(input_file_path),
         str(output_dir_path),
     ]
-    result = subprocess.run(command, capture_output=True, text=True, check=False)
-    return result
+    return subprocess.run(command, capture_output=True, text=True, check=False)  # noqa: S603
 
-
-def run_ip_test(tmp_path: Path, ip_block: str):
+test_ips = ["lc_ctrl", "uart"]
+@pytest.mark.parametrize("ip_block", test_ips)
+def test_export_ip(tmp_path: Path, ip_block: str) -> None:
+    """Test an given ip block."""
     input_rdl = SNAPSHOTS_DIR / f"{ip_block}.rdl"
-    cli_result = run_cli_tool(input_rdl, tmp_path)
+    cli_result = _run_cli_tool(input_rdl, tmp_path)
     assert cli_result.returncode == 0, f"CLI exited with error: {cli_result.stderr}"
     assert "Successfully finished!" in cli_result.stdout  # Check for success message
 
@@ -36,11 +41,3 @@ def run_ip_test(tmp_path: Path, ip_block: str):
         assert actual_output_content == snapshot_content, (
             f"Output mismatch, to debug, run:\nmeld {outfile} {snapshot_file}\n"
         )
-
-
-def test_cli_lc_ctrl(tmp_path: Path):
-    run_ip_test(tmp_path, "lc_ctrl")
-
-
-def test_cli_uart(tmp_path: Path):
-    run_ip_test(tmp_path, "uart")
diff --git a/rdlexporter/README.md b/rdlexporter/README.md
new file mode 100644
index 0000000..7f6cd15
--- /dev/null
+++ b/rdlexporter/README.md
@@ -0,0 +1,61 @@
+# rdl-exporter
+A library to generate SystemRDL files from the Hierarchical Register Model.
+
+How to use it: 
+```sh
+uv pip install rdlexporter
+```
+Example:
+```python
+from rdlexporter import RdlExporter
+from systemrdl import RDLCompiler, RDLImporter
+from systemrdl.rdltypes import AccessType
+
+rdlc = RDLCompiler()
+
+imp = RDLImporter(rdlc)
+imp.default_src_ref = None
+
+addrmap = imp.create_addrmap_definition("generic")
+
+field_en = imp.create_field_definition("EN")
+field_en = imp.instantiate_field(field_en, "EN", 0, 1)
+imp.assign_property(field_en, "reset", 0x00)
+imp.assign_property(field_en, "swmod", value=True)
+imp.assign_property(field_en, "desc", "Enable the ip")
+
+imp.assign_property(field_mode, "reset", 0x7)
+imp.assign_property(field_mode, "desc", "Define the mode.")
+imp.assign_property(field_mode, "sw", AccessType.rw)
+
+reg = imp.create_reg_definition("CTRL")
+imp.add_child(reg, field_en)
+imp.add_child(reg, field_mode)
+
+reg = imp.instantiate_reg(reg, "CTRL", 0x04, [4], 0x04)
+imp.add_child(addrmap, reg)
+
+imp.register_root_component(addrmap)
+RdlExporter(rdlc).export("./generic.rdl")
+```
+
+## Contributing
+### How to run tests
+```sh
+cd rdlexporter
+uv run pytest
+```
+
+### How to build the package and install it locally
+Install dev dependencies
+```sh
+uv sync --all-extras 
+```
+Build package
+```sh
+uv build --all
+```
+Install the package locally
+```sh
+uv pip install dist/rdlexporter-0.1.0-py3-none-any.whl
+```
diff --git a/rdlexporter/pyproject.toml b/rdlexporter/pyproject.toml
index f3454b2..dba1f48 100644
--- a/rdlexporter/pyproject.toml
+++ b/rdlexporter/pyproject.toml
@@ -4,30 +4,33 @@ version = "0.1.0"
 description = "Library to export rdl files"
 requires-python = ">=3.10"
 keywords = ["SystemRDL", "library", "exporter"]
-dependencies = []
+readme = "README.md"
+dependencies = [
+  "peakrdl>=1.4.0",
+]
 
 authors = [
     { name = "lowRISC contributors"},
 ]
 
 [project.urls]
-Homepage = "https://github.com/lowrisc/benevisrdl/rdlexporter"
-Issues = "https://github.com/lowrisc/benevisrdl/rdlexporter/issues"
-Documentation = "https://github.com/lowrisc/benevisrdl/rdlexporter"
+Homepage = "https://github.com/lowrisc/benevisrdl"
+Issues = "https://github.com/lowrisc/benevisrdl/issues"
+Documentation = "https://github.com/lowrisc/benevisrdl"
 
 [build-system]
 requires = ["hatchling"]
 build-backend = "hatchling.build"
 
-[tool.hatch.build.targets.wheel]
-packages = ["src/rdlexporter"]
 
-[tool.hatch.build.targets.sdist]
-exclude = [
-    "/.github",
-    "/tests",
-    "/*.pyc",
-    "/.pytest_cache",
-    "/.uv",
-    "/.venv",
+[tool.pyright]
+include = ["src"]
+reportMissingImports = "error"
+reportMissingTypeStubs = false
+venv = ".venv"
+executionEnvironments = [
+    { root = "src" },
 ]
+
+[tool.hatch.build.targets.wheel]
+packages = ["src/rdlexporter"]
diff --git a/rdlexporter/src/rdlexporter/__init__.py b/rdlexporter/src/rdlexporter/__init__.py
index 5d6cac8..bcf6494 100644
--- a/rdlexporter/src/rdlexporter/__init__.py
+++ b/rdlexporter/src/rdlexporter/__init__.py
@@ -2,10 +2,10 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Init."""
+
 from .exporter import RdlExporter
 
-__all__ = [
-    "RdlExporter",
-]
+__all__ = ("RdlExporter",)
 
 __version__ = "0.1.0"
diff --git a/rdlexporter/src/rdlexporter/exporter.py b/rdlexporter/src/rdlexporter/exporter.py
index 8c85642..2930acf 100644
--- a/rdlexporter/src/rdlexporter/exporter.py
+++ b/rdlexporter/src/rdlexporter/exporter.py
@@ -2,19 +2,24 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
+"""Exports rdl files."""
+
+from dataclasses import dataclass, field
 from pathlib import Path
+
 from systemrdl import RDLCompiler
-from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
-from systemrdl.rdltypes.user_enum import UserEnumMeta
-from systemrdl.ast.literals import StringLiteral, BoolLiteral, IntLiteral, BuiltinEnumLiteral
 from systemrdl.ast.cast import AssignmentCast
+from systemrdl.ast.literals import BoolLiteral, BuiltinEnumLiteral, IntLiteral, StringLiteral
 from systemrdl.ast.references import InstRef
-from systemrdl.component import Addrmap, Reg, Field, Mem, AddressableComponent
-from dataclasses import dataclass, field
+from systemrdl.component import AddressableComponent, Addrmap, Field, Mem, Reg
+from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
+from systemrdl.rdltypes.user_enum import UserEnumMeta
 
 
 @dataclass
 class RdlExporter:
+    """Exports rdl files from AST."""
+
     rdlc: RDLCompiler
     stream: str = ""
     indent_pos = 0
@@ -23,7 +28,7 @@ class RdlExporter:
     dynamic_assignment: dict[str, list[dict]] = field(default_factory=dict)
     ast_path: list[str] = field(default_factory=list)
 
-    def _raise_type_error(self, type_name):
+    def _raise_type_error(self, type_name: str) -> None:
         print(f"Error: Unsupported type: {type_name} at this level only supports")
         raise RuntimeError
 
@@ -42,9 +47,9 @@ def _get_field_limits(self, field: Field) -> (int, int):
 
     def _get_offset(self, comp: AddressableComponent) -> str:
         if isinstance(comp.addr_offset, AssignmentCast):
-            return " @ 0x{:X}".format(comp.addr_offset.get_value())
+            return f" @ 0x{comp.addr_offset.get_value():X}"
         if isinstance(comp.addr_offset, int):
-            return " @ 0x{:X}".format(comp.addr_offset)
+            return f" @ 0x{comp.addr_offset:X}"
         return ""
 
     def _get_register_array_dim(self, reg: Reg) -> int:
@@ -92,7 +97,7 @@ def _emit_property(self, properties: dict) -> None:
             elif isinstance(obj, InstRef):
                 # This should be emited at a higher scope indicated by `ref_root._scope_name`.
                 ref = obj.get_value()
-                scope = ref.ref_root._scope_name or ref.ref_root.type_name
+                scope = ref.ref_root._scope_name or ref.ref_root.type_name  # noqa: SLF001
                 self.dynamic_assignment.setdefault(scope.lower(), []).append(
                     {
                         "property": name,
@@ -114,9 +119,9 @@ def _arrays(self, component: Reg) -> str:
         if len(component.array_dimensions) > 1:
             print("Error: Unsupported multidimentional arrays.")
             raise RuntimeError
+
         dim = self._get_register_array_dim(component)
-        array_str = f"[{dim}]"
-        return array_str
+        return f"[{dim}]"
 
     def _emit_parameters(self, parameters: list) -> None:
         if not len(parameters):
@@ -208,6 +213,7 @@ def _emit_addrmap(self, name: str, addrmap: Addrmap) -> None:
         self.ast_path.pop()
 
     def export(self, outfile: Path) -> None:
+        """Export the SystemRDL ast to an RDL file."""
         self.ast_path.append(str(self.rdlc.root.inst_name))
         for name, component in self.rdlc.root.comp_defs.items():
             if isinstance(component, Addrmap):
diff --git a/rdlexporter/tests/test_rdl-exporter.py b/rdlexporter/tests/test_exporter.py
similarity index 83%
rename from rdlexporter/tests/test_rdl-exporter.py
rename to rdlexporter/tests/test_exporter.py
index 415dbfd..3358303 100644
--- a/rdlexporter/tests/test_rdl-exporter.py
+++ b/rdlexporter/tests/test_exporter.py
@@ -2,30 +2,29 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-import sys
+"""Unittests."""
+
 from pathlib import Path
-from systemrdl import RDLCompiler, RDLCompileError, RDLImporter
-from systemrdl import rdltypes
+
+from systemrdl import RDLCompiler, RDLImporter, rdltypes
+from systemrdl.ast.references import InstRef
 from systemrdl.core.parameter import Parameter
 from systemrdl.messages import FileSourceRef
 from systemrdl.rdltypes import AccessType, OnReadType, OnWriteType
-from systemrdl.ast.references import InstRef
+
 from rdlexporter import RdlExporter
 
 SNAPSHOTS_DIR = Path(__file__).parent / "snapshots"
 
 
-def run_ip_test_from_file(tmp_path: Path, ip_block: str):
+def _run_ip_test_from_file(tmp_path: Path, ip_block: str) -> None:
     input_rdl = SNAPSHOTS_DIR / f"{ip_block}.rdl"
     snapshot_file = input_rdl
     snapshot_content = snapshot_file.read_text(encoding="utf-8")
     output_file = tmp_path / f"{ip_block}.rdl"
 
     rdlc = RDLCompiler()
-    try:
-        rdlc.compile_file(input_rdl)
-    except RDLCompileError:
-        sys.exit(1)
+    rdlc.compile_file(input_rdl)
 
     # Include the user defined enums and properties.
     with output_file.open("w") as f:
@@ -40,15 +39,18 @@ def run_ip_test_from_file(tmp_path: Path, ip_block: str):
     )
 
 
-def test_cli_uart_from_file(tmp_path: Path):
-    run_ip_test_from_file(tmp_path, "uart")
+def test_cli_uart_from_file(tmp_path: Path) -> None:
+    """Test the uart."""
+    _run_ip_test_from_file(tmp_path, "uart")
 
 
-def test_cli_lc_ctrl_from_file(tmp_path: Path):
-    run_ip_test_from_file(tmp_path, "lc_ctrl")
+def test_cli_lc_ctrl_from_file(tmp_path: Path) -> None:
+    """Test the lc_ctrl."""
+    _run_ip_test_from_file(tmp_path, "lc_ctrl")
 
 
-def test_importer(tmp_path: Path):
+def test_importer(tmp_path: Path) -> None:
+    """Test with the SystemRDL importer."""
     input_rdl = SNAPSHOTS_DIR / "generic.rdl"
     snapshot_file = input_rdl
     snapshot_content = snapshot_file.read_text(encoding="utf-8")
@@ -74,13 +76,13 @@ def test_importer(tmp_path: Path):
     field_en = imp.create_field_definition("EN")
     field_en = imp.instantiate_field(field_en, "EN", 0, 1)
     imp.assign_property(field_en, "reset", 0x00)
-    imp.assign_property(field_en, "swmod", True)
+    imp.assign_property(field_en, "swmod", value=True)
     imp.assign_property(field_en, "desc", "Enable the ip")
 
     field_mode = imp.create_field_definition("MODE")
     field_mode = imp.instantiate_field(field_mode, "MODE", 2, 8)
     imp.assign_property(field_mode, "reset", 0x7)
-    imp.assign_property(field_mode, "swmod", False)
+    imp.assign_property(field_mode, "swmod", value=False)
     imp.assign_property(field_mode, "desc", "Define the mode.")
     imp.assign_property(field_mode, "sw", AccessType.rw)
     imp.assign_property(field_mode, "onread", OnReadType.rclr)
@@ -105,7 +107,7 @@ def test_importer(tmp_path: Path):
 
     value = 0x56
     param = Parameter(rdltypes.get_rdltype(value), "Width")
-    param._value = value
+    param._value = value  # noqa: SLF001
     addrmap.parameters.append(param)
 
     imp.register_root_component(addrmap)
diff --git a/uv.lock b/uv.lock
index 3e2816d..fbb9d69 100644
--- a/uv.lock
+++ b/uv.lock
@@ -18,21 +18,6 @@ wheels = [
     { url = "https://files.pythonhosted.org/packages/89/03/a851e84fcbb85214dc637b6378121ef9a0dd61b4c65264675d8a5c9b1ae7/antlr4_python3_runtime-4.13.2-py3-none-any.whl", hash = "sha256:fe3835eb8d33daece0e799090eda89719dbccee7aa39ef94eed3818cafa5a7e8", size = 144462 },
 ]
 
-[[package]]
-name = "anyio"
-version = "4.9.0"
-source = { registry = "https://pypi.org/simple" }
-dependencies = [
-    { name = "exceptiongroup", marker = "python_full_version < '3.11'" },
-    { name = "idna" },
-    { name = "sniffio" },
-    { name = "typing-extensions", marker = "python_full_version < '3.13'" },
-]
-sdist = { url = "https://files.pythonhosted.org/packages/95/7d/4c1bd541d4dffa1b52bd83fb8527089e097a106fc90b467a7313b105f840/anyio-4.9.0.tar.gz", hash = "sha256:673c0c244e15788651a4ff38710fea9675823028a6f08a5eda409e0c9840a028", size = 190949 }
-wheels = [
-    { url = "https://files.pythonhosted.org/packages/a1/ee/48ca1a7c89ffec8b6a0c5d02b89c305671d5ffd8d3c94acf8b8c408575bb/anyio-4.9.0-py3-none-any.whl", hash = "sha256:9f76d541cad6e36af7beb62e978876f3b41e3e04f2c1fbf0884604c0a9c4d93c", size = 100916 },
-]
-
 [[package]]
 name = "backports-tarfile"
 version = "1.2.0"
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-    { name = "flake8" },
-    { name = "hatch" },
-    { name = "mypy" },
+    { name = "pyright" },
     { name = "pytest" },
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     { name = "twine" },
+    { name = "uv-build" },
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 dev = [
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-    { name = "hatch" },
     { name = "pytest" },
     { name = "twine" },
+    { name = "uv-build" },
 ]
 linting = [
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-    { name = "mypy" },
+    { name = "pyright" },
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