fixup! [top] Align ram_cfg ports with OpenTitan

Author: SamuelRiedel

dv/riscv_compliance/rtl/ibex_riscv_compliance.sv

@@ -160,57 +160,60 @@ module ibex_riscv_compliance (
       .DmHaltAddr       (32'h00000000      ),
       .DmExceptionAddr  (32'h00000000      )
     ) u_top (
-      .clk_i                  (clk_sys              ),
-      .rst_ni                 (rst_sys_n            ),
+      .clk_i                     (clk_sys              ),
+      .rst_ni                    (rst_sys_n            ),
 
-      .test_en_i              ('b0                  ),
-      .scan_rst_ni            (1'b1                 ),
-      .ram_cfg_i              ('b0                  ),
+      .test_en_i                 ('b0                  ),
+      .scan_rst_ni               (1'b1                 ),
+      .ram_cfg_icache_tag_i      ('b0                  ),
+      .ram_cfg_rsp_icache_tag_o  (                     ),
+      .ram_cfg_icache_data_i     ('b0                  ),
+      .ram_cfg_rsp_icache_data_o (                     ),
 
-      .hart_id_i              (32'b0                ),
+      .hart_id_i                 (32'b0                ),
       // First instruction executed is at 0x0 + 0x80
-      .boot_addr_i            (32'h00000000         ),
-
-      .instr_req_o            (host_req[CoreI]      ),
-      .instr_gnt_i            (host_gnt[CoreI]      ),
-      .instr_rvalid_i         (host_rvalid[CoreI]   ),
-      .instr_addr_o           (host_addr[CoreI]     ),
-      .instr_rdata_i          (host_rdata[CoreI]    ),
-      .instr_rdata_intg_i     (ibex_instr_rdata_intg),
-      .instr_err_i            (host_err[CoreI]      ),
-
-      .data_req_o             (host_req[CoreD]      ),
-      .data_gnt_i             (host_gnt[CoreD]      ),
-      .data_rvalid_i          (host_rvalid[CoreD]   ),
-      .data_we_o              (host_we[CoreD]       ),
-      .data_be_o              (host_be[CoreD]       ),
-      .data_addr_o            (host_addr[CoreD]     ),
-      .data_wdata_o           (host_wdata[CoreD]    ),
-      .data_wdata_intg_o      (                     ),
-      .data_rdata_i           (host_rdata[CoreD]    ),
-      .data_rdata_intg_i      (ibex_data_rdata_intg ),
-      .data_err_i             (host_err[CoreD]      ),
-
-      .irq_software_i         (1'b0                 ),
-      .irq_timer_i            (1'b0                 ),
-      .irq_external_i         (1'b0                 ),
-      .irq_fast_i             (15'b0                ),
-      .irq_nm_i               (1'b0                 ),
-
-      .scramble_key_valid_i   ('0                   ),
-      .scramble_key_i         ('0                   ),
-      .scramble_nonce_i       ('0                   ),
-      .scramble_req_o         (                     ),
-
-      .debug_req_i            ('b0                  ),
-      .crash_dump_o           (                     ),
-      .double_fault_seen_o    (                     ),
-
-      .fetch_enable_i         (ibex_pkg::IbexMuBiOn ),
-      .alert_minor_o          (                     ),
-      .alert_major_internal_o (                     ),
-      .alert_major_bus_o      (                     ),
-      .core_sleep_o           (                     )
+      .boot_addr_i               (32'h00000000         ),
+
+      .instr_req_o               (host_req[CoreI]      ),
+      .instr_gnt_i               (host_gnt[CoreI]      ),
+      .instr_rvalid_i            (host_rvalid[CoreI]   ),
+      .instr_addr_o              (host_addr[CoreI]     ),
+      .instr_rdata_i             (host_rdata[CoreI]    ),
+      .instr_rdata_intg_i        (ibex_instr_rdata_intg),
+      .instr_err_i               (host_err[CoreI]      ),
+
+      .data_req_o                (host_req[CoreD]      ),
+      .data_gnt_i                (host_gnt[CoreD]      ),
+      .data_rvalid_i             (host_rvalid[CoreD]   ),
+      .data_we_o                 (host_we[CoreD]       ),
+      .data_be_o                 (host_be[CoreD]       ),
+      .data_addr_o               (host_addr[CoreD]     ),
+      .data_wdata_o              (host_wdata[CoreD]    ),
+      .data_wdata_intg_o         (                     ),
+      .data_rdata_i              (host_rdata[CoreD]    ),
+      .data_rdata_intg_i         (ibex_data_rdata_intg ),
+      .data_err_i                (host_err[CoreD]      ),
+
+      .irq_software_i            (1'b0                 ),
+      .irq_timer_i               (1'b0                 ),
+      .irq_external_i            (1'b0                 ),
+      .irq_fast_i                (15'b0                ),
+      .irq_nm_i                  (1'b0                 ),
+
+      .scramble_key_valid_i      ('0                   ),
+      .scramble_key_i            ('0                   ),
+      .scramble_nonce_i          ('0                   ),
+      .scramble_req_o            (                     ),
+
+      .debug_req_i               ('b0                  ),
+      .crash_dump_o              (                     ),
+      .double_fault_seen_o       (                     ),
+
+      .fetch_enable_i            (ibex_pkg::IbexMuBiOn ),
+      .alert_minor_o             (                     ),
+      .alert_major_internal_o    (                     ),
+      .alert_major_bus_o         (                     ),
+      .core_sleep_o              (                     )
     );
 
   // SRAM block for instruction and data storage