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1 parent 96b705f commit 0a5e2fcCopy full SHA for 0a5e2fc
dv/cosim/spike_cosim.cc
@@ -1052,8 +1052,8 @@ bool SpikeCosim::pc_is_debug_ebreak(uint32_t pc) {
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// ebreak debug entry is controlled by the ebreakm (bit 15) and ebreaku (bit
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// 12) fields of DCSR. If the appropriate bit of the current privilege level
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// isn't set ebreak won't enter debug so return false.
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- if ((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0) ||
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- (processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0)) {
+ if (((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0)) ||
+ ((processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0))) {
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return false;
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}
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