We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 4c5dac7 commit deaa293Copy full SHA for deaa293
dv/cosim/spike_cosim.cc
@@ -1052,8 +1052,8 @@ bool SpikeCosim::pc_is_debug_ebreak(uint32_t pc) {
1052
// ebreak debug entry is controlled by the ebreakm (bit 15) and ebreaku (bit
1053
// 12) fields of DCSR. If the appropriate bit of the current privlege level
1054
// isn't set ebreak won't enter debug so return false.
1055
- if ((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0) ||
1056
- (processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0)) {
+ if (((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0)) ||
+ ((processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0))) {
1057
return false;
1058
}
1059
0 commit comments