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[doc] Clarify usage of data independent timing & branch prediction
As highlighted in the Branch Prediction documentation, this feature experimential. Clarify this in the data independent feature section. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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doc/03_reference/instruction_fetch.rst

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@@ -26,6 +26,8 @@ The interfaces of the icache module are the same as the prefetch buffer with two
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Firstly, a signal to enable the cache which is driven from a custom CSR.
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Secondly a signal to the flush the cache which is set every time a ``fence.i`` instruction is executed.
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.. _branch-prediction:
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Branch Prediction
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doc/03_reference/security.rst

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@@ -36,6 +36,8 @@ Software that has need of data independent timing may wish to disable the instru
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The instruction cache is controlled by the **icache_enable** bit in the **cpuctrl** register.
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Precise details of fetch timing will depend upon the memory system Ibex is connected to.
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If data independent timing is needed for branches, turn off the branch prediction feature as it is :ref:`experimental<branch-prediction>`.
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Dummy Instruction Insertion
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