Problem building the simple system #2345
Description
Hi,
I have installed all prerequisites according to the simple system instructions. However, the fusesoc command fails as shown below:
$ fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system $(util/ibex_config.py small fusesoc_opts)
INFO: Preparing lowrisc:dv:crypto_prince_ref:0.1
INFO: Preparing lowrisc:dv:dv_fcov_macros:0
INFO: Preparing lowrisc:dv:secded_enc:0
INFO: Preparing lowrisc:dv_verilator:ibex_pcounts:0
INFO: Preparing lowrisc:dv_verilator:simutil_verilator:0
INFO: Preparing lowrisc:ibex:ibex_pkg:0.1
INFO: Preparing lowrisc:prim:primgen:0.1
INFO: Preparing lowrisc:prim:ram_1p_pkg:0
INFO: Preparing lowrisc:prim:ram_2p_pkg:0
INFO: Preparing lowrisc:prim:util_get_scramble_params:0
INFO: Preparing lowrisc:tool:check_tool_requirements:0.1
INFO: Preparing lowrisc:dv:scramble_model:0
INFO: Preparing lowrisc:dv_verilator:memutil_dpi:0
INFO: Preparing lowrisc:lint:common:0.1
INFO: Preparing lowrisc:prim:prim_pkg:0.1
INFO: Preparing lowrisc:dv_verilator:memutil_dpi_scrambled:0
INFO: Preparing lowrisc:dv_verilator:memutil_verilator:0
INFO: Preparing lowrisc:prim:assert:0.1
INFO: Preparing lowrisc:prim:cipher_pkg:0.1
INFO: Preparing lowrisc:prim:clock_gating:0
INFO: Preparing lowrisc:prim:clock_mux2:0
INFO: Preparing lowrisc:prim:ram_1p:0
INFO: Preparing lowrisc:prim:ram_2p:0
INFO: Preparing lowrisc:prim:secded:0.1
INFO: Preparing lowrisc:ibex:ibex_icache:0.1
INFO: Preparing lowrisc:ibex:ibex_tracer:0.1
INFO: Preparing lowrisc:ibex:sim_shared:0
INFO: Preparing lowrisc:prim:and2:0
INFO: Preparing lowrisc:prim:buf:0
INFO: Preparing lowrisc:prim:cipher:0
INFO: Preparing lowrisc:prim:count:0
INFO: Preparing lowrisc:prim:flop:0
INFO: Preparing lowrisc:prim:lfsr:0.1
INFO: Preparing lowrisc:prim:util:0.1
INFO: Preparing lowrisc:prim:mubi:0.1
INFO: Preparing lowrisc:prim:onehot:0
INFO: Preparing lowrisc:prim:onehot_check:0
INFO: Preparing lowrisc:prim:ram_1p_adv:0.1
INFO: Preparing lowrisc:ibex:ibex_core:0.1
INFO: Preparing lowrisc:prim:ram_1p_scr:0.1
INFO: Preparing lowrisc:ibex:ibex_top:0.1
INFO: Preparing lowrisc:ibex:ibex_top_tracing:0.1
INFO: Preparing lowrisc:ibex:ibex_simple_system_core:0
INFO: Preparing lowrisc:ibex:ibex_simple_system:0
INFO: Generating lowrisc:prim:prim_pkg-impl:0.1
Creating prim_pkg.sv
Core file written to prim_pkg.core.
INFO: Generating lowrisc:prim:clock_gating-impl:0
Implementations for primitive clock_gating: xilinx, generic
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_clock_gating-impl_0/prim_clock_gating.sv
Creating core file for primitive clock_gating.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_clock_gating-impl_0/prim_clock_gating.core
INFO: Generating lowrisc:prim:clock_mux2-impl:0
Implementations for primitive clock_mux2: generic, xilinx
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_mux2.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_clock_mux2-impl_0/prim_clock_mux2.sv
Creating core file for primitive clock_mux2.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_clock_mux2-impl_0/prim_clock_mux2.core
INFO: Generating lowrisc:prim:ram_1p-impl:0
Implementations for primitive ram_1p: generic, badbit
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_ram_1p-impl_0/prim_ram_1p.sv
Creating core file for primitive ram_1p.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_ram_1p-impl_0/prim_ram_1p.core
INFO: Generating lowrisc:prim:ram_2p-impl:0
Implementations for primitive ram_2p: generic
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_2p.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_ram_2p-impl_0/prim_ram_2p.sv
Creating core file for primitive ram_2p.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_ram_2p-impl_0/prim_ram_2p.core
INFO: Generating lowrisc:prim:and2-impl:0
Implementations for primitive and2: generic, xilinx
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_and2.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_and2-impl_0/prim_and2.sv
Creating core file for primitive and2.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_and2-impl_0/prim_and2.core
INFO: Generating lowrisc:prim:buf-impl:0
Implementations for primitive buf: xilinx, generic
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_buf-impl_0/prim_buf.sv
Creating core file for primitive buf.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_buf-impl_0/prim_buf.core
INFO: Generating lowrisc:prim:flop-impl:0
Implementations for primitive flop: xilinx, generic
Inspecting generic module /home/mn/ibex/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv
[Errno 2] No such file or directory: 'verible-verilog-syntax'
Verible parser failed, using regex fallback instead.
Creating SystemVerilog module for abstract primitive
Abstract primitive written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_flop-impl_0/prim_flop.sv
Creating core file for primitive flop.
Core file written to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/generated/lowrisc_prim_flop-impl_0/prim_flop.core
INFO: Wrote dependency graph to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/lowrisc_ibex_ibex_simple_system_0.deps-after-generators.dot
INFO: Wrote Makefile fragment to /home/mn/ibex/build/lowrisc_ibex_ibex_simple_system_0/sim-verilator/core-deps.mk
INFO: Setting up project
INFO: Running pre_build script check_tool_requirements
INFO: Building simulation model
INFO: verilator -f lowrisc_ibex_ibex_simple_system_0.vc --trace --trace-fst --trace-structs --trace-params --trace-max-array 1024 -CFLAGS "-std=c++17 -Wall -DVM_TRACE_FMT_FST -DTOPLEVEL_NAME=ibex_simple_system -g" -LDFLAGS "-pthread -lutil -lelf" -Wall --unroll-count 72
ERROR: %Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_id_stage.sv:220:16: Signal unoptimizable: Circular combinational logic: 'ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.instr_executing_spec'
: ... note: In instance 'ibex_simple_system'
220 | logic instr_executing_spec;
| ^~~~~~~~~~~~~~~~~~~~
... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.043
... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_id_stage.sv:220:16: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.instr_executing_spec
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_id_stage.sv:781:3: Example path: ALWAYS
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_id_stage.sv:269:16: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.stall_alu
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:103:33: Example path: ASSIGNW
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:103:33: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.stall_id_i
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:453:3: Example path: ALWAYS
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:136:9: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.halt_if
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ASSIGNW
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.id_in_ready_o
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:453:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:140:9: Signal unoptimizable: Circular combinational logic: 'ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.special_req'
: ... note: In instance 'ibex_simple_system'
140 | logic special_req;
| ^~~~~~~~~~~
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:140:9: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.special_req
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:453:3: Example path: ALWAYS
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:136:9: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.halt_if
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ASSIGNW
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.id_in_ready_o
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:453:3: Example path: ALWAYS
%Warning-UNOPTFLAT: ../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Signal unoptimizable: Circular combinational logic: 'ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.id_in_ready_o'
: ... note: In instance 'ibex_simple_system'
44 | output logic id_in_ready_o,
| ^~~~~~~~~~~~~
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.id_in_ready_o
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:453:3: Example path: ALWAYS
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:136:9: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.halt_if
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ASSIGNW
../src/lowrisc_ibex_ibex_core_0.1/rtl/ibex_controller.sv:44:33: Example path: ibex_simple_system.u_top.u_ibex_top.u_ibex_core.id_stage_i.controller_i.id_in_ready_o
%Error: Exiting due to 3 warning(s)
make: *** [Makefile:16: Vibex_simple_system.mk] Error 1
ERROR: Failed to build lowrisc:ibex:ibex_simple_system:0 : '['make', '-j', '12']' exited with an error: 2
I have installed Verilator from the source. See below that the command exists:
$ which verilator
/usr/local/bin/verilator
$ find /usr/local/bin/ -name "verilator*"
/usr/local/bin/verilator_gantt
/usr/local/bin/verilator_profcfunc
/usr/local/bin/verilator_coverage_bin_dbg
/usr/local/bin/verilator_bin
/usr/local/bin/verilator_coverage
/usr/local/bin/verilator_bin_dbg
/usr/local/bin/verilator
I don't understand errors like No such file or directory: 'verible-verilog-syntax'. Any idea about that?