diff --git a/doc/02_user/integration.rst b/doc/02_user/integration.rst index cc3c59c84d..c002de571f 100644 --- a/doc/02_user/integration.rst +++ b/doc/02_user/integration.rst @@ -34,7 +34,7 @@ Primitives ---------- Ibex uses a number of primitive modules (that are held outside the :file:`rtl/` which contains the Ibex RTL). -Full implementations of these primitives are provided in the Ibex repository but implementors may wish to provide their own implementations. +Full implementations of these primitives are provided in the Ibex repository but implementers may wish to provide their own implementations. Some of the primitives are only used for specific Ibex configurations so can be ignored/removed if you're not using one of those configurations. The mandatory primitives (used by all configurations) are: @@ -55,7 +55,7 @@ The configuration dependent primitives are: Required where ``SecureIbex == 1``. * ``prim_onehot_check`` - Checks a onehot signal is correct, for detecting fault injection attacks. Required where ``SecureIbex == 1``. - * ``prim_secded_X`` - Various primitives to encode and decode SECDED (single error correct, double error detect) error detection and correction codes. + * ``prim_secded_X`` - Various primitives to encode and decode SECDED (Single Error Correct, Double Error Detect) error detection and correction codes. Required where ``SecureIbex == 1``. Primitives exclusively used by other primitives: @@ -207,7 +207,7 @@ Parameters +------------------------------+---------------------+------------+-----------------------------------------------------------------------+ | ``ICache`` | bit | 0 | Enable instruction cache instead of prefetch buffer | +------------------------------+---------------------+------------+-----------------------------------------------------------------------+ -| ``ICacheECC`` | bit | 0 | Enable SECDED ECC protection in ICache (if ICache == 1) | +| ``ICacheECC`` | bit | 0 | Enable SECDED ECC protection in ICache (if ICache == 1) | +------------------------------+---------------------+------------+-----------------------------------------------------------------------+ | ``ICacheScramble`` | bit | 0 | Enabling this parameter replaces tag and data RAMs of ICache with | | | | | scrambling RAM primitives. | diff --git a/doc/03_reference/exception_interrupts.rst b/doc/03_reference/exception_interrupts.rst index ca8480bbad..028f9b00ab 100644 --- a/doc/03_reference/exception_interrupts.rst +++ b/doc/03_reference/exception_interrupts.rst @@ -11,7 +11,7 @@ Interrupts are handled in vectored mode, i.e., the core jumps to the base addres Upon executing an MRET instruction, the core jumps to the program counter previously saved in the ``mepc`` CSR and restores ``mstatus``.MPIE to ``mstatus``.MIE. The base address of the vector table is initialized to the boot address (must be aligned to 256 bytes, i.e., its least significant byte must be 0x00) when the core is booting. -The base address can be changed after bootup by writing to the ``mtvec`` CSR. +The base address can be changed after boot-up by writing to the ``mtvec`` CSR. For more information, see the :ref:`cs-registers` documentation. The core starts fetching at the address made by concatenating the most significant 3 bytes of the boot address and the reset value (0x80) as the least significant byte. diff --git a/doc/03_reference/icache.rst b/doc/03_reference/icache.rst index 48e238728d..8e7f4455a4 100644 --- a/doc/03_reference/icache.rst +++ b/doc/03_reference/icache.rst @@ -64,7 +64,7 @@ The following table describes the available configuration parameters. Performance notes ----------------- -Note that although larger cache line sizes allow for better area efficiency (lower tagram area overhead), there is a performance penalty. +Note that although larger cache line sizes allow for better area efficiency (lower tag-RAM area overhead), there is a performance penalty. When the core branches to an address that is not aligned to the bottom of a cache line (and the request misses in the cache), the I$ will attempt to fetch this address first from the bus. The I$ will then fetch the rest of the remaining beats of data in wrapping address order to complete the cache line (in order to allocate it to the cache). While these lower addresses are being fetched, the core is starved of data. @@ -77,7 +77,7 @@ RAM Arrangement --------------- The data RAMs are arranged as ``NumWays`` banks of ``LineSize`` width. -If ECC is configured, the tag and data banks will be wider to accomodate the extra checkbits. +If ECC is configured, the tag and data banks will be wider to accommodate the extra checkbits. Indicative RAM sizes for common configurations are given in the table below: diff --git a/doc/03_reference/performance_counters.rst b/doc/03_reference/performance_counters.rst index c48ef0cc9f..35c347cd62 100644 --- a/doc/03_reference/performance_counters.rst +++ b/doc/03_reference/performance_counters.rst @@ -138,7 +138,7 @@ The remaining event selector CSRs are tied to 0, i.e., no events are counted by FPGA Targets ------------ -For FPGA targets the performance counters constitute a particularily large structure. +For FPGA targets the performance counters constitute a particularly large structure. Implementing the maximum 29 event counters 32, 48 and 64 bit wide results in relative logic utilizations of the core of 100%, 111% and 129% respectively. The relative numbers of flip-flops are 100%, 125% and 150%. It is recommended to implement event counters of 32 bit width where possible. diff --git a/doc/03_reference/register_file.rst b/doc/03_reference/register_file.rst index 0cf00992ba..57179b298c 100644 --- a/doc/03_reference/register_file.rst +++ b/doc/03_reference/register_file.rst @@ -28,7 +28,8 @@ FPGA Register File The FPGA register file leverages synchronous-write / asynchronous-read RAM design elements, where available on FPGA targets. -For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives. Using this design with a Xilinx Artya7-100 FPGA conserves around 600 Logic LUTs and 1000 flip-flops at the expense of 48 LUTRAMs for the 31-entry register file as compared to the flip-flop-based register file. +For Xilinx FPGAs, synthesis results in an implementation using RAM32M primitives. +Using this design with a Xilinx Arty A7-100 FPGA conserves around 600 Logic LUTs and 1000 flip-flops at the expense of 48 LUTRAMs for the 31-entry register file as compared to the flip-flop-based register file. This makes it the **first choice for FPGA synthesis**. diff --git a/doc/03_reference/security.rst b/doc/03_reference/security.rst index 52a62af50b..ac5dee7666 100644 --- a/doc/03_reference/security.rst +++ b/doc/03_reference/security.rst @@ -61,7 +61,7 @@ Other values of **dummy_instr_mask** are legal, but will have a less predictable The interval between instruction insertion is randomized in the core using an LFSR. The initial seed and output permutation for this LFSR can be set using parameters from the top-level of Ibex. -Sofware can periodically re-seed this LFSR with true random numbers (if available) via the **secureseed** CSR. +Software can periodically re-seed this LFSR with true random numbers (if available) via the **secureseed** CSR. This will make the insertion interval of dummy instructions much harder for an attacker to predict. Note that the dummy instruction feature inserts multiply and divide instructions. diff --git a/doc/03_reference/verification_stages.rst b/doc/03_reference/verification_stages.rst index 74f4c3e303..9bc4a6050d 100644 --- a/doc/03_reference/verification_stages.rst +++ b/doc/03_reference/verification_stages.rst @@ -97,7 +97,7 @@ V2 Checklist +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Coverage | FPV_COI_COVERAGE_V2 | N/A | No formal applied for non-security features in Ibex. | +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| Integration | PRE_VERIFIED_SUB_MODULES_V2 | Complete | ICache is verified in a seperate testbench. | +| Integration | PRE_VERIFIED_SUB_MODULES_V2 | Complete | ICache is verified in a separate testbench. | +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Issues | NO_HIGH_PRIORITY_ISSUES_PENDING | Complete | | +---------------+-------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ @@ -178,7 +178,7 @@ The mapping between countermeasures and tests is given below | | This test produces double faults, which are checked by an assertion. | | | ``chip_sw_rv_core_ibex_double_fault`` top-level test in OpenTitan demonstrates escalation on a double fault | +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| ICACHE.MEM.SCRAMBLE | No explicit testing, the scrambling memory primitive is seperately verified within OpenTitan. | +| ICACHE.MEM.SCRAMBLE | No explicit testing, the scrambling memory primitive is separately verified within OpenTitan. | | | Assertions in the OpenTitan specific ``rv_core_ibex`` wrapper ensure a newly requested scramble key is correctly applied to the scrambling memories. | | | The ``rv_core_ibex_icache_invalidate_test`` OpenTitan top-level test covers assertions within the OpenTitan specific ``rv_core_ibex`` wrapper that check that a ``FENCE.I`` results in an icache scramble key request and that the returned key is correctly supplied to the scrambling memory primitives. | +--------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ diff --git a/dv/cosim/spike_cosim.cc b/dv/cosim/spike_cosim.cc index 336d520948..4201ef6a47 100644 --- a/dv/cosim/spike_cosim.cc +++ b/dv/cosim/spike_cosim.cc @@ -166,7 +166,7 @@ bool SpikeCosim::backdoor_read_mem(uint32_t addr, size_t len, // The state.last_inst_pc also remains with the sentinel value PC_INVALID. // - If we catch a trap_t&, then the take_trap() fn updates the state of the // processor, and when we call step() again we start executing in the new -// context of the trap (trap andler, new MSTATUS, debug rom, etc. etc.) +// context of the trap (trap handler, new MSTATUS, debug rom, etc. etc.) bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc, bool sync_trap, bool suppress_reg_write) { assert(write_reg < 32); @@ -196,7 +196,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc, // we do the stop, so we can restore it after the step (as spike won't // suppressed the register write). // - // First check retired instruciton to ensure load suppression is correct + // First check retired instruction to ensure load suppression is correct if (!check_suppress_reg_write(write_reg, pc, suppressed_write_reg)) { return false; } @@ -228,7 +228,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc, // - PC_INVALID == true // - current state is that of the trapping instruction // DUT - // - If the dut encounters an async trap (which can be thought of as occuring + // - If the dut encounters an async trap (which can be thought of as occurring // between instructions), an rvfi_item will be generated for the the first // retired instruction of the trap handler. // - If the dut encounters a sync trap, an rvfi_item will be generated for the @@ -626,7 +626,7 @@ void SpikeCosim::early_interrupt_handle() { // Ibex splits misaligned accesses into two separate requests. They // independently undergo PMP access checks. It is possible for one to fail (so -// no request produced for that half of the access) whilst the other successed +// no request produced for that half of the access) whilst the other succeeds // (producing a request for that half of the access). // // Spike splits misaligned accesses up into bytes and will apply PMP access @@ -1022,7 +1022,7 @@ SpikeCosim::check_mem_result_e SpikeCosim::check_mem_access( } // For any misaligned access that sees an error immediately indicate to - // spike the error has occured, so ensure the top pending access gets + // spike the error has occurred, so ensure the top pending access gets // removed. pending_access_done = true; } @@ -1048,7 +1048,7 @@ bool SpikeCosim::pc_is_debug_ebreak(uint32_t pc) { uint32_t dcsr = processor->get_csr(CSR_DCSR); // ebreak debug entry is controlled by the ebreakm (bit 15) and ebreaku (bit - // 12) fields of DCSR. If the appropriate bit of the current privlege level + // 12) fields of DCSR. If the appropriate bit of the current privilege level // isn't set ebreak won't enter debug so return false. if ((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0) || (processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0)) { diff --git a/dv/cosim/spike_cosim.h b/dv/cosim/spike_cosim.h index a4baad5dc2..9526d93880 100644 --- a/dv/cosim/spike_cosim.h +++ b/dv/cosim/spike_cosim.h @@ -62,7 +62,7 @@ class SpikeCosim : public simif_t, public Cosim { uint32_t pending_iside_err_addr; typedef enum { - kCheckMemOk, // Checks passed and access succeded in RTL + kCheckMemOk, // Checks passed and access succeeded in RTL kCheckMemCheckFailed, // Checks failed kCheckMemBusError // Checks passed, but access generated bus error in RTL } check_mem_result_e; diff --git a/dv/cs_registers/model/base_register.cc b/dv/cs_registers/model/base_register.cc index a0716f5d73..44da7bf9c4 100644 --- a/dv/cs_registers/model/base_register.cc +++ b/dv/cs_registers/model/base_register.cc @@ -65,7 +65,7 @@ bool BaseRegister::ProcessTransaction(bool *match, RegisterTransaction *trans) { // else if (read_val != trans->csr_rdata) { // std::cout << "MCycle(H) incrementing as expected" << std::endl; //} - // Don't panic about MCycle(H) incremeting, this is expected behavior as + // Don't panic about MCycle(H) incrementing, this is expected behavior as // the clock is always running. Silently ignore mismatches for MCycle(H). } else if (read_val != trans->csr_rdata) { std::cout << "Error, transaction:" << std::endl; diff --git a/dv/formal/check/top.sv b/dv/formal/check/top.sv index 87dbbacdff..1b96550517 100644 --- a/dv/formal/check/top.sv +++ b/dv/formal/check/top.sv @@ -80,7 +80,7 @@ module top import ibex_pkg::*; #( input logic irq_timer_i, input logic irq_external_i, input logic [14:0] irq_fast_i, - input logic irq_nm_i, // non-maskeable interrupt + input logic irq_nm_i, // non-maskable interrupt // Scrambling Interface input logic scramble_key_valid_i, @@ -435,7 +435,7 @@ assign ex_is_checkable_csr = ~( `undef INSTR `define INSTR wbexc_decompressed_instr -// Illegal instructions arent checkable unless the relevant specifications are present. +// Illegal instructions aren't checkable unless the relevant specifications are present. logic can_check_illegal; assign can_check_illegal = `SPEC_ILLEGAL & `SPEC_CSR & `SPEC_MRET & `SPEC_WFI; diff --git a/dv/formal/spec/main.sail b/dv/formal/spec/main.sail index 794e15a304..2629512e82 100644 --- a/dv/formal/spec/main.sail +++ b/dv/formal/spec/main.sail @@ -13,7 +13,7 @@ main is equivalent to the Sail step function, it has some differences however: 1. It's difficult to compare IRQ handling, since ibex takes them later than the Sail would. This is OK since it's not really fair to enforce that IRQs are handled between any two specific instructions, so long as it is eventually. 2. The three modes are a useful case analysis we can make. This means that to prove correctness of an I-Type instruction, for example, we - can more easily seperate out the check for instruction fetch correctness, which makes things faster and avoids repeated work. + can more easily separate out the check for instruction fetch correctness, which makes things faster and avoids repeated work. */ union FetchResult = { @@ -48,7 +48,7 @@ function main(insn_bits, mode) : (bits(32), MainMode) -> MainResult = { let irq = dispatchInterrupt(cur_privilege); let f : FetchResult = altFetch(insn_bits[15..0], insn_bits[31..16]); - + let res : MainResult = match mode { MAIN_IDEX => { match decompress(insn) { diff --git a/dv/formal/spec/spec_api.sv b/dv/formal/spec/spec_api.sv index ca2fcafe37..12555aa30f 100644 --- a/dv/formal/spec/spec_api.sv +++ b/dv/formal/spec/spec_api.sv @@ -5,7 +5,7 @@ // SPDX-License-Identifier: Apache-2.0 /* -This module contains the actual instance of the specification. It's quite ugly. Mostly it's just forwaring things to +This module contains the actual instance of the specification. It's quite ugly. Mostly it's just forwarding things to different names and ignoring registers we don't care about. */ diff --git a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv index 5fd0685e29..dec8074638 100644 --- a/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv +++ b/dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv @@ -347,7 +347,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard; endfunction : final_phase // If the UVM_EXIT action is triggered (such as by reaching max_quit_count), this callback is run. - // This ensures proper cleanup, such as commiting the logfile to disk. + // This ensures proper cleanup, such as committing the logfile to disk. function void pre_abort(); cleanup_cosim(); endfunction diff --git a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv index 614216f646..05895facc1 100644 --- a/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv +++ b/dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv @@ -178,7 +178,7 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item); endfunction // Read a word of DATA_WIDTH bits from addr. - // Handle reads fromm uninit memory as follows: + // Handle reads from uninit memory as follows: // - DMEM : return a random value // - IMEM : return {2{C.unimp}} protected function logic [DATA_WIDTH-1:0] read(bit [ADDR_WIDTH-1:0] addr, diff --git a/dv/uvm/core_ibex/common/irq_agent/irq_if.sv b/dv/uvm/core_ibex/common/irq_agent/irq_if.sv index 92de1301c0..116d4c1fd8 100644 --- a/dv/uvm/core_ibex/common/irq_agent/irq_if.sv +++ b/dv/uvm/core_ibex/common/irq_agent/irq_if.sv @@ -8,7 +8,7 @@ interface irq_if(input clk); logic irq_timer; logic irq_external; logic [14:0] irq_fast; - logic irq_nm; // non-maskeable interrupt + logic irq_nm; // non-maskable interrupt clocking driver_cb @(posedge clk); default output negedge; diff --git a/dv/uvm/core_ibex/directed_tests/README.md b/dv/uvm/core_ibex/directed_tests/README.md index cb82814d9e..5a68cc7df0 100644 --- a/dv/uvm/core_ibex/directed_tests/README.md +++ b/dv/uvm/core_ibex/directed_tests/README.md @@ -5,7 +5,7 @@ This directory contains the custom directed tests as well as scripts and headers Currently following open source test suites are vendored: - [riscv-tests](https://github.com/riscv-software-src/riscv-tests) - [riscv-arch-tests](https://github.com/riscv-non-isa/riscv-arch-test) -- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an opensource [repo](https://github.com/joxie/riscv-isa-sim)) +- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an open-source [repo](https://github.com/joxie/riscv-isa-sim)) ## Generating test list diff --git a/dv/uvm/core_ibex/directed_tests/gen_testlist.py b/dv/uvm/core_ibex/directed_tests/gen_testlist.py index 209904ead2..c922608140 100644 --- a/dv/uvm/core_ibex/directed_tests/gen_testlist.py +++ b/dv/uvm/core_ibex/directed_tests/gen_testlist.py @@ -1,6 +1,6 @@ #!/usr/bin/env python3 """ -Generating testlists for following opensource test suites +Generating testlists for following open-source test suites - riscv-tests - riscv-arch-tests - ePMP directed tests diff --git a/dv/uvm/core_ibex/env/core_ibex_scoreboard.sv b/dv/uvm/core_ibex/env/core_ibex_scoreboard.sv index b84e8dd927..bb0d2ae920 100644 --- a/dv/uvm/core_ibex/env/core_ibex_scoreboard.sv +++ b/dv/uvm/core_ibex/env/core_ibex_scoreboard.sv @@ -71,7 +71,7 @@ class core_ibex_scoreboard extends uvm_scoreboard; end end // Latch the 'double_fault_seen_o' signal to catch the fault. - // The single pulse may be receieved sometime before the rvfi_seq_item + // The single pulse may be received sometime before the rvfi_seq_item // corresponding to the faulting instruction is generated. Hence we // latch that pulse when it is seen, and then reset above when the // seq_item arrives. diff --git a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv index 3c844da742..e3e2fcf2f1 100644 --- a/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv +++ b/dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv @@ -310,7 +310,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; ( assign instr_id_matches_trigger_d = id_stage_i.controller_i.trigger_match_i && id_stage_i.controller_i.fcov_debug_entry_if; - // Delay instruction matching trigger point since it is catched in IF stage. + // Delay instruction matching trigger point since it is cached in IF stage. // We would want to cross it with decoded instruction categories and it does not matter // when exactly we are hitting the condition. always @(posedge clk_i or negedge rst_ni) begin diff --git a/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv b/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv index 9d6f290b4f..0d71913abb 100644 --- a/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv +++ b/dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv @@ -255,7 +255,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( csr_pmp_cfg[i_region].mode != PMP_MODE_OFF && !(fcov_access_attempted_into_dm[PMP_I])) { - // Will never see a succesful exec access when execute is disallowed + // Will never see a successful exec access when execute is disallowed illegal_bins illegal_allow_exec = // Ensuring MML is low and we are not in a X allowed configuration (binsof(cp_region_priv_bits) intersect {NONE, R, W, WR, L, LR, LW, LWR} && @@ -313,7 +313,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( csr_pmp_cfg[i_region].mode != PMP_MODE_OFF && !(fcov_access_attempted_into_dm[PMP_I2])) { - // Will never see a succesful exec access when execute is disallowed + // Will never see a successful exec access when execute is disallowed illegal_bins illegal_allow_exec = // Ensuring MML is low and we are not in a X allowed configuration (binsof(cp_region_priv_bits) intersect {NONE, R, W, WR, L, LR, LW, LWR} && @@ -371,7 +371,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( csr_pmp_cfg[i_region].mode != PMP_MODE_OFF && !(fcov_access_attempted_into_dm[PMP_D])) { - // Will never see a succesful read access when read is disallowed + // Will never see a successful read access when read is disallowed illegal_bins illegal_allow_read = // Ensuring MML is low and we are not in a R allowed configuration (binsof(cp_region_priv_bits) intersect {NONE, W, X, XW, L, LW, LX, LXW} && @@ -415,7 +415,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( binsof(cp_req_type_dside) intersect {PMP_ACC_READ} && binsof(pmp_dside_req_err) intersect {1}); - // Will never see a succesful write access when write is disallowed + // Will never see a successful write access when write is disallowed illegal_bins illegal_allow_write = // Ensuring MML is low and we are not in a W allowed configuration (binsof(cp_region_priv_bits) intersect {NONE, R, X, XR, L, LR, LX, LXR} && @@ -613,7 +613,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( pmp_iside_nomatch_cross : cross cp_req_type_iside, cp_priv_lvl_iside, pmp_iside_req_err, cp_mmwp, cp_mml iff (pmp_iside_nomatch) { - // Will never see a succesful exec access when execute is disallowed + // Will never see a successful exec access when execute is disallowed illegal_bins illegal_user_allow_exec = // In User mode - no match case, we should always deny (binsof(cp_priv_lvl_iside) intersect {PRIV_LVL_U} && @@ -639,7 +639,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( pmp_iside2_nomatch_cross : cross cp_req_type_iside2, cp_priv_lvl_iside2, pmp_iside2_req_err, cp_mmwp, cp_mml iff (pmp_iside2_nomatch) { - // Will never see a succesful exec access when execute is disallowed + // Will never see a successful exec access when execute is disallowed illegal_bins illegal_user_allow_exec = // In User mode - no match case, we should always deny (binsof(cp_priv_lvl_iside2) intersect {PRIV_LVL_U} && @@ -666,7 +666,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #( cross cp_req_type_dside, cp_priv_lvl_dside, pmp_dside_req_err, cp_mmwp, cp_mml iff (pmp_dside_nomatch) { - // Will never see a succesful write/read access when it should be denied + // Will never see a successful write/read access when it should be denied illegal_bins illegal_machine_allow_wr = // Deny WR when MMWP = 1 in Machine mode (binsof(cp_priv_lvl_dside) intersect {PRIV_LVL_M} && diff --git a/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv b/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv index 244d80fa39..ed160326cb 100644 --- a/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv +++ b/dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv @@ -112,7 +112,7 @@ class ibex_asm_program_gen extends riscv_asm_program_gen; endfunction // Re-define gen_test_done() to override the base-class with an empty implementation. - // Then, our own overrided gen_program() can append new test_done code. + // Then, our own overriding gen_program() can append new test_done code. virtual function void gen_test_done(); // empty endfunction diff --git a/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv b/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv index 36a13df404..aeebfd0ef5 100644 --- a/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv +++ b/dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv @@ -51,7 +51,7 @@ class ibex_breakpoint_stream extends riscv_directed_instr_stream; la_instr.rd = cfg.gpr[1]; // Create the ebreak insn which will cause us to enter debug mode, and run the - // special code in the debugrom. + // special code in the debug ROM. ebreak_insn = riscv_instr::get_instr(EBREAK); // Add the instructions into the stream. diff --git a/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py b/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py index cb5372d03e..6b9ba47c98 100644 --- a/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py +++ b/dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py @@ -206,7 +206,7 @@ def check_ibex_uvm_log(uvm_log): # the test result so ignore any lines after the test result is seen for # 'UVM_ERROR' checking. If the loop terminated immediately when a test # result was seen it would miss issues where the test result is - # (erronously) repeated multiple times with different results. + # (erroneously) repeated multiple times with different results. test_result_seen = False for linenum, line in enumerate(log, 1): diff --git a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv index 0788f6c303..15b1e697c9 100644 --- a/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv +++ b/dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv @@ -107,10 +107,10 @@ int kernel_stack_len = 5000; int kernel_program_instr_cnt = 400; // ---------------------------------------------------------------------------- -// Previleged CSR implementation +// Privileged CSR implementation // ---------------------------------------------------------------------------- -// Implemented previlieged CSR list +// Implemented privileged CSR list // TODO: Bring back commented out CSRs, these are currently removed as they can // cause co-sim mismatches. These must be investigated and fixed const privileged_reg_t implemented_csr[] = { diff --git a/dv/uvm/core_ibex/scripts/compile_tb.py b/dv/uvm/core_ibex/scripts/compile_tb.py index 2adcfa4a5c..a4040e7f6e 100755 --- a/dv/uvm/core_ibex/scripts/compile_tb.py +++ b/dv/uvm/core_ibex/scripts/compile_tb.py @@ -24,7 +24,7 @@ def _get_iss_pkgconfig_flags(specifiers: List[str], iss_pc: List[str], simulator: str) -> str: all_tokens = [] - # Seperate pkg-config calls for each specifier as combining them has been + # Separate pkg-config calls for each specifier as combining them has been # observed misbehaving on CentOS 7 # Generate a list of tokens for each call, and append it to the all_tokens variable for s in specifiers: diff --git a/dv/uvm/core_ibex/scripts/merge_cov.py b/dv/uvm/core_ibex/scripts/merge_cov.py index a9a84e7aa8..738e52434f 100755 --- a/dv/uvm/core_ibex/scripts/merge_cov.py +++ b/dv/uvm/core_ibex/scripts/merge_cov.py @@ -66,7 +66,7 @@ def merge_cov_xlm(md: RegressionMetadata, cov_dbs: Set[pathlib.Path]) -> int: imc_cmd = ["imc", "-64bit", "-licqueue"] - # Update the metdadata file with the commands we're about to run + # Update the metadata file with the commands we're about to run with LockedMetadata(md.dir_metadata, __file__) as md: md.cov_merge_db_list = md.dir_cov / 'cov_db_runfile' diff --git a/dv/uvm/core_ibex/scripts/report_lib/util.py b/dv/uvm/core_ibex/scripts/report_lib/util.py index 55cb1d74d9..4fa671a6b0 100644 --- a/dv/uvm/core_ibex/scripts/report_lib/util.py +++ b/dv/uvm/core_ibex/scripts/report_lib/util.py @@ -77,7 +77,7 @@ def parse_xcelium_cov_report(cov_report: str) -> Dict[str, Dict[str, Dict[str, i } The top-level dictionary gives per-module info. For each module coverage is - seperated into a number of metrics. Each metric can be one of two types: + separated into a number of metrics. Each metric can be one of two types: 1. covered - Two integers, 'total' giving total number of things to cover and 'covered' giving the number that are covered. 2. average - Single integer, 'average' giving the average coverage diff --git a/dv/uvm/core_ibex/scripts/scripts_lib.py b/dv/uvm/core_ibex/scripts/scripts_lib.py index 77eaef6f37..a30588f5e4 100644 --- a/dv/uvm/core_ibex/scripts/scripts_lib.py +++ b/dv/uvm/core_ibex/scripts/scripts_lib.py @@ -263,14 +263,14 @@ class testdata_cls(): """Baseclass for testdata to hold common methods.... Objects inheriting from this can easily import/export - themselves to files, allowing data to gain continuinty between + themselves to files, allowing data to gain continuity between different phases of the regression and testing process """ @classmethod @typechecked def construct_from_pickle(cls, metadata_pickle: pathlib.Path): - """Allow easy contruction of the data-structure from a file.""" + """Allow easy construction of the data-structure from a file.""" trr = cls() logger.debug(f"Constructing object from data in {metadata_pickle}") with metadata_pickle.open('rb') as handle: diff --git a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv index 5ca14c0664..355f20dc20 100644 --- a/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv +++ b/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv @@ -191,7 +191,7 @@ module core_ibex_tb_top; // Data load/store vif connection assign data_mem_vif.reset = ~rst_n; - // Instruction fetch vif connnection + // Instruction fetch vif connection assign instr_mem_vif.reset = ~rst_n; assign instr_mem_vif.we = 0; assign instr_mem_vif.be = 0; @@ -368,13 +368,13 @@ module core_ibex_tb_top; unused_assert_connected = 1; end - // Disable the assertion for onhot check in case WrenCheck (set by SecureIbex) is enabled. + // Disable the assertion for onehot check in case WrenCheck (set by SecureIbex) is enabled. if (SecureIbex) begin : gen_disable_onehot_check assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check. unused_assert_connected = 1; end - // Disable the assertion for onhot check in case RdataMuxCheck (set by SecureIbex) is enabled. + // Disable the assertion for onehot check in case RdataMuxCheck (set by SecureIbex) is enabled. if (SecureIbex) begin : gen_disable_rdata_mux_check assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check. u_prim_onehot_check_raddr_a.unused_assert_connected = 1; diff --git a/dv/uvm/core_ibex/tests/core_ibex_base_test.sv b/dv/uvm/core_ibex/tests/core_ibex_base_test.sv index d9fc99f9da..f136373f1f 100644 --- a/dv/uvm/core_ibex/tests/core_ibex_base_test.sv +++ b/dv/uvm/core_ibex/tests/core_ibex_base_test.sv @@ -23,7 +23,7 @@ class core_ibex_base_test extends uvm_test; int unsigned timeout_in_cycles = 100000000; int unsigned max_quit_count = 1; // If no signature_addr handshake functionality is desired between the testbench and the generated - // code, the test will wait for the specifield number of cycles before starting stimulus + // code, the test will wait for the specified number of cycles before starting stimulus // sequences (irq and debug) int unsigned stimulus_delay = 800; bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] signature_data_q[$]; @@ -171,7 +171,7 @@ class core_ibex_base_test extends uvm_test; void'($value$plusargs("disable_spurious_dside_responses=%0d", disable_spurious_dside_responses)); - // Disable spurious reponses for non secure configs or when disabled through plusarg + // Disable spurious responses for non secure configs or when disabled through plusarg if ((secure_ibex == 0) || disable_spurious_dside_responses) begin cfg.enable_spurious_dside_responses = 0; end @@ -277,7 +277,7 @@ class core_ibex_base_test extends uvm_test; end endtask : handle_reset - // Watch for all of the different critera for test pass/failure here + // Watch for all of the different criteria for test pass/failure here virtual task wait_for_test_done(); longint timeout_timestamp, ts; bit result; diff --git a/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv index 1e4236c122..880e2dbebb 100644 --- a/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv +++ b/dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv @@ -52,7 +52,7 @@ class core_base_new_seq #(type REQ = uvm_sequence_item) extends uvm_sequence #(R endfunction virtual task pre_body(); - // Randomize once before starting to ensure all unininitialized rand variables have a valid starting value + // Randomize once before starting to ensure all uninitialized rand variables have a valid starting value this.randomize(); endtask: pre_body @@ -204,7 +204,7 @@ endclass class memory_error_seq extends core_base_new_seq#(ibex_mem_intf_seq_item); core_ibex_vseq vseq; rand bit choose_side; - // When set skip error injection if Ibex is currently handling an exception (incluing IRQs) + // When set skip error injection if Ibex is currently handling an exception (including IRQs) bit skip_on_exc = 1'b0; error_type_e err_type = PickErr; diff --git a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv index bf4181af6f..526dfbd552 100644 --- a/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv +++ b/dv/uvm/core_ibex/tests/core_ibex_test_lib.sv @@ -1860,7 +1860,7 @@ class core_ibex_mem_error_test extends core_ibex_directed_test; // // We don't terminate immediately as sometimes the test hits an illegal instruction exception // but finds its way back to generated code and terminates as usual. Sometimes it doesn't. The - // treshold allows for normal test termination in cases where that's possible. + // threshold allows for normal test termination in cases where that's possible. if (!cfg.enable_mem_intg_err) begin return; end diff --git a/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv b/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv index 4089988a66..8c95bd3923 100644 --- a/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv +++ b/dv/uvm/icache/dv/env/ibex_icache_env_cov.sv @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 /** - * Covergoups that are dependent on run-time parameters that may be available + * Covergroups that are dependent on run-time parameters that may be available * only in build_phase can be defined here * Covergroups may also be wrapped inside helper classes if needed. */ diff --git a/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv b/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv index 8b66823c1e..15b69fb22e 100644 --- a/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv +++ b/dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv @@ -34,7 +34,7 @@ class ibex_icache_core_monitor extends dv_base_monitor #( disable fork; endtask - // collect transactions forever - already forked in dv_base_moditor::run_phase + // collect transactions forever - already forked in dv_base_monitor::run_phase virtual protected task collect_trans(); ibex_icache_core_bus_item trans; logic last_inval = 0; diff --git a/dv/uvm/icache/dv/prim_badbit/README.md b/dv/uvm/icache/dv/prim_badbit/README.md index 22aebb5076..689f913ab7 100644 --- a/dv/uvm/icache/dv/prim_badbit/README.md +++ b/dv/uvm/icache/dv/prim_badbit/README.md @@ -1,7 +1,7 @@ Badbit RAM ========== -This is an SRAM wrapper that allows a testbench to force bit errors onthe read interface. +This is an SRAM wrapper that allows a testbench to force bit errors on the read interface. This works as a dummy technology library. Instantiate it by adding setting `PRIM_DEFAULT_IMPL` to prim_pkg::ImplBadbit (see the README.md in the prim directory for details). diff --git a/dv/verilator/simple_system_cosim/README.md b/dv/verilator/simple_system_cosim/README.md index 61952613a9..3777ed0662 100644 --- a/dv/verilator/simple_system_cosim/README.md +++ b/dv/verilator/simple_system_cosim/README.md @@ -3,7 +3,7 @@ This augments the Ibex Simple System (`examples/simple_system`) to include the co-simulation system to check Ibex's execution. This runs Spike in lockstep with Ibex and checks each instruction Ibex retires matches what Spike has executed. -In addition all data memory accesses are checked against memory acceses Spike +In addition all data memory accesses are checked against memory accesses Spike has performed. More details on how the co-simulation works and how to build and run simple system with it included can be in found in the Ibex documentation under 'Co-simulation System' in the 'Ibex Reference Guide' section. @@ -20,7 +20,7 @@ mkdir build cd build # Configure and build spike -../configure --enable-commitlog --enable-misaligned --prefix=/opt/spike-cosim +../configure --enable-commitlog --enable-misaligned --prefix=/opt/spike-cosim # Installs in /opt/spike-cosim sudo make -j8 install @@ -33,7 +33,7 @@ cd # Build simulator fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim --RV32E=0 --RV32M=ibex_pkg::RV32MFast -# Build coremark test binary, with performance counter dump disabled. The +# Build coremark test binary, with performance counter dump disabled. The # co-simulator system doesn't produce matching performance counters in spike so # any read of those CSRs results in a mismatch and a failure. make -C ./examples/sw/benchmarks/coremark SUPPRESS_PCOUNT_DUMP=1 diff --git a/examples/simple_system/README.md b/examples/simple_system/README.md index 026bbb7c66..df8d0e660d 100644 --- a/examples/simple_system/README.md +++ b/examples/simple_system/README.md @@ -45,7 +45,7 @@ comes from replacing `small` in the command above with `opentitan`. Simple System related software can be found in `examples/sw/simple_system`. -To build the hello world example, from the Ibex reposistory root run: +To build the hello world example, from the Ibex repository root run: ``` make -C examples/sw/simple_system/hello_test diff --git a/examples/sw/benchmarks/coremark/ibex/core_portme.c b/examples/sw/benchmarks/coremark/ibex/core_portme.c index 704665cec2..26bc134ca8 100644 --- a/examples/sw/benchmarks/coremark/ibex/core_portme.c +++ b/examples/sw/benchmarks/coremark/ibex/core_portme.c @@ -133,7 +133,7 @@ void stop_time(void) { Actual value returned may be cpu cycles, milliseconds or any other value, as long as it can be converted to seconds by . This - methodology is taken to accomodate any hardware or simulated platform. The + methodology is taken to accommodate any hardware or simulated platform. The sample implementation returns millisecs by default, and the resolution is controlled by */ @@ -144,7 +144,7 @@ CORE_TICKS get_time(void) { /* Function : time_in_secs Convert the value returned by get_time to seconds. - The type is used to accomodate systems with no support for + The type is used to accommodate systems with no support for floating point. Default implementation implemented by the EE_TICKS_PER_SEC macro above. */ diff --git a/examples/sw/benchmarks/coremark/ibex/core_portme.h b/examples/sw/benchmarks/coremark/ibex/core_portme.h index 4117de4f42..00222b2b84 100644 --- a/examples/sw/benchmarks/coremark/ibex/core_portme.h +++ b/examples/sw/benchmarks/coremark/ibex/core_portme.h @@ -74,7 +74,7 @@ extern unsigned int _stack_start; To avoid compiler issues, define the data types that need to be used for 8b, 16b and 32b in . - *Imprtant* : + *Important* : ee_ptr_int needs to be the data type used to hold pointers, otherwise CoreMark may fail!!! */ @@ -175,7 +175,7 @@ typedef ee_u32 CORE_TICKS; #endif /* Variable : default_num_contexts - Not used for this simple port, must cintain the value 1. + Not used for this simple port, must contain the value 1. */ extern ee_u32 default_num_contexts; diff --git a/examples/sw/simple_system/common/link.ld b/examples/sw/simple_system/common/link.ld index 297ffc1a30..b1ea210df5 100644 --- a/examples/sw/simple_system/common/link.ld +++ b/examples/sw/simple_system/common/link.ld @@ -7,7 +7,7 @@ OUTPUT_ARCH(riscv) MEMORY { /* Change this if you'd like different sizes. Arty A7-100(35) has a maximum of 607.5KB(225KB) - BRAM space. Configuration below is for maximum BRAM capacity with Artya A7-35 while letting + BRAM space. Configuration below is for maximum BRAM capacity with Arty A7-35 while letting CoreMark run (.vmem of 152.8KB). */ ram : ORIGIN = 0x00100000, LENGTH = 0x30000 /* 192 kB */ diff --git a/rtl/ibex_alu.sv b/rtl/ibex_alu.sv index cfb44ac736..563f571cf4 100644 --- a/rtl/ibex_alu.sv +++ b/rtl/ibex_alu.sv @@ -203,7 +203,7 @@ module ibex_alu #( // // Funnel Shifts // ------------- - // For funnel shifs, operand_a_i is tied to rs1 in the first cycle and rs3 in the + // For funnel shifts, operand_a_i is tied to rs1 in the first cycle and rs3 in the // second cycle. operand_b_i is always tied to rs2. The order of applying the shift amount or // its complement is determined by bit [5] of shift_amt. // @@ -484,7 +484,7 @@ module ibex_alu #( // butterfly network control signals. The adders in the intermediate value adder tree thus need // not be full 5-bit adders. We leave the optimization to the synthesis tools. // - // Consider the following 8-bit example for illustraton. + // Consider the following 8-bit example for illustration. // // let bitcnt_bits = 8'babcdefgh. // @@ -783,7 +783,7 @@ module ibex_alu #( end ALU_XPERM_B: begin - // Convert byte to nibble indicies. + // Convert byte to nibble indices. for (int b = 0; b < 4; b++) begin sel[b*2 + 0] = {sel_b[b], 1'b0}; sel[b*2 + 1] = {sel_b[b], 1'b1}; @@ -863,7 +863,7 @@ module ibex_alu #( // where P denotes lower 32 bits of the corresponding CRC polynomial, rev(a) the bit reversal // of a, n = 8,16, or 32 for .b, .h, .w -variants. {a, b} denotes bit concatenation. // - // Using barret reduction, one can show that + // Using Barrett reduction, one can show that // // M(x) mod P(x) = R(x) = // (M(x) * x**n) & {deg(P(x)'{1'b1}}) ^ (M(x) x**-(deg(P(x) - n)) cx mu(x) cx P(x), diff --git a/rtl/ibex_controller.sv b/rtl/ibex_controller.sv index 1b2666c0bc..1803c44d7c 100644 --- a/rtl/ibex_controller.sv +++ b/rtl/ibex_controller.sv @@ -47,7 +47,7 @@ module ibex_controller #( input logic instr_exec_i, // Execution control, when clear ID/EX // stage stops accepting instructions from // IF - // to prefetcher + // to prefetch output logic instr_req_o, // start fetching instructions output logic pc_set_o, // jump to address set by pc_mux output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector @@ -76,7 +76,7 @@ module ibex_controller #( input logic irq_pending_i, // interrupt request pending input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with // mie CSR - input logic irq_nm_ext_i, // non-maskeable interrupt + input logic irq_nm_ext_i, // non-maskable interrupt output logic nmi_mode_o, // core executing NMI handler // debug signals @@ -248,7 +248,7 @@ module ibex_controller #( // Note that with the writeback stage store/load errors occur on the instruction in writeback, // all other exception/faults occur on the instruction in ID/EX. The faults from writeback - // must take priority as that instruction is architecurally ordered before the one in ID/EX. + // must take priority as that instruction is architecturally ordered before the one in ID/EX. if (store_err_q) begin store_err_prio = 1'b1; end else if (load_err_q) begin @@ -317,7 +317,7 @@ module ibex_controller #( assign entering_nmi = nmi_mode_d & ~nmi_mode_q; - // Load integerity error internal interrupt + // Load integrity error internal interrupt always_comb begin mem_resp_intg_err_addr_d = mem_resp_intg_err_addr_q; mem_resp_intg_err_irq_set = 1'b0; @@ -428,7 +428,7 @@ module ibex_controller #( // Record the debug cause outside of the FSM // The decision to enter debug_mode and the write of the cause to DCSR happen - // in seperate steps within the FSM. Hence, there are a small number of cycles + // in separate steps within the FSM. Hence, there are a small number of cycles // where a change in external stimulus can cause the cause to be recorded incorrectly. assign debug_cause_d = trigger_match_i ? DBG_CAUSE_TRIGGER : ebrk_insn_prio & ebreak_into_debug ? DBG_CAUSE_EBREAK : @@ -935,7 +935,7 @@ module ibex_controller #( debug_mode_d != debug_mode_q |-> flush_id_o & pc_set_o) `ifdef RVFI - // Workaround for internal verilator error when using hierarchical refers to calcuate this + // Workaround for internal verilator error when using hierarchical refers to calculate this // directly in ibex_core logic rvfi_flush_next; diff --git a/rtl/ibex_core.sv b/rtl/ibex_core.sv index 6d037348b0..6700244559 100644 --- a/rtl/ibex_core.sv +++ b/rtl/ibex_core.sv @@ -109,7 +109,7 @@ module ibex_core import ibex_pkg::*; #( input logic irq_timer_i, input logic irq_external_i, input logic [14:0] irq_fast_i, - input logic irq_nm_i, // non-maskeable interrupt + input logic irq_nm_i, // non-maskable interrupt output logic irq_pending_o, // Debug Interface @@ -291,7 +291,7 @@ module ibex_core import ibex_pkg::*; #( logic [31:0] csr_rdata; logic [31:0] csr_wdata; logic illegal_csr_insn_id; // CSR access to non-existent register, - // with wrong priviledge level, + // with wrong privilege level, // or missing write permissions // Data Memory Control @@ -897,7 +897,7 @@ module ibex_core import ibex_pkg::*; #( logic [1:0] rf_ecc_err_a, rf_ecc_err_b; logic rf_ecc_err_a_id, rf_ecc_err_b_id; - // ECC checkbit generation for regiter file wdata + // ECC checkbit generation for register file wdata prim_secded_inv_39_32_enc regfile_ecc_enc ( .data_i(rf_wdata_wb), .data_o(rf_wdata_wb_ecc_o) @@ -1537,7 +1537,7 @@ module ibex_core import ibex_pkg::*; #( // rvfi_irq_valid signals an interrupt event to the cosim. These should only occur when the RVFI - // pipe is empty so just send it straigh through. + // pipe is empty so just send it straight through. for (genvar i = 0; i < RVFI_STAGES + 1; i = i + 1) begin : g_rvfi_irq_valid if (i == 0) begin : g_rvfi_irq_valid_first_stage always_ff @(posedge clk_i or negedge rst_ni) begin diff --git a/rtl/ibex_cs_registers.sv b/rtl/ibex_cs_registers.sv index 6f27b20352..29e0b8dcb9 100644 --- a/rtl/ibex_cs_registers.sv +++ b/rtl/ibex_cs_registers.sv @@ -109,7 +109,7 @@ module ibex_cs_registers #( input ibex_pkg::exc_cause_t csr_mcause_i, input logic [31:0] csr_mtval_i, output logic illegal_csr_insn_o, // access to non-existent CSR, - // with wrong priviledge level, or + // with wrong privilege level, or // missing write permissions output logic double_fault_seen_o, // Performance Counters @@ -199,7 +199,7 @@ module ibex_cs_registers #( } dcsr_t; // Partial CPU control and status register fields - // ICache scramble key valid (ic_scr_key_valid) is registered seperately to this struct. This is + // ICache scramble key valid (ic_scr_key_valid) is registered separately to this struct. This is // because it is sampled from the top-level every cycle whilst the other fields only change // occasionally. typedef struct packed { @@ -343,7 +343,7 @@ module ibex_cs_registers #( CSR_MIMPID: csr_rdata_int = CsrMimpId; // mhartid: unique hardware thread id CSR_MHARTID: csr_rdata_int = hart_id_i; - // mconfigptr: pointer to configuration data structre + // mconfigptr: pointer to configuration data structure CSR_MCONFIGPTR: csr_rdata_int = CSR_MCONFIGPTR_VALUE; // mstatus: always M-mode, contains IE bit diff --git a/rtl/ibex_decoder.sv b/rtl/ibex_decoder.sv index 880885575f..843eb05f05 100644 --- a/rtl/ibex_decoder.sv +++ b/rtl/ibex_decoder.sv @@ -1196,7 +1196,7 @@ module ibex_decoder #( // instruction exceptions assign illegal_insn_o = illegal_insn | illegal_reg_rv32e; - // do not propgate regfile write enable if non-available registers are accessed in RV32E + // do not propagate regfile write enable if non-available registers are accessed in RV32E assign rf_we_o = rf_we & ~illegal_reg_rv32e; // Not all bits are used diff --git a/rtl/ibex_dummy_instr.sv b/rtl/ibex_dummy_instr.sv index ba33adc41a..8951eb191e 100644 --- a/rtl/ibex_dummy_instr.sv +++ b/rtl/ibex_dummy_instr.sv @@ -96,9 +96,9 @@ module ibex_dummy_instr import ibex_pkg::*; #( // LFSR with a mask applied (based on CSR config data) to shorten the period if required. assign dummy_cnt_threshold = lfsr_data.cnt & {dummy_instr_mask_i,{TIMEOUT_CNT_W-3{1'b1}}}; assign dummy_cnt_incr = dummy_cnt_q + {{TIMEOUT_CNT_W-1{1'b0}},1'b1}; - // Clear the counter everytime a new instruction is inserted + // Clear the counter every time a new instruction is inserted assign dummy_cnt_d = insert_dummy_instr ? '0 : dummy_cnt_incr; - // Increment the counter for each executed instruction while dummy instuctions are + // Increment the counter for each executed instruction while dummy instructions are // enabled. assign dummy_cnt_en = dummy_instr_en_i & id_in_ready_i & (fetch_valid_i | insert_dummy_instr); diff --git a/rtl/ibex_ex_block.sv b/rtl/ibex_ex_block.sv index c44a931691..1a21017ebb 100644 --- a/rtl/ibex_ex_block.sv +++ b/rtl/ibex_ex_block.sv @@ -23,7 +23,7 @@ module ibex_ex_block #( input logic alu_instr_first_cycle_i, // Branch Target ALU - // All of these signals are unusued when BranchTargetALU == 0 + // All of these signals are unused when BranchTargetALU == 0 input logic [31:0] bt_a_operand_i, input logic [31:0] bt_b_operand_i, @@ -197,7 +197,7 @@ module ibex_ex_block #( assign ex_valid_o = multdiv_sel ? multdiv_valid : ~(|alu_imd_val_we); `ifdef INC_ASSERT - // This is intended to be accessed via hierarchal references so isn't output from this module nor + // This is intended to be accessed via hierarchical references so isn't output from this module nor // used in any logic in this module logic sva_multdiv_fsm_idle; diff --git a/rtl/ibex_icache.sv b/rtl/ibex_icache.sv index 23f4357028..8def4a7cae 100644 --- a/rtl/ibex_icache.sv +++ b/rtl/ibex_icache.sv @@ -76,7 +76,7 @@ module ibex_icache import ibex_pkg::*; #( logic [ADDR_W-1:0] lookup_addr_aligned; logic [ADDR_W-1:0] prefetch_addr_d, prefetch_addr_q; logic prefetch_addr_en; - // Cache pipelipe IC0 signals + // Cache pipeline IC0 signals logic lookup_throttle; logic lookup_req_ic0; logic [ADDR_W-1:0] lookup_addr_ic0; @@ -98,7 +98,7 @@ module ibex_icache import ibex_pkg::*; #( logic [IC_NUM_WAYS-1:0] data_banks_ic0; logic data_write_ic0; logic [LineSizeECC-1:0] data_wdata_ic0; - // Cache pipelipe IC1 signals + // Cache pipeline IC1 signals logic [TagSizeECC-1:0] tag_rdata_ic1 [IC_NUM_WAYS]; logic [LineSizeECC-1:0] data_rdata_ic1 [IC_NUM_WAYS]; logic [LineSizeECC-1:0] hit_data_ecc_ic1; @@ -1112,7 +1112,7 @@ module ibex_icache import ibex_pkg::*; #( inval_index_en = 1'b1; if (icache_inval_i) begin - // If a new invalidaiton requests comes in go back to the beginning with a new scramble + // If a new invalidation requests comes in go back to the beginning with a new scramble // key ic_scr_key_req_o = 1'b1; inval_state_d = AWAIT_SCRAMBLE_KEY; @@ -1127,7 +1127,7 @@ module ibex_icache import ibex_pkg::*; #( ic_scr_key_req_o = 1'b1; inval_state_d = AWAIT_SCRAMBLE_KEY; end else begin - // Allow other cache activies whilst in IDLE and no invalidation has been requested + // Allow other cache activities whilst in IDLE and no invalidation has been requested inval_block_cache = 1'b0; end end diff --git a/rtl/ibex_id_stage.sv b/rtl/ibex_id_stage.sv index 43f7762f15..81fe19253f 100644 --- a/rtl/ibex_id_stage.sv +++ b/rtl/ibex_id_stage.sv @@ -519,7 +519,7 @@ module ibex_id_stage #( // instructions are in general rare and not part of performance critical parts of the code. // // No flush is triggered for a small number of specific CSRs. These are ones that have been - // specifically identified to be a) likely to be modifed in exception handlers and b) safe to + // specifically identified to be a) likely to be modified in exception handlers and b) safe to // alter without a flush. assign no_flush_csr_addr = csr_addr_o inside {CSR_MSCRATCH, CSR_MEPC}; @@ -578,7 +578,7 @@ module ibex_id_stage #( .controller_run_o (controller_run), .instr_exec_i (instr_exec_i), - // to prefetcher + // to prefetch .instr_req_o (instr_req_o), .pc_set_o (pc_set_o), .pc_mux_o (pc_mux_o), @@ -972,7 +972,7 @@ module ibex_id_stage #( (outstanding_memory_access | (lsu_req_dec & ~lsu_req_done_i)); // If we stall a load in ID for any reason, it must not make an LSU request - // (otherwide we might issue two requests for the same instruction) + // (otherwise we might issue two requests for the same instruction) `ASSERT(IbexStallMemNoRequest, instr_valid_i & lsu_req_dec & ~instr_done |-> ~lsu_req_done_i) @@ -1040,7 +1040,7 @@ module ibex_id_stage #( assign rf_rd_b_wb_match_o = 1'b0; // First cycle of a load or store is always the request. We're expecting a response the cycles - // following. Note if the request isn't immediatly accepted these signals will still assert. + // following. Note if the request isn't immediately accepted these signals will still assert. // However in this case the LSU won't signal a response as it's still waiting for the grant // (even if the external memory bus signals are glitched to generate a false response). assign expecting_load_resp_o = instr_valid_i & lsu_req_dec & ~instr_first_cycle & ~lsu_we; @@ -1146,7 +1146,7 @@ module ibex_id_stage #( `ASSERT(IbexDuplicateInstrMatch, instr_valid_i |-> instr_rdata_i === instr_rdata_alu_i) // Check that when ID stage is ready for next instruction FSM is in FIRST_CYCLE state the - // following cycle (when the new instructon may begin executing). + // following cycle (when the new instruction may begin executing). `ASSERT(IbexMoveToFirstCycleWhenIdReady, id_in_ready_o |=> id_fsm_q == FIRST_CYCLE) `ifdef CHECK_MISALIGNED diff --git a/rtl/ibex_if_stage.sv b/rtl/ibex_if_stage.sv index b5650cac6b..ebdd6e46c4 100644 --- a/rtl/ibex_if_stage.sv +++ b/rtl/ibex_if_stage.sv @@ -541,7 +541,8 @@ module ibex_if_stage import ibex_pkg::*; #( logic prev_instr_seq_q, prev_instr_seq_d; // Do not check for sequential increase after a branch, jump, exception, interrupt or debug - // request, all of which will set branch_req. Also do not check after reset or for dummys. + // request, all of which will set branch_req. Also do not check after reset or for dummy + // instructions. assign prev_instr_seq_d = (prev_instr_seq_q | instr_new_id_d) & ~branch_req & ~if_instr_err & ~stall_dummy_instr; diff --git a/rtl/ibex_load_store_unit.sv b/rtl/ibex_load_store_unit.sv index 564f89bf68..cfd7ac4134 100644 --- a/rtl/ibex_load_store_unit.sv +++ b/rtl/ibex_load_store_unit.sv @@ -565,7 +565,7 @@ module ibex_load_store_unit #( // fcov_mis_rvalid_2: Set when response is received for the second half logic fcov_mis_rvalid_1, fcov_mis_rvalid_2; - // Set when the first half of a misaligned access saw a bus errror + // Set when the first half of a misaligned access saw a bus error logic fcov_mis_bus_err_1_d, fcov_mis_bus_err_1_q; assign fcov_mis_rvalid_1 = ls_fsm_cs inside {WAIT_RVALID_MIS, WAIT_RVALID_MIS_GNTS_DONE} && diff --git a/rtl/ibex_multdiv_fast.sv b/rtl/ibex_multdiv_fast.sv index 2e48dc5270..4cfe11c143 100644 --- a/rtl/ibex_multdiv_fast.sv +++ b/rtl/ibex_multdiv_fast.sv @@ -254,7 +254,7 @@ module ibex_multdiv_fast #( assign unused_mult1_res_uns = mult1_res_uns[33:32]; - // States must be knwon/valid. + // States must be known/valid. `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) assign sva_mul_fsm_idle = mult_state_q == MULL; @@ -374,7 +374,7 @@ module ibex_multdiv_fast #( end end - // States must be knwon/valid. + // States must be known/valid. `ASSERT_KNOWN(IbexMultStateKnown, mult_state_q) assign sva_mul_fsm_idle = mult_state_q == ALBL; @@ -528,7 +528,7 @@ module ibex_multdiv_fast #( assign valid_o = mult_valid | div_valid; - // States must be knwon/valid. + // States must be known/valid. `ASSERT(IbexMultDivStateValid, md_state_q inside { MD_IDLE, MD_ABS_A, MD_ABS_B, MD_COMP, MD_LAST, MD_CHANGE_SIGN, MD_FINISH}) @@ -536,7 +536,7 @@ module ibex_multdiv_fast #( logic sva_fsm_idle; logic unused_sva_fsm_idle; - // This is intended to be accessed via hierarchal references so isn't output from this module nor + // This is intended to be accessed via hierarchical references so isn't output from this module nor // used in any logic in this module assign sva_fsm_idle = (md_state_q == MD_IDLE) && sva_mul_fsm_idle; // Mark the sva_fsm_idle as unused to avoid lint issues diff --git a/rtl/ibex_multdiv_slow.sv b/rtl/ibex_multdiv_slow.sv index c409e2965f..7f5c33259a 100644 --- a/rtl/ibex_multdiv_slow.sv +++ b/rtl/ibex_multdiv_slow.sv @@ -374,7 +374,7 @@ module ibex_multdiv_slow logic sva_fsm_idle; logic unused_sva_fsm_idle; - // This is intended to be accessed via hierarchal references so isn't output from this module nor + // This is intended to be accessed via hierarchical references so isn't output from this module nor // used in any logic in this module assign sva_fsm_idle = (md_state_q == MD_IDLE); // Mark the sva_fsm_idle as unused to avoid lint issues diff --git a/rtl/ibex_pkg.sv b/rtl/ibex_pkg.sv index 803f95b187..f5cb75a3e7 100644 --- a/rtl/ibex_pkg.sv +++ b/rtl/ibex_pkg.sv @@ -388,7 +388,7 @@ package ibex_pkg; parameter int unsigned PMP_MAX_REGIONS = 16; parameter int unsigned PMP_CFG_W = 8; - // PMP acces type + // PMP access type parameter int unsigned PMP_I = 0; parameter int unsigned PMP_I2 = 1; parameter int unsigned PMP_D = 2; @@ -624,7 +624,7 @@ package ibex_pkg; localparam logic [31:0] CSR_MARCHID_VALUE = {1'b0, 31'd22}; // Machine Configuration Pointer - // 0 indicates the configuration data structure does not eixst. Ibex implementors may wish to + // 0 indicates the configuration data structure does not exist. Ibex implementers may wish to // alter this to point to their system specific configuration data structure. localparam logic [31:0] CSR_MCONFIGPTR_VALUE = 32'b0; @@ -642,7 +642,7 @@ package ibex_pkg; parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonceDefault = 64'hf79780bc735f3843; - // Mult-bit signal used for security hardening. For non-secure implementation all bits other than + // Multi-bit signal used for security hardening. For non-secure implementation all bits other than // the bottom bit are ignored. parameter int IbexMuBiWidth = 4; typedef logic [IbexMuBiWidth-1:0] ibex_mubi_t; @@ -680,7 +680,7 @@ package ibex_pkg; '{lock: 1'b0, mode: PMP_MODE_OFF, exec: 1'b0, write: 1'b0, read: 1'b0} // region 15 }; - // Addresses are given in byte granularity for readibility. A minimum of two + // Addresses are given in byte granularity for readability. A minimum of two // bits will be stripped off the bottom (PMPGranularity == 0) with more stripped // off at coarser granularities. parameter logic [33:0] PmpAddrRst[16] = '{ diff --git a/rtl/ibex_prefetch_buffer.sv b/rtl/ibex_prefetch_buffer.sv index 2984d84a68..0c3be0acbd 100644 --- a/rtl/ibex_prefetch_buffer.sv +++ b/rtl/ibex_prefetch_buffer.sv @@ -4,7 +4,7 @@ // SPDX-License-Identifier: Apache-2.0 /** - * Prefetcher Buffer for 32 bit memory interface + * Prefetch Buffer for 32 bit memory interface * * Prefetch Buffer that caches instructions. This cuts overly long critical * paths to the instruction cache. @@ -134,7 +134,7 @@ module ibex_prefetch_buffer #( // 2. fetch_addr_q - This is our next address to fetch from. It is updated on branches to // capture the new address, and then for each new request issued. // A third address is tracked in the fetch FIFO itself: - // 3. instr_addr_q - This is the address at the head of the FIFO, efectively our oldest fetched + // 3. instr_addr_q - This is the address at the head of the FIFO, effectively our oldest fetched // address. This address is updated on branches, and does its own increment // each time the FIFO is popped. diff --git a/rtl/ibex_top.sv b/rtl/ibex_top.sv index 951d1f155d..3c5a09b56c 100644 --- a/rtl/ibex_top.sv +++ b/rtl/ibex_top.sv @@ -45,11 +45,11 @@ module ibex_top import ibex_pkg::*; #( parameter logic [SCRAMBLE_KEY_W-1:0] RndCnstIbexKey = RndCnstIbexKeyDefault, parameter logic [SCRAMBLE_NONCE_W-1:0] RndCnstIbexNonce = RndCnstIbexNonceDefault, // mvendorid: encoding of manufacturer/provider - // 0 indicates this field is not implemented. Ibex implementors may wish to set their + // 0 indicates this field is not implemented. Ibex implementers may wish to set their // own JEDEC ID here. parameter logic [31:0] CsrMvendorId = 32'b0, // mimpid: encoding of processor implementation version - // 0 indicates this field is not implemented. Ibex implementors may wish to indicate an + // 0 indicates this field is not implemented. Ibex implementers may wish to indicate an // RTL/netlist version here using their own unique encoding (e.g. 32 bits of the git hash of the // implemented commit). parameter logic [31:0] CsrMimpId = 32'b0 @@ -91,7 +91,7 @@ module ibex_top import ibex_pkg::*; #( input logic irq_timer_i, input logic irq_external_i, input logic [14:0] irq_fast_i, - input logic irq_nm_i, // non-maskeable interrupt + input logic irq_nm_i, // non-maskable interrupt // Scrambling Interface input logic scramble_key_valid_i, diff --git a/rtl/ibex_top_tracing.sv b/rtl/ibex_top_tracing.sv index b9f8045c06..4af5b5b8aa 100644 --- a/rtl/ibex_top_tracing.sv +++ b/rtl/ibex_top_tracing.sv @@ -71,7 +71,7 @@ module ibex_top_tracing import ibex_pkg::*; #( input logic irq_timer_i, input logic irq_external_i, input logic [14:0] irq_fast_i, - input logic irq_nm_i, // non-maskeable interrupt + input logic irq_nm_i, // non-maskable interrupt // Scrambling Interface input logic scramble_key_valid_i, diff --git a/shared/rtl/bus.sv b/shared/rtl/bus.sv index 072a959929..f92ecc3056 100644 --- a/shared/rtl/bus.sv +++ b/shared/rtl/bus.sv @@ -61,7 +61,7 @@ module bus #( logic [NumBitsHostSel-1:0] host_sel_req, host_sel_resp; logic [NumBitsDeviceSel-1:0] device_sel_req, device_sel_resp; - // Master select prio arbiter + // Master select priority arbiter always_comb begin host_sel_valid = 1'b0; host_sel_req = '0; diff --git a/shared/rtl/sim/simulator_ctrl.sv b/shared/rtl/sim/simulator_ctrl.sv index 1e10b75c2d..d00d496c74 100644 --- a/shared/rtl/sim/simulator_ctrl.sv +++ b/shared/rtl/sim/simulator_ctrl.sv @@ -61,7 +61,7 @@ module simulator_ctrl #( rvalid_o <= 0; sim_finish <= 'b0; end else begin - // Immeditely respond to any request + // Immediately respond to any request rvalid_o <= req_i; if (req_i & we_i) begin diff --git a/syn/README.md b/syn/README.md index 4f2a37b2dd..0c5792b09d 100644 --- a/syn/README.md +++ b/syn/README.md @@ -11,11 +11,11 @@ OpenSTA to produce timing reports. Its outputs are: been mapped to a standard-cell library yet * A post synthesis netlist - Gate-level verilog after optimisation mapped to a standard-cell library -* An STA netlist - Logically equivilent to the netlist above but with changes to +* An STA netlist - Logically equivalent to the netlist above but with changes to allow processing by OpenSTA * Area/Cell Usage report - Total area consumed by utilised cells and counts of each cell instance used -* Timing reports - Overal timing report and reports broken down into various +* Timing reports - Overall timing report and reports broken down into various path groups (register to register paths and per IO reports) Yosys doesn't yet support the full subset of SystemVerilog used by Ibex so the @@ -91,7 +91,7 @@ flow. These are used to generate a single .sdc file inputs and the desired clock period in ps * `ibex.[library-name].sdc` - Header to include in generated .sdc file. Settings can be library dependent so the `LR_SYNTH_CELL_LIBRARY_NAME` environment - varible is used to supply the `[library-name]` part of the name + variable is used to supply the `[library-name]` part of the name # Timing reports diff --git a/syn/python/get_kge.py b/syn/python/get_kge.py index e2704eacf8..c0cb937a12 100755 --- a/syn/python/get_kge.py +++ b/syn/python/get_kge.py @@ -4,7 +4,7 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -# Parse a yosys area report and give a kGE equivalient +# Parse a yosys area report and give a kGE equivalent import argparse diff --git a/syn/tcl/lr_synth_flow_var_setup.tcl b/syn/tcl/lr_synth_flow_var_setup.tcl index caa06a91c8..293c748ff4 100644 --- a/syn/tcl/lr_synth_flow_var_setup.tcl +++ b/syn/tcl/lr_synth_flow_var_setup.tcl @@ -16,7 +16,7 @@ set_flow_bool_var timing_run 0 "timing run" set_flow_bool_var ibex_branch_target_alu 0 "Enable branch target ALU in Ibex" set_flow_bool_var ibex_writeback_stage 0 "Enable writeback stage in Ibex" set_flow_bool_var ibex_secure_ibex 0 "Enable SecureIbex configuration" -set_flow_var ibex_bitmanip 0 "Bitmanip extenion setting for Ibex (see ibex_pkg::rv32b_e for permitted values. Enum names are not supported in Yosys.)" +set_flow_var ibex_bitmanip 0 "Bitmanip extension setting for Ibex (see ibex_pkg::rv32b_e for permitted values. Enum names are not supported in Yosys.)" set_flow_var ibex_multiplier 2 "Multiplier extension setting for Ibex (see ibex_pkg::rv32m_e for permitted values. Enum names are not supported in Yosys.)" set_flow_var ibex_regfile 2 "Register file implementation selection for Ibex (see ibex_pkg::regfile_e for permitted values. Enum names are not supported in Yosys.)"