Update prim_fifo IP

This vendors a newer version of OT prim FIFO IP. The new version has a single
core file for both async and sync FIFOs, and port names are changed.

Signed-off-by: Gary Guo <gary@garyguo.net>

Author: nbdd0121

ip/core/muntjac_core.core

@@ -11,7 +11,7 @@ filesets:
       - lowrisc:muntjac:pipeline
       - lowrisc:prim:ram_1p
       - lowrisc:prim:util
-      - lowrisc:prim:fifo_sync
+      - lowrisc:prim:fifo
       - lowrisc:tl:common
       - lowrisc:tl:socket_m1
       - lowrisc:tl:adapter

ip/core/rtl/muntjac_dcache.sv

@@ -1035,14 +1035,16 @@ module muntjac_dcache import muntjac_pkg::*; import tl_pkg::*; # (
   ) refill_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (refill_fifo_insert),
-    .wready (),
-    .wdata  ({gnt_w, mem_d_last, mem_d_idx}),
-    .rvalid (refill_fifo_valid),
-    .rready (refill_fifo_ready),
-    .rdata  ({refill_fifo_beat, refill_fifo_last, refill_fifo_idx}),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (refill_fifo_insert),
+    .wready_o (),
+    .wdata_i  ({gnt_w, mem_d_last, mem_d_idx}),
+    .rvalid_o (refill_fifo_valid),
+    .rready_i (refill_fifo_ready),
+    .rdata_o  ({refill_fifo_beat, refill_fifo_last, refill_fifo_idx}),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
   logic refill_beat_saved_q, refill_beat_saved_d;

ip/core/rtl/muntjac_icache_coherent.sv

@@ -642,14 +642,16 @@ module muntjac_icache_coherent import muntjac_pkg::*; import tl_pkg::*; # (
   ) refill_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (refill_fifo_insert),
-    .wready (),
-    .wdata  ({gnt_w, mem_d_last, mem_d_idx}),
-    .rvalid (refill_fifo_valid),
-    .rready (refill_fifo_ready),
-    .rdata  ({refill_fifo_beat, refill_fifo_last, refill_fifo_idx}),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (refill_fifo_insert),
+    .wready_o (),
+    .wdata_i  ({gnt_w, mem_d_last, mem_d_idx}),
+    .rvalid_o (refill_fifo_valid),
+    .rready_i (refill_fifo_ready),
+    .rdata_o  ({refill_fifo_beat, refill_fifo_last, refill_fifo_idx}),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
   logic refill_beat_saved_q, refill_beat_saved_d;

ip/tl/rtl/tl_fifo_sync.sv

@@ -47,14 +47,16 @@ module tl_fifo_sync import tl_pkg::*; #(
   ) req_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (host_a_valid),
-    .wready (host_a_ready),
-    .wdata  (req_w),
-    .rvalid (device_a_valid),
-    .rready (device_a_ready),
-    .rdata  (device_a),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (host_a_valid),
+    .wready_o (host_a_ready),
+    .wdata_i  (req_w),
+    .rvalid_o (device_a_valid),
+    .rready_i (device_a_ready),
+    .rdata_o  (device_a),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
   ///////////////////
@@ -72,14 +74,16 @@ module tl_fifo_sync import tl_pkg::*; #(
   ) prb_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (device_b_valid),
-    .wready (device_b_ready),
-    .wdata  (prb_w),
-    .rvalid (host_b_valid),
-    .rready (host_b_ready),
-    .rdata  (host_b),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (device_b_valid),
+    .wready_o (device_b_ready),
+    .wdata_i  (prb_w),
+    .rvalid_o (host_b_valid),
+    .rready_i (host_b_ready),
+    .rdata_o  (host_b),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
   /////////////////////
@@ -97,14 +101,16 @@ module tl_fifo_sync import tl_pkg::*; #(
   ) rel_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (host_c_valid),
-    .wready (host_c_ready),
-    .wdata  (rel_w),
-    .rvalid (device_c_valid),
-    .rready (device_c_ready),
-    .rdata  (device_c),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (host_c_valid),
+    .wready_o (host_c_ready),
+    .wdata_i  (rel_w),
+    .rvalid_o (device_c_valid),
+    .rready_i (device_c_ready),
+    .rdata_o  (device_c),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
   ///////////////////
@@ -122,14 +128,16 @@ module tl_fifo_sync import tl_pkg::*; #(
   ) gnt_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (device_d_valid),
-    .wready (device_d_ready),
-    .wdata  (gnt_w),
-    .rvalid (host_d_valid),
-    .rready (host_d_ready),
-    .rdata  (host_d),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (device_d_valid),
+    .wready_o (device_d_ready),
+    .wdata_i  (gnt_w),
+    .rvalid_o (host_d_valid),
+    .rready_i (host_d_ready),
+    .rdata_o  (host_d),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
   /////////////////////////////
@@ -143,14 +151,16 @@ module tl_fifo_sync import tl_pkg::*; #(
   ) ack_fifo (
     .clk_i,
     .rst_ni,
-    .clr_i  (1'b0),
-    .wvalid (host_e_valid),
-    .wready (host_e_ready),
-    .wdata  (host_e),
-    .rvalid (device_e_valid),
-    .rready (device_e_ready),
-    .rdata  (device_e),
-    .depth  ()
+    .clr_i    (1'b0),
+    .wvalid_i (host_e_valid),
+    .wready_o (host_e_ready),
+    .wdata_i  (host_e),
+    .rvalid_o (device_e_valid),
+    .rready_i (device_e_ready),
+    .rdata_o  (device_e),
+    .full_o   (),
+    .depth_o  (),
+    .err_o    ()
   );
 
 endmodule

ip/tl/tl_fifo_async.core

@@ -9,7 +9,7 @@ filesets:
   files_rtl:
     depend:
       - lowrisc:tl:common
-      - lowrisc:prim:fifo_async
+      - lowrisc:prim:fifo
     files:
       - rtl/tl_fifo_async.sv
     file_type: systemVerilogSource

ip/tl/tl_fifo_sync.core

@@ -9,7 +9,7 @@ filesets:
   files_rtl:
     depend:
       - lowrisc:tl:common
-      - lowrisc:prim:fifo_sync
+      - lowrisc:prim:fifo
     files:
       - rtl/tl_fifo_sync.sv
     file_type: systemVerilogSource

vendor/lowrisc_ip/prim/lint/prim_fifo.vlt

@@ -0,0 +1,10 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+`verilator_config
+
+// prim_fifo_sync
+// In passthrough mode, clk and reset are not read form within this module
+lint_off -rule UNUSED -file "*/rtl/prim_fifo_sync.sv" -match "*clk_i*"
+lint_off -rule UNUSED -file "*/rtl/prim_fifo_sync.sv" -match "*rst_ni*"

vendor/lowrisc_ip/prim/lint/prim_fifo.waiver

@@ -0,0 +1,35 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# waiver file for prim_fifo
+
+waive -rules {ONE_BIT_MEM_WIDTH} -location {prim_fifo_sync.sv} -msg {Memory 'gen_normal_fifo.storage' has word width which is single bit wide} \
+      -comment "It is permissible that a FIFO has a wordwidth of 1bit"
+
+waive -rules {INPUT_NOT_READ} -location {prim_fifo_sync.sv} -regexp {Input port '(clk_i|rst_ni)' is not read from, instance.*Depth=0\)} \
+      -comment "In passthrough mode, clk and reset are not read form within this module"
+
+
+waive -rules {ASSIGN_SIGN} -location {prim_fifo_async.sv} -msg {Signed target 'i' assigned unsigned value 'PTR_WIDTH - 3'} \
+      -comment "Parameter PTR_WIDTH is unsigned, but integer i is signed. This is fine. Changing the integer to unsigned might \
+                cause issues with the for loop never exiting, because an unsigned integer can never become < 0."
+
+waive -rules NOT_READ             -location {prim_fifo_async.sv} -regexp {Signal 'nc_decval_msb' is not read} \
+      -comment "Store temporary values. Not used intentionally"
+
+
+waive -rules VAR_INDEX_RANGE      -location {prim_fifo_*sync.sv} -regexp {maximum value .* may be too large for 'storage'} \
+      -comment "index is protected by control logic"
+
+waive -rules EXPLICIT_BITLEN      -location {prim_fifo_*sync.sv} -regexp {Bit length not specified for constant '1'} \
+      -comment "index is protected by control logic"
+
+## prim_fifo_async_sram_adapter
+waive -rules ARITH_CONTEXT -location {prim_fifo_async_sram_adapter.sv} \
+      -regexp {(r|w)_wptr_v.*_rptr_v} \
+      -comment "The pointer value width is determined. Remove the casting for readability"
+waive -rules USE_BEFORE_DECL -location {prim_fifo_async_sram_adapter.sv} -msg {'dec2gray' is referenced before its declaration at prim_fifo_async_sram_adapter.sv} \
+      -comment "dec2gray is a function defined towards the end of the file."
+waive -rules USE_BEFORE_DECL -location {prim_fifo_async_sram_adapter.sv} -msg {'gray2dec' is referenced before its declaration at prim_fifo_async_sram_adapter.sv} \
+      -comment "gray2dec is a function defined towards the end of the file."

…dor/lowrisc_ip/prim/prim_fifo_async.core vendor/lowrisc_ip/prim/prim_fifo.corevendor/lowrisc_ip/prim/prim_fifo_async.core renamed to vendor/lowrisc_ip/prim/prim_fifo.core vendor/lowrisc_ip/prim/prim_fifo_async.core renamed to vendor/lowrisc_ip/prim/prim_fifo.core

@@ -1,34 +1,44 @@
 CAPI=2:
-# Copyright lowRISC contributors.
+# Copyright lowRISC contributors (OpenTitan project).
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-name: "lowrisc:prim:fifo_async"
-description: "Async FIFO"
+name: "lowrisc:prim:fifo"
+description: "Synchronous and asynchronous fifos"
 filesets:
   files_rtl:
     depend:
       - lowrisc:prim:assert
+      - lowrisc:prim:util
       - lowrisc:prim:flop_2sync
     files:
+      - rtl/prim_fifo_async_sram_adapter.sv
+      - rtl/prim_fifo_async_simple.sv
       - rtl/prim_fifo_async.sv
+      - rtl/prim_fifo_sync.sv
+      - rtl/prim_fifo_sync_cnt.sv
     file_type: systemVerilogSource
 
   files_verilator_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
+    files:
+      - lint/prim_fifo.vlt
+    file_type: vlt
 
   files_ascentlint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
+    files:
+      - lint/prim_fifo.waiver
+    file_type: waiver
 
   files_veriblelint_waiver:
     depend:
       # common waivers
       - lowrisc:lint:common
-      - lowrisc:lint:comportable
 
 targets:
   default: