[hw,darjeeling] Remove references to the ADC clock

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson

@@ -123,7 +123,6 @@
         clocks:
         {
           clk_io_peri: io
-          clk_aon_peri: aon
         }
       }
       {
@@ -3562,11 +3561,6 @@
           clock: io
           group: infra
         }
-        clk_ast_adc_i:
-        {
-          clock: aon
-          group: peri
-        }
         clk_ast_alert_i:
         {
           clock: io
@@ -3586,11 +3580,6 @@
           name: lc_io
           domain: "0"
         }
-        rst_ast_adc_ni:
-        {
-          name: lc_aon
-          domain: Aon
-        }
         rst_ast_alert_ni:
         {
           name: lc_io
@@ -3611,7 +3600,6 @@
       clock_connections:
       {
         clk_ast_tlul_i: clkmgr_aon_clocks.clk_io_infra
-        clk_ast_adc_i: clkmgr_aon_clocks.clk_aon_peri
         clk_ast_alert_i: clkmgr_aon_clocks.clk_io_secure
         clk_ast_rng_i: clkmgr_aon_clocks.clk_main_secure
       }
@@ -20650,7 +20638,6 @@
         clocks:
         {
           clk_io_peri: io
-          clk_aon_peri: aon
         }
       }
       clock_connection: clkmgr_aon_clocks.clk_io_peri
@@ -20673,7 +20660,6 @@
         clocks:
         {
           clk_io_peri: io
-          clk_aon_peri: aon
         }
       }
       clock_connection: clkmgr_aon_clocks.clk_io_peri
@@ -20696,7 +20682,6 @@
         clocks:
         {
           clk_io_peri: io
-          clk_aon_peri: aon
         }
       }
       clock_connection: clkmgr_aon_clocks.clk_io_peri
@@ -20765,7 +20750,6 @@
         clocks:
         {
           clk_io_peri: io
-          clk_aon_peri: aon
         }
       }
       clock_connection: clkmgr_aon_clocks.clk_io_peri

hw/top_darjeeling/data/chip_conn_testplan.hjson

@@ -36,7 +36,6 @@
               "ast_clk_io_out",
               "ast_all_byp_ack_out",
               "ast_io_byp_ack_out",
-              "ast_clk_adc_in",
               "ast_clk_alert_in",
               "ast_clk_es_in",
               "ast_clk_rng_in",
@@ -73,8 +72,7 @@
       desc: '''Verify the reset connectivity between AST and reset manager.
             '''
       stage: V2
-      tests: ["ast_rst_adc_in",
-              "ast_rst_alert_in",
+      tests: ["ast_rst_alert_in",
               "ast_rst_es_in",
               "ast_rst_rng_in",
               "ast_rst_tlul_in",
@@ -380,15 +378,13 @@
       name: clkmgr_clk_io_peri
       desc: '''Verify clkmgr's `clk_io_peri` is connected to the following blocks' clock
             input:
-            - adc_ctrl clk_i
             - gpio clk_i
             - spi_device clk_i
             - i2c0 clk_i
             - uart0 clk_i
             '''
       stage: V2
-      tests: ["clkmgr_peri_clk_adc_ctrl_aon_clk",
-              "clkmgr_peri_clk_gpio_clk",
+      tests: ["clkmgr_peri_clk_gpio_clk",
               "clkmgr_peri_clk_spi_device_clk",
               "clkmgr_peri_clk_i2c0_clk",
               "clkmgr_peri_clk_uart0_clk"]
@@ -949,17 +945,6 @@
       tests: ["rstmgr_spi_host0_d0_spi_host0_rst_ni"]
       tags: ["conn"]
     }
-    {
-      name: rst_sys_aon_aon
-      desc: '''Verify rstmgr's rst_sys_aon_n[0] is connected to the following:
-            - adc_ctrl's rst_aon_ni
-            - sensor_ctrl's rst_aon_ni
-            '''
-      stage: V2
-      tests: ["rstmgr_sys_aon_aon_adc_ctrl_rst_aon_ni",
-              "rstmgr_sys_aon_aon_sensor_ctrl_rst_aon_ni"]
-      tags: ["conn"]
-    }
     {
       name: rst_sys_io_d0
       desc: '''Verify rstmgr's rst_sys_io_n[1] is connected to xbar_main's rst_spi_host0_ni.'''
@@ -970,13 +955,11 @@
     {
       name: rst_sys_io_aon
       desc: '''Verify rstmgr's rst_sys_io_n[0] is connected to the following:
-            - adc_ctrl's rst_ni
             - sensor_ctrl's rst_ni
             - sram_ctrl_ret's rst_ni
             '''
       stage: V2
-      tests: ["rstmgr_sys_io_aon_adc_ctrl_rst_ni",
-              "rstmgr_sys_io_aon_sensor_ctrl_rst_ni",
+      tests: ["rstmgr_sys_io_aon_sensor_ctrl_rst_ni",
               "rstmgr_sys_io_aon_sram_ctrl_ret_rst_ni"]
       tags: ["conn"]
     }

hw/top_darjeeling/data/chip_testplan.hjson

@@ -2438,11 +2438,10 @@
       desc: '''Verify the clk and rst inputs to AST (from `clkmgr`).
 
             Create different scenarios that affect the clocks and resets and see that the AST features
-            (RNG, entropy, alert, ADC) that use those clocks/resets behave correctly.
+            (RNG, entropy, alert) that use those clocks/resets behave correctly.
             sequence:
             1. Check that AST RNG generates data and fills the entropy source fifo
             2. Create AST alerts
-            3. Activate ADC conversion
             4. EDN entropy supply to AST
             Enter sleep/deep sleep/ stop IO clocks
             Repeat 1-4 to check it is ok.
@@ -2930,7 +2929,6 @@
 
       Blocks / functionality to run simultaneously in this test:
 
-        - The ADC is continuously sampling new data
         - Staggered activation of OTBN, aes, KMAC/HMAC.
           - KMAC / aes would need to take turns being fed data
           - KMAC activation should be a combination of otp background, key

hw/top_darjeeling/data/top_darjeeling.hjson

@@ -553,10 +553,6 @@
           clock: "io",
           group: "infra"
         },
-        clk_ast_adc_i: {
-          clock: "aon",
-          group: "peri"
-        },
         clk_ast_alert_i: {
           clock: "io",
           group: "secure"
@@ -572,10 +568,6 @@
           name: "lc_io",
           domain: "0",
         }
-        rst_ast_adc_ni: {
-          name: "lc_aon",
-          domain: "Aon"
-        },
         rst_ast_alert_ni: {
           name: "lc_io",
           domain: "0",

hw/top_darjeeling/dv/env/chip_env.core

@@ -126,7 +126,6 @@ filesets:
       - seq_lib/chip_sw_rom_e2e_jtag_debug_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_rom_e2e_jtag_inject_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_power_virus_vseq.sv: {is_include_file: true}
-      - seq_lib/chip_sw_ast_clk_rst_inputs_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_dma_spi_hw_handshake_vseq.sv: {is_include_file: true}
       - autogen/chip_env_pkg__params.sv: {is_include_file: true}
       - alerts_if.sv

hw/top_darjeeling/dv/env/chip_if.sv

@@ -536,7 +536,6 @@ interface chip_if;
   wire sram_ret_init_done = `SRAM_CTRL_RET_HIER.u_reg_regs.status_init_done_qs;
   wire sram_mbox_init_done = `SRAM_CTRL_MBOX.u_reg_regs.status_init_done_qs;
 `endif
-  wire adc_data_valid = `AST_HIER.u_adc.adc_d_val_o;
 
   // alert_esc_if alert_if[NUM_ALERTS](.clk  (`ALERT_HANDLER_HIER.clk_i),
   //                                   .rst_n(`ALERT_HANDLER_HIER.rst_ni));

hw/top_darjeeling/dv/env/seq_lib/chip_sw_ast_clk_rst_inputs_vseq.sv

@@ -85,6 +85,5 @@
 `include "chip_sw_rom_e2e_asm_init_vseq.sv"
 `include "chip_sw_rom_e2e_jtag_debug_vseq.sv"
 `include "chip_sw_rom_e2e_jtag_inject_vseq.sv"
-`include "chip_sw_ast_clk_rst_inputs_vseq.sv"
 `include "chip_sw_power_virus_vseq.sv"
 `include "chip_sw_dma_spi_hw_handshake_vseq.sv"

hw/top_darjeeling/dv/env/seq_lib/chip_vseq_list.sv

@@ -20,7 +20,6 @@ CONNECTION, AST_IO_BYP_ACK_OUT,  u_ast, io_clk_byp_ack_o,  top_darjeeling.u_clkm
 #################################
 # Signals from Clkmgr to AST
 #################################
-CONNECTION, AST_CLK_ADC_IN,     top_darjeeling.u_clkmgr_aon, clocks_o.clk_aon_peri,         u_ast, clk_ast_adc_i
 CONNECTION, AST_CLK_ALERT_IN,   top_darjeeling.u_clkmgr_aon, clocks_o.clk_io_secure,        u_ast, clk_ast_alert_i
 CONNECTION, AST_CLK_ES_IN,      top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_secure,      u_ast, clk_ast_es_i
 CONNECTION, AST_CLK_RNG_IN,     top_darjeeling.u_clkmgr_aon, clocks_o.clk_main_secure,      u_ast, clk_ast_rng_i