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[csrng/rtl] Remove the bencack FIFO from ctr_drbg_upd
This removal requires slight adaptions to the handshaking done with block_encrypt as well as the removal of a complex SVA from the tb. No functional or timing impact; the response data from block_encrypt even still feed into registers. Signed-off-by: Florian Glaser <[email protected]>
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-175
lines changed

14 files changed

+47
-175
lines changed

‎hw/ip/csrng/data/csrng.hjson‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -746,15 +746,6 @@
746746
This bit will stay set until the next reset.
747747
'''
748748
}
749-
{ bits: "7",
750-
name: "SFIFO_BENCACK_ERR",
751-
desc: '''
752-
This bit will be set to one when an error has been detected for the
753-
bencack FIFO. The type of error is reflected in the type status
754-
bits (bits 28 through 30 of this register).
755-
This bit will stay set until the next reset.
756-
'''
757-
}
758749
{ bits: "9",
759750
name: "SFIFO_FINAL_ERR",
760751
desc: '''

‎hw/ip/csrng/doc/registers.md‎

Lines changed: 3 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
555555
Hardware detection of error conditions status register
556556
- Offset: `0x54`
557557
- Reset default: `0x0`
558-
- Reset mask: `0x77f0fe9b`
558+
- Reset mask: `0x77f0fe1b`
559559

560560
### Fields
561561

562562
```wavejson
563-
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
563+
{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
564564
```
565565

566566
| Bits | Type | Reset | Name |
@@ -585,9 +585,7 @@ Hardware detection of error conditions status register
585585
| 11 | ro | 0x0 | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
586586
| 10 | ro | 0x0 | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
587587
| 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) |
588-
| 8 | | | Reserved |
589-
| 7 | ro | 0x0 | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err) |
590-
| 6:5 | | | Reserved |
588+
| 8:5 | | | Reserved |
591589
| 4 | ro | 0x0 | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err) |
592590
| 3 | ro | 0x0 | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err) |
593591
| 2 | | | Reserved |
@@ -697,12 +695,6 @@ final FIFO. The type of error is reflected in the type status
697695
bits (bits 28 through 30 of this register).
698696
This bit will stay set until the next reset.
699697

700-
### ERR_CODE . SFIFO_BENCACK_ERR
701-
This bit will be set to one when an error has been detected for the
702-
bencack FIFO. The type of error is reflected in the type status
703-
bits (bits 28 through 30 of this register).
704-
This bit will stay set until the next reset.
705-
706698
### ERR_CODE . SFIFO_KEYVRC_ERR
707699
This bit will be set to one when an error has been detected for the
708700
keyvrc FIFO. The type of error is reflected in the type status

‎hw/ip/csrng/dv/env/csrng_env_pkg.sv‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,6 @@ package csrng_env_pkg;
5858
sfifo_genbits_error = 1,
5959
sfifo_rcstage_error = 3,
6060
sfifo_keyvrc_error = 4,
61-
sfifo_bencack_error = 7,
6261
sfifo_final_error = 9,
6362
sfifo_gbencack_error = 10,
6463
sfifo_grcstage_error = 11,
@@ -84,7 +83,6 @@ package csrng_env_pkg;
8483
sfifo_genbits_err = 1,
8584
sfifo_rcstage_err = 3,
8685
sfifo_keyvrc_err = 4,
87-
sfifo_bencack_err = 7,
8886
sfifo_final_err = 9,
8987
sfifo_gbencack_err = 10,
9088
sfifo_grcstage_err = 11,
@@ -107,7 +105,6 @@ package csrng_env_pkg;
107105
sfifo_genbits_err_test = 27,
108106
sfifo_rcstage_err_test = 29,
109107
sfifo_keyvrc_err_test = 30,
110-
sfifo_bencack_err_test = 33,
111108
sfifo_final_err_test = 35,
112109
sfifo_gbencack_err_test = 36,
113110
sfifo_grcstage_err_test = 37,
@@ -132,7 +129,6 @@ package csrng_env_pkg;
132129
SFIFO_GENBITS_ERR = 1,
133130
SFIFO_RCSTAGE_ERR = 3,
134131
SFIFO_KEYVRC_ERR = 4,
135-
SFIFO_BENCACK_ERR = 7,
136132
SFIFO_FINAL_ERR = 9,
137133
SFIFO_GBENCACK_ERR = 10,
138134
SFIFO_GRCSTAGE_ERR = 11,
@@ -171,7 +167,6 @@ package csrng_env_pkg;
171167
sfifo_grcstage = 4,
172168
sfifo_gbencack = 5,
173169
sfifo_final = 6,
174-
sfifo_bencack = 8,
175170
sfifo_keyvrc = 11,
176171
sfifo_rcstage = 12,
177172
sfifo_genbits = 14,

‎hw/ip/csrng/dv/env/csrng_path_if.sv‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,7 @@ interface csrng_path_if
1919
".u_csrng_cmd_stage.", fifo_name, "_", which_path};
2020
"sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
2121
fifo_name, "_", which_path};
22-
"sfifo_bencack", "sfifo_final": return
23-
{core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
22+
"sfifo_final": return {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
2423
"sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
2524
return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),
2625
"_", which_path};

‎hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv‎

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,7 @@ class csrng_err_vseq extends csrng_base_vseq;
102102
case (cfg.which_err_code) inside
103103
sfifo_cmd_err, sfifo_genbits_err, sfifo_rcstage_err, sfifo_keyvrc_err,
104104
sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
105-
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err,
106-
sfifo_bencack_err, sfifo_ggenreq_err: begin
105+
sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_ggenreq_err: begin
107106
fld = csr.get_field_by_name(fld_name);
108107
fifo_base_path = fld_name.substr(0, last_index-1);
109108

@@ -115,8 +114,7 @@ class csrng_err_vseq extends csrng_base_vseq;
115114
`uvm_info(`gfn, $sformatf("Forcing this FIFO error type %s", cfg.which_fifo_err.name()),
116115
UVM_MEDIUM)
117116

118-
if (cfg.which_err_code == sfifo_ggenreq_err ||
119-
cfg.which_err_code == sfifo_bencack_err) begin
117+
if (cfg.which_err_code == sfifo_ggenreq_err) begin
120118
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, fld,
121119
1'b1, cfg.which_fifo_err);
122120

@@ -263,8 +261,7 @@ class csrng_err_vseq extends csrng_base_vseq;
263261
value1 = fifo_err_value[0][path_key];
264262
value2 = fifo_err_value[1][path_key];
265263

266-
if (cfg.which_err_code == fifo_read_error &&
267-
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin
264+
if ((cfg.which_err_code == fifo_read_error) && (cfg.which_fifo == sfifo_ggenreq)) begin
268265
force_fifo_err_exception(path1, path2, 1'b1, 1'b0, 1'b0, fld, 1'b1);
269266

270267
// For sfifo_gadstage the down stream FIFO also takes inputs from sources other than
@@ -302,8 +299,7 @@ class csrng_err_vseq extends csrng_base_vseq;
302299
csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val));
303300
cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
304301
end
305-
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test,
306-
sfifo_keyvrc_err_test, sfifo_bencack_err_test,
302+
sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test, sfifo_keyvrc_err_test,
307303
sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
308304
sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
309305
sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_gen_sm_err_test,

‎hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -223,15 +223,14 @@ class csrng_intr_vseq extends csrng_base_vseq;
223223
sfifo_cmd_error, sfifo_genbits_error, sfifo_rcstage_error,
224224
sfifo_keyvrc_error, sfifo_final_error, sfifo_gbencack_error,
225225
sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error,
226-
sfifo_cmdid_error, sfifo_bencack_error, sfifo_ggenreq_error: begin
226+
sfifo_cmdid_error, sfifo_ggenreq_error: begin
227227
fifo_base_path = fld_name.substr(0, last_index-1);
228228

229229
foreach (path_exts[i]) begin
230230
fifo_forced_paths[i] = cfg.csrng_path_vif.fifo_err_path(cfg.NHwApps, fifo_base_path,
231231
path_exts[i]);
232232
end
233-
if (cfg.which_fatal_err == sfifo_bencack_error ||
234-
cfg.which_fatal_err == sfifo_ggenreq_error) begin
233+
if (cfg.which_fatal_err == sfifo_ggenreq_error) begin
235234
force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts,
236235
ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err);
237236
end else begin
@@ -308,8 +307,7 @@ class csrng_intr_vseq extends csrng_base_vseq;
308307
value1 = fifo_err_value[0][path_key];
309308
value2 = fifo_err_value[1][path_key];
310309

311-
if (cfg.which_fatal_err == fifo_read_error &&
312-
((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin
310+
if ((cfg.which_fatal_err == fifo_read_error) && (cfg.which_fifo == sfifo_ggenreq)) begin
313311
force_fifo_err_exception(path1, path2, value1, value2, 1'b0, ral.intr_state.cs_fatal_err,
314312
1'b1);
315313
end else begin

‎hw/ip/csrng/dv/tb.sv‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -150,14 +150,6 @@ module tb;
150150
[csrng_pkg::BencDataWidth-1 -: csrng_pkg::BlkLen]) !=
151151
$past(`BLOCK_ENCRYPT_PATH.cipher_data_out, 2), clk, !rst_n)
152152

153-
`define CTR_DRBG_UPD tb.dut.u_csrng_core.u_csrng_ctr_drbg_upd
154-
`define CTR_DRBG_UPD_FIFO `CTR_DRBG_UPD.u_prim_fifo_sync_bencack.gen_singleton_fifo
155-
`ASSERT(CsrngSecCmAesCipherDataRegLocalEscUpd,
156-
$rose(`CTR_DRBG_UPD_FIFO.full_q) && `BLOCK_ENCRYPT_PATH.cipher_sm_err_o |=>
157-
$past(`CTR_DRBG_UPD_FIFO.storage
158-
[csrng_pkg::BencDataWidth-1 -: csrng_pkg::BlkLen]) !=
159-
$past(`BLOCK_ENCRYPT_PATH.cipher_data_out, 2), clk, !rst_n)
160-
161153
// Assertion controls
162154
`DV_ASSERT_CTRL("EntropySrcIf_ReqHighUntilAck_A_CTRL", entropy_src_if.ReqHighUntilAck_A)
163155
`DV_ASSERT_CTRL("EntropySrcIf_AckAssertedOnlyWhenReqAsserted_A_CTRL",

‎hw/ip/csrng/rtl/csrng_block_encrypt.sv‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -116,7 +116,6 @@ module csrng_block_encrypt import csrng_pkg::*; #(
116116
.state_o (state_done)
117117
);
118118

119-
120119
//--------------------------------------------
121120
// cmd / id tracking fifo
122121
//--------------------------------------------
@@ -144,18 +143,22 @@ module csrng_block_encrypt import csrng_pkg::*; #(
144143
assign sfifo_cmdid_wdata = {req_data_i.inst_id,
145144
req_data_i.cmd};
146145

147-
assign req_rdy_o = (cipher_in_ready == aes_pkg::SP2V_HIGH);
148-
149146
assign rsp_data_o = '{
150147
inst_id: sfifo_cmdid_rdata[CmdWidth +: InstIdWidth],
151148
cmd: sfifo_cmdid_rdata[0 +: CmdWidth],
152149
key: '0, // unused in rsp path
153150
v: cipher_data_out
154151
};
155152

156-
assign rsp_vld_o = rsp_rdy_i && (cipher_out_valid == aes_pkg::SP2V_HIGH);
153+
// The cipher determines whether the response is ready for consumption
154+
assign rsp_vld_o = (cipher_out_valid == aes_pkg::SP2V_HIGH);
155+
156+
// Type conversion for AES compatibility
157+
assign req_rdy_o = (cipher_in_ready == aes_pkg::SP2V_HIGH);
157158
assign cipher_out_ready = rsp_rdy_i ? aes_pkg::SP2V_HIGH : aes_pkg::SP2V_LOW;
158-
assign sfifo_cmdid_rrdy = rsp_vld_o;
159+
160+
// Empty the cmdid FIFO when the data response is consumed
161+
assign sfifo_cmdid_rrdy = rsp_rdy_i && rsp_vld_o;
159162

160163
assign fifo_cmdid_err_o =
161164
{( sfifo_cmdid_wvld && !sfifo_cmdid_wrdy),

‎hw/ip/csrng/rtl/csrng_core.sv‎

Lines changed: 2 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -134,8 +134,6 @@ module csrng_core import csrng_pkg::*; #(
134134
logic [2:0] ctr_drbg_cmd_sfifo_rcstage_err;
135135
logic ctr_drbg_cmd_sfifo_keyvrc_err_sum;
136136
logic [2:0] ctr_drbg_cmd_sfifo_keyvrc_err;
137-
logic ctr_drbg_upd_sfifo_bencack_err_sum;
138-
logic [2:0] ctr_drbg_upd_sfifo_bencack_err;
139137
logic ctr_drbg_upd_sfifo_final_err_sum;
140138
logic [2:0] ctr_drbg_upd_sfifo_final_err;
141139
logic ctr_drbg_gen_sfifo_gbencack_err_sum;
@@ -422,7 +420,6 @@ module csrng_core import csrng_pkg::*; #(
422420
(|cmd_stage_sfifo_genbits_err_sum) ||
423421
ctr_drbg_cmd_sfifo_rcstage_err_sum ||
424422
ctr_drbg_cmd_sfifo_keyvrc_err_sum ||
425-
ctr_drbg_upd_sfifo_bencack_err_sum ||
426423
ctr_drbg_upd_sfifo_final_err_sum ||
427424
ctr_drbg_gen_sfifo_gbencack_err_sum ||
428425
ctr_drbg_gen_sfifo_grcstage_err_sum ||
@@ -442,8 +439,6 @@ module csrng_core import csrng_pkg::*; #(
442439
err_code_test_bit[3];
443440
assign ctr_drbg_cmd_sfifo_keyvrc_err_sum = (|ctr_drbg_cmd_sfifo_keyvrc_err) ||
444441
err_code_test_bit[4];
445-
assign ctr_drbg_upd_sfifo_bencack_err_sum = (|ctr_drbg_upd_sfifo_bencack_err) ||
446-
err_code_test_bit[7];
447442
assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) ||
448443
err_code_test_bit[9];
449444
assign ctr_drbg_gen_sfifo_gbencack_err_sum = (|ctr_drbg_gen_sfifo_gbencack_err) ||
@@ -480,7 +475,6 @@ module csrng_core import csrng_pkg::*; #(
480475
ctr_drbg_gen_sfifo_grcstage_err[2] ||
481476
ctr_drbg_gen_sfifo_gbencack_err[2] ||
482477
ctr_drbg_upd_sfifo_final_err[2] ||
483-
ctr_drbg_upd_sfifo_bencack_err[2] ||
484478
ctr_drbg_cmd_sfifo_keyvrc_err[2] ||
485479
ctr_drbg_cmd_sfifo_rcstage_err[2] ||
486480
(|cmd_stage_sfifo_genbits_err_wr) ||
@@ -494,7 +488,6 @@ module csrng_core import csrng_pkg::*; #(
494488
ctr_drbg_gen_sfifo_grcstage_err[1] ||
495489
ctr_drbg_gen_sfifo_gbencack_err[1] ||
496490
ctr_drbg_upd_sfifo_final_err[1] ||
497-
ctr_drbg_upd_sfifo_bencack_err[1] ||
498491
ctr_drbg_cmd_sfifo_keyvrc_err[1] ||
499492
ctr_drbg_cmd_sfifo_rcstage_err[1] ||
500493
(|cmd_stage_sfifo_genbits_err_rd) ||
@@ -508,7 +501,6 @@ module csrng_core import csrng_pkg::*; #(
508501
ctr_drbg_gen_sfifo_grcstage_err[0] ||
509502
ctr_drbg_gen_sfifo_gbencack_err[0] ||
510503
ctr_drbg_upd_sfifo_final_err[0] ||
511-
ctr_drbg_upd_sfifo_bencack_err[0] ||
512504
ctr_drbg_cmd_sfifo_keyvrc_err[0] ||
513505
ctr_drbg_cmd_sfifo_rcstage_err[0] ||
514506
(|cmd_stage_sfifo_genbits_err_st) ||
@@ -532,10 +524,6 @@ module csrng_core import csrng_pkg::*; #(
532524
assign hw2reg.err_code.sfifo_keyvrc_err.de = cs_enable_fo[6] &&
533525
ctr_drbg_cmd_sfifo_keyvrc_err_sum;
534526

535-
assign hw2reg.err_code.sfifo_bencack_err.d = 1'b1;
536-
assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable_fo[9] &&
537-
ctr_drbg_upd_sfifo_bencack_err_sum;
538-
539527
assign hw2reg.err_code.sfifo_final_err.d = 1'b1;
540528
assign hw2reg.err_code.sfifo_final_err.de = cs_enable_fo[11] &&
541529
ctr_drbg_upd_sfifo_final_err_sum;
@@ -1267,7 +1255,6 @@ module csrng_core import csrng_pkg::*; #(
12671255
.block_encrypt_rsp_data_i(block_encrypt_rsp_data),
12681256

12691257
.ctr_err_o (ctr_drbg_upd_v_ctr_err),
1270-
.fifo_bencack_err_o (ctr_drbg_upd_sfifo_bencack_err),
12711258
.fifo_final_err_o (ctr_drbg_upd_sfifo_final_err),
12721259
.sm_block_enc_req_err_o(drbg_updbe_sm_err),
12731260
.sm_block_enc_rsp_err_o(drbg_updob_sm_err)
@@ -1477,10 +1464,8 @@ module csrng_core import csrng_pkg::*; #(
14771464
logic unused_state_db_inst_state;
14781465

14791466
assign unused_err_code_test_bit = err_code_test_bit[27] || (|err_code_test_bit[19:16]) ||
1480-
err_code_test_bit[8] || (|err_code_test_bit[6:5]) ||
1481-
err_code_test_bit[2];
1482-
assign unused_enable_fo = cs_enable_fo[42] || cs_enable_fo[10] || (|cs_enable_fo[8:7]) ||
1483-
cs_enable_fo[4];
1467+
(|err_code_test_bit[8:5]) || err_code_test_bit[2];
1468+
assign unused_enable_fo = cs_enable_fo[42] || (|cs_enable_fo[10:7]) || cs_enable_fo[4];
14841469
assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
14851470
assign unused_int_state_val = (|reg2hw.int_state_val.q);
14861471
assign unused_reseed_interval = reg2hw.reseed_interval.qe;

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