Skip to content

Commit 152fdc2

Browse files
loiclefortRazer6
loiclefort
authored and
Razer6
committed
[hw,darjeeling] Add support for building a Verilator sim
Co-authored-by: Robert Schillin <[email protected]> Signed-off-by: Loïc Lefort <[email protected]>
1 parent a724e3a commit 152fdc2

File tree

15 files changed

+1674
-7
lines changed

15 files changed

+1674
-7
lines changed

‎hw/BUILD‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
load("@rules_pkg//pkg:mappings.bzl", "pkg_files")
66
load("//rules:fusesoc.bzl", "fusesoc_build")
77
load("@rules_python//python:defs.bzl", "py_library")
8+
load("//hw/top:defs.bzl", "opentitan_select_top_attr")
89

910
# This configuration exposes fusesoc's "verilator_options" option to the
1011
# command line. This is intended to allow CI to specifically build a single
@@ -100,9 +101,7 @@ fusesoc_build(
100101
],
101102
data = ["//hw/ip/otbn:rtl_files"],
102103
make_options = ":make_options",
103-
output_groups = {
104-
"binary": ["lowrisc_dv_top_earlgrey_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"],
105-
},
104+
output_groups = opentitan_select_top_attr("top_verilator_binary"),
106105
systems = ["lowrisc:dv:chip_verilator_sim"],
107106
tags = [
108107
"manual",
@@ -177,7 +176,7 @@ filegroup(
177176
# dv_macros are needed by Ibex, so include this back in.
178177
"//hw/dv/sv:dv_macros",
179178
"//hw/ip:rtl_files",
180-
"//hw/top_earlgrey:rtl_files",
179+
"//hw/top:rtl_files",
181180
],
182181
visibility = ["//visibility:public"],
183182
)

‎hw/top/BUILD‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -89,6 +89,11 @@ opentitan_alias_top_attr(
8989
attr_name = "otp_map",
9090
)
9191

92+
opentitan_alias_top_attr(
93+
name = "rtl_files",
94+
attr_name = "top_rtl",
95+
)
96+
9297
# For each top, create a selecting alias for the seed.
9398
[
9499
alias(

‎hw/top_darjeeling/BUILD‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,16 @@ load(
1212

1313
package(default_visibility = ["//visibility:public"])
1414

15+
filegroup(
16+
name = "rtl_files",
17+
srcs = glob(["**"]) + [
18+
"//hw/top_darjeeling/data:all_files",
19+
"//hw/top_darjeeling/dv/verilator:all_files",
20+
"//hw/top_darjeeling/ip:rtl_files",
21+
"//hw/top_darjeeling/sw:all_files",
22+
],
23+
)
24+
1525
filegroup(
1626
name = "doc_files",
1727
srcs = glob(["**/*.md"]) + [

‎hw/top_darjeeling/chip_darjeeling_verilator.core‎

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
1+
CAPI=2:
2+
# Copyright lowRISC contributors (OpenTitan project).
3+
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
4+
# SPDX-License-Identifier: Apache-2.0
5+
name: "lowrisc:systems:chip_darjeeling_verilator:0.1"
6+
description: "Darjeeling toplevel for simulation with Verilator"
7+
filesets:
8+
files_sim_verilator:
9+
depend:
10+
- lowrisc:systems:top_darjeeling:0.1
11+
- lowrisc:systems:top_darjeeling_pkg
12+
- lowrisc:ibex:ibex_tracer
13+
- lowrisc:prim:clock_div
14+
- lowrisc:systems:top_darjeeling_ast
15+
- lowrisc:darjeeling_systems:scan_role_pkg
16+
# TODO(#27347): prim_legacy_pkg is deprecated
17+
- lowrisc:prim:prim_legacy_pkg
18+
- lowrisc:prim_generic:all
19+
files:
20+
- rtl/chip_darjeeling_verilator.sv: { file_type: systemVerilogSource }
21+
22+
parameters:
23+
AST_BYPASS_CLK:
24+
datatype: bool
25+
paramtype: vlogdefine
26+
27+
targets:
28+
default: &default_target
29+
filesets:
30+
- files_sim_verilator
31+
parameters:
32+
- AST_BYPASS_CLK=true
33+
toplevel: chip_darjeeling_verilator
34+
tools:
35+
verilator:
36+
verilator_options:
37+
# required to support OTP constants
38+
- "--max-num-width 131072"
39+
40+
lint:
41+
<<: *default_target
42+
default_tool: verilator
43+
tools:
44+
verilator:
45+
mode: lint-only
46+
verilator_options:
47+
- "-Wall"

‎hw/top_darjeeling/defs.bzl‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@ DARJEELING = opentitan_top(
1111
name = "darjeeling",
1212
hjson = "//hw/top_darjeeling/data/autogen:top_darjeeling.gen.hjson",
1313
top_lib = "//hw/top_darjeeling/sw/autogen:top_darjeeling",
14+
top_rtl = "//hw/top_darjeeling:rtl_files",
15+
top_verilator_binary = {"binary": ["lowrisc_dv_top_darjeeling_chip_verilator_sim_0.1/sim-verilator/Vchip_sim_tb"]},
1416
top_ld = "//hw/top_darjeeling/sw/autogen:top_darjeeling_memory",
1517
otp_map = "//hw/top_darjeeling/data/otp:otp_ctrl_mmap.hjson",
1618
std_otp_overlay = DARJEELING_STD_OTP_OVERLAYS,

‎hw/top_darjeeling/dv/verilator/BUILD‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,10 @@
1+
# Copyright lowRISC contributors (OpenTitan project).
2+
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
3+
# SPDX-License-Identifier: Apache-2.0
4+
5+
package(default_visibility = ["//visibility:public"])
6+
7+
filegroup(
8+
name = "all_files",
9+
srcs = glob(["**"]),
10+
)

‎hw/top_darjeeling/dv/verilator/chip_sim.core‎

Lines changed: 132 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,132 @@
1+
CAPI=2:
2+
# Copyright lowRISC contributors (OpenTitan project).
3+
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
4+
# SPDX-License-Identifier: Apache-2.0
5+
name: "lowrisc:dv:top_darjeeling_chip_verilator_sim:0.1"
6+
description: "Darjeeling toplevel for simulation with Verilator"
7+
virtual:
8+
- lowrisc:dv:chip_verilator_sim
9+
10+
filesets:
11+
files_sim_verilator:
12+
depend:
13+
- lowrisc:dv_dpi_c:uartdpi
14+
- lowrisc:dv_dpi_sv:uartdpi
15+
- lowrisc:dv_dpi_c:gpiodpi
16+
- lowrisc:dv_dpi_sv:gpiodpi
17+
- lowrisc:dv_dpi_c:jtagdpi
18+
- lowrisc:dv_dpi_sv:jtagdpi
19+
- lowrisc:dv_dpi_c:dmidpi
20+
- lowrisc:dv_dpi_sv:dmidpi
21+
- lowrisc:dv_dpi_c:spidpi
22+
- lowrisc:dv_dpi_sv:spidpi
23+
- lowrisc:dv_verilator:memutil_verilator
24+
- lowrisc:dv_verilator:simutil_verilator
25+
- lowrisc:dv:sim_sram
26+
- lowrisc:dv:sw_test_status
27+
- lowrisc:dv:dv_test_status
28+
- lowrisc:systems:chip_darjeeling_verilator
29+
files:
30+
- chip_sim_tb.sv: { file_type: systemVerilogSource }
31+
- chip_sim_tb.cc: { file_type: cppSource }
32+
33+
parameters:
34+
RVFI:
35+
datatype: bool
36+
paramtype: vlogdefine
37+
description: Enable the RISC-V Verification Interface and instruction tracing
38+
VERILATOR_MEM_BASE:
39+
datatype: int
40+
paramtype: vlogdefine
41+
description: Main memory mem base.
42+
VERILATOR_TEST_STATUS_ADDR:
43+
datatype: int
44+
paramtype: vlogdefine
45+
description: Verilator specific address to write to, to report the test status. This value should be at a word offset in the unmapped address space.
46+
rom0init:
47+
datatype : file
48+
description : Application to load into Base ROM (in Verilog hex format)
49+
paramtype : cmdlinearg
50+
rom1init:
51+
datatype : file
52+
description : Application to load into Second ROM (in Verilog hex format)
53+
paramtype : cmdlinearg
54+
otpinit:
55+
datatype : file
56+
description : Image to load into the OTP (in Verilog hex format)
57+
paramtype : cmdlinearg
58+
ctnraminit:
59+
datatype : file
60+
description : Application to load into CTN RAM (in Verilog hex format)
61+
paramtype : cmdlinearg
62+
DMIDirectTAP:
63+
datatype: bool
64+
paramtype: vlogdefine
65+
default: true
66+
description: Replace JTAG TAP with an OpenOCD direct connection
67+
UART_LOG_uart0:
68+
datatype: str
69+
paramtype: plusarg
70+
description: Write a log of output from uart0 to the given log file. Use "-" for stdout.
71+
RV_CORE_IBEX_SIM_SRAM:
72+
datatype: bool
73+
paramtype: vlogdefine
74+
description: Disconnect the TL data output of rv_core_ibex so that we can attach the simulation SRAM.
75+
76+
targets:
77+
default: &default_target
78+
filesets:
79+
- files_sim_verilator
80+
toplevel: chip_sim_tb
81+
82+
sim:
83+
parameters:
84+
- RVFI=true
85+
- VERILATOR_MEM_BASE=0x10000000
86+
- VERILATOR_TEST_STATUS_ADDR=0x211f0440
87+
- rom0init
88+
- rom1init
89+
- otpinit
90+
- ctnraminit
91+
- DMIDirectTAP
92+
- RV_CORE_IBEX_SIM_SRAM=true
93+
default_tool: verilator
94+
filesets:
95+
- files_sim_verilator
96+
toplevel: chip_sim_tb
97+
tools:
98+
verilator:
99+
mode: cc
100+
verilator_options:
101+
# Disabling tracing reduces compile times but doesn't have a
102+
# huge influence on runtime performance.
103+
- '--trace'
104+
- '--trace-fst' # this requires -DVM_TRACE_FMT_FST in CFLAGS below!
105+
# Remove FST options for VCD trace
106+
- '--trace-structs'
107+
- '--trace-params'
108+
- '--trace-max-array 1024'
109+
- '--unroll-count 512'
110+
# TODO: Variable expansion depends on edalize internals. Find better solution.
111+
# (Applies to LDFLAGS expansion below as well)
112+
- '-CFLAGS "$(CFLAGS_FOR_BUILD) -std=c++17 -Wall -DVM_TRACE_FMT_FST -DVL_USER_STOP -DTOPLEVEL_NAME=chip_sim_tb"'
113+
- '-LDFLAGS "$(LDFLAGS_FOR_BUILD) -pthread -lutil -lelf"'
114+
- '-Wall'
115+
# Execute simulation with four threads by default, which works best
116+
# with four physical CPU cores.
117+
# Users can override this setting by appending e.g.
118+
# --verilator_options '--threads 2'
119+
# to the end of the fusesoc invocation when compiling the simulation.
120+
- '--threads 4'
121+
# XXX: Cleanup all warnings and remove this option
122+
# (or make it more fine-grained at least)
123+
- '-Wno-fatal'
124+
125+
lint:
126+
<<: *default_target
127+
default_tool: verilator
128+
tools:
129+
verilator:
130+
mode: lint-only
131+
verilator_options:
132+
- "-Wall"

‎hw/top_darjeeling/dv/verilator/chip_sim_tb.cc‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
// Copyright lowRISC contributors (OpenTitan project).
2+
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
3+
// SPDX-License-Identifier: Apache-2.0
4+
5+
#include <algorithm>
6+
#include <iostream>
7+
#include <string>
8+
#include <vector>
9+
10+
#include "verilated_toplevel.h"
11+
#include "verilator_memutil.h"
12+
#include "verilator_sim_ctrl.h"
13+
14+
int main(int argc, char **argv) {
15+
chip_sim_tb top;
16+
VerilatorMemUtil memutil;
17+
VerilatorSimCtrl &simctrl = VerilatorSimCtrl::GetInstance();
18+
simctrl.SetTop(&top, &top.clk_i, &top.rst_ni,
19+
VerilatorSimCtrlFlags::ResetPolarityNegative);
20+
21+
std::string dut_scope("TOP.chip_sim_tb.u_dut");
22+
std::string top_scope(dut_scope + ".top_darjeeling");
23+
std::string ram_name("gen_ram_inst[0].u_mem");
24+
std::string ram1p_adv_scope("u_prim_ram_1p_adv." + ram_name);
25+
26+
MemArea rom0(top_scope + (".u_rom_ctrl0.gen_rom_scramble_enabled.u_rom.u_rom"
27+
".u_prim_rom"),
28+
0x8000 / 4, 4);
29+
MemArea rom1(top_scope + (".u_rom_ctrl1.gen_rom_scramble_enabled.u_rom.u_rom"
30+
".u_prim_rom"),
31+
0x10000 / 4, 4);
32+
MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4,
33+
4);
34+
MemArea ctn_ram(dut_scope + ".u_prim_ram_1p_adv_ctn." + ram_name,
35+
0x100000 / 4, 4);
36+
MemArea otp(top_scope + ".u_otp_macro." + ram1p_adv_scope, 0x10000 / 4, 4);
37+
38+
memutil.RegisterMemoryArea("rom0", 0x8000, &rom0);
39+
memutil.RegisterMemoryArea("rom1", 0x20000, &rom1);
40+
memutil.RegisterMemoryArea("ram", 0x10000000u, &ram);
41+
memutil.RegisterMemoryArea("ctn_ram", 0x41000000u, &ctn_ram);
42+
memutil.RegisterMemoryArea("otp", 0x30000000u /* (bogus LMA) */, &otp);
43+
simctrl.RegisterExtension(&memutil);
44+
45+
// The initial reset delay must be long enough such that pwr/rst/clkmgr will
46+
// release clocks to the entire design. This allows for synchronous resets
47+
// to appropriately propagate.
48+
// The reset duration must be appropriately sized to the divider for clk_aon
49+
// in chip_darjeeling_verilator.sv. It must be at least 2 cycles of clk_aon.
50+
simctrl.SetInitialResetDelay(20000);
51+
simctrl.SetResetDuration(10);
52+
53+
std::cout << "Simulation of OpenTitan Darjeeling" << std::endl
54+
<< "==================================" << std::endl
55+
<< std::endl;
56+
57+
return simctrl.Exec(argc, argv).first;
58+
}

0 commit comments

Comments
 (0)