[csrng/rtl] Remove the keyvrc FIFO from ctr_drbg_cmd

This commit removes the last FIFO from the ctr_drbg_cmd module. Since
the request and response ready signals are now in many cases asserted in
the same cycle, slight adaptions to the main FSM are also necessary.

Signed-off-by: Florian Glaser <[email protected]>

Author: glaserf

hw/ip/csrng/data/csrng.hjson

@@ -731,15 +731,6 @@
                 This bit will stay set until the next reset.
                 '''
         }
-        { bits: "4",
-          name: "SFIFO_KEYVRC_ERR",
-          desc: '''
-                This bit will be set to one when an error has been detected for the
-                keyvrc FIFO. The type of error is reflected in the type status
-                bits (bits 28 through 30 of this register).
-                This bit will stay set until the next reset.
-                '''
-        }
         { bits: "9",
           name: "SFIFO_FINAL_ERR",
           desc: '''

hw/ip/csrng/doc/registers.md

@@ -555,12 +555,12 @@ Writing a zero resets this status bit.
 Hardware detection of error conditions status register
 - Offset: `0x54`
 - Reset default: `0x0`
-- Reset mask: `0x7ff0fe13`
+- Reset mask: `0x7ff0fe03`
 
 ### Fields
 
 ```wavejson
-{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
+{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 7}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_CMD_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}}
 ```
 
 |  Bits  |  Type  |  Reset  | Name                                                |
@@ -585,9 +585,7 @@ Hardware detection of error conditions status register
 |   11   |   ro   |   0x0   | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) |
 |   10   |   ro   |   0x0   | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) |
 |   9    |   ro   |   0x0   | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err)       |
-|  8:5   |        |         | Reserved                                            |
-|   4    |   ro   |   0x0   | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err)     |
-|  3:2   |        |         | Reserved                                            |
+|  8:2   |        |         | Reserved                                            |
 |   1    |   ro   |   0x0   | [SFIFO_GENBITS_ERR](#err_code--sfifo_genbits_err)   |
 |   0    |   ro   |   0x0   | [SFIFO_CMD_ERR](#err_code--sfifo_cmd_err)           |
 
@@ -700,12 +698,6 @@ final FIFO. The type of error is reflected in the type status
 bits (bits 28 through 30 of this register).
 This bit will stay set until the next reset.
 
-### ERR_CODE . SFIFO_KEYVRC_ERR
-This bit will be set to one when an error has been detected for the
-keyvrc FIFO. The type of error is reflected in the type status
-bits (bits 28 through 30 of this register).
-This bit will stay set until the next reset.
-
 ### ERR_CODE . SFIFO_GENBITS_ERR
 This bit will be set to one when an error has been detected for the
 command stage genbits FIFO. The type of error is reflected in the type status

hw/ip/csrng/dv/env/csrng_env_pkg.sv

@@ -58,7 +58,6 @@ package csrng_env_pkg;
   typedef enum int {
     sfifo_cmd_error      = 0,
     sfifo_genbits_error  = 1,
-    sfifo_keyvrc_error   = 2,
     sfifo_final_error    = 3,
     sfifo_gbencack_error = 4,
     sfifo_grcstage_error = 5,
@@ -83,7 +82,6 @@ package csrng_env_pkg;
     // ERR_CODE
     sfifo_cmd_err           = 0,
     sfifo_genbits_err       = 1,
-    sfifo_keyvrc_err        = 2,
     sfifo_final_err         = 3,
     sfifo_gbencack_err      = 4,
     sfifo_grcstage_err      = 5,
@@ -105,7 +103,6 @@ package csrng_env_pkg;
     // ERR_CODE_TEST
     sfifo_cmd_err_test      = 21,
     sfifo_genbits_err_test  = 22,
-    sfifo_keyvrc_err_test   = 23,
     sfifo_final_err_test    = 24,
     sfifo_gbencack_err_test = 25,
     sfifo_grcstage_err_test = 26,
@@ -131,7 +128,6 @@ package csrng_env_pkg;
   typedef enum int {
     SFIFO_CMD_ERR      = 0,
     SFIFO_GENBITS_ERR  = 1,
-    SFIFO_KEYVRC_ERR   = 4,
     SFIFO_FINAL_ERR    = 9,
     SFIFO_GBENCACK_ERR = 10,
     SFIFO_GRCSTAGE_ERR = 11,
@@ -171,9 +167,8 @@ package csrng_env_pkg;
     sfifo_grcstage = 4,
     sfifo_gbencack = 5,
     sfifo_final    = 6,
-    sfifo_keyvrc   = 7,
-    sfifo_genbits  = 8,
-    sfifo_cmd      = 9
+    sfifo_genbits  = 7,
+    sfifo_cmd      = 8
   } which_fifo_e;
 
   typedef enum int {

hw/ip/csrng/dv/env/csrng_path_if.sv

@@ -17,8 +17,6 @@ interface csrng_path_if
     case (fifo_name) inside
       "sfifo_cmd", "sfifo_genbits": return {core_path, $sformatf(".gen_cmd_stage[%0d]", app),
                                             ".u_csrng_cmd_stage.", fifo_name, "_", which_path};
-      "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.",
-                                                               fifo_name, "_", which_path};
       "sfifo_final": return {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path};
       "sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits":
         return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1),

hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv

@@ -99,8 +99,7 @@ class csrng_err_vseq extends csrng_base_vseq;
                               cfg.which_app_err_alert, fld_name), UVM_MEDIUM)
 
     case (cfg.which_err_code) inside
-      sfifo_cmd_err, sfifo_genbits_err, sfifo_keyvrc_err,
-      sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
+      sfifo_cmd_err, sfifo_genbits_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err,
       sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_ggenreq_err: begin
         fld = csr.get_field_by_name(fld_name);
         fifo_base_path = fld_name.substr(0, last_index-1);
@@ -299,7 +298,7 @@ class csrng_err_vseq extends csrng_base_vseq;
         csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val));
         cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val));
       end
-      sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_keyvrc_err_test,
+      sfifo_cmd_err_test, sfifo_genbits_err_test,
       sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test,
       sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test,
       sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_cmd_sm_err_test,

hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv

@@ -220,10 +220,9 @@ class csrng_intr_vseq extends csrng_base_vseq;
     last_index = find_index("_", fld_name, "last");
 
     case (cfg.which_fatal_err) inside
-      sfifo_cmd_error, sfifo_genbits_error,
-      sfifo_keyvrc_error, sfifo_final_error, sfifo_gbencack_error,
-      sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error,
-      sfifo_cmdid_error, sfifo_ggenreq_error: begin
+      sfifo_cmd_error, sfifo_genbits_error, sfifo_final_error, sfifo_gbencack_error,
+      sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error, sfifo_cmdid_error,
+      sfifo_ggenreq_error: begin
         fifo_base_path = fld_name.substr(0, last_index-1);
 
         foreach (path_exts[i]) begin

hw/ip/csrng/rtl/csrng_core.sv

@@ -130,8 +130,6 @@ module csrng_core import csrng_pkg::*; #(
   logic                        main_sm_cmd_vld;
   logic                        clr_adata_packer;
 
-  logic                        ctr_drbg_cmd_sfifo_keyvrc_err_sum;
-  logic [2:0]                  ctr_drbg_cmd_sfifo_keyvrc_err;
   logic                        ctr_drbg_upd_sfifo_final_err_sum;
   logic [2:0]                  ctr_drbg_upd_sfifo_final_err;
   logic                        ctr_drbg_gen_sfifo_gbencack_err_sum;
@@ -419,7 +417,6 @@ module csrng_core import csrng_pkg::*; #(
   assign event_cs_fatal_err = (cs_enable_fo[1]  && (
          (|cmd_stage_sfifo_cmd_err_sum) ||
          (|cmd_stage_sfifo_genbits_err_sum) ||
-         ctr_drbg_cmd_sfifo_keyvrc_err_sum ||
          ctr_drbg_upd_sfifo_final_err_sum ||
          ctr_drbg_gen_sfifo_gbencack_err_sum ||
          ctr_drbg_gen_sfifo_grcstage_err_sum ||
@@ -435,8 +432,6 @@ module csrng_core import csrng_pkg::*; #(
          fatal_loc_events;
 
   // set fifo errors that are single instances of source
-  assign ctr_drbg_cmd_sfifo_keyvrc_err_sum = (|ctr_drbg_cmd_sfifo_keyvrc_err) ||
-         err_code_test_bit[4];
   assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) ||
          err_code_test_bit[9];
   assign ctr_drbg_gen_sfifo_gbencack_err_sum = (|ctr_drbg_gen_sfifo_gbencack_err) ||
@@ -468,7 +463,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_gen_sfifo_grcstage_err[2] ||
          ctr_drbg_gen_sfifo_gbencack_err[2] ||
          ctr_drbg_upd_sfifo_final_err[2] ||
-         ctr_drbg_cmd_sfifo_keyvrc_err[2] ||
          (|cmd_stage_sfifo_genbits_err_wr) ||
          (|cmd_stage_sfifo_cmd_err_wr) ||
          err_code_test_bit[28];
@@ -480,7 +474,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_gen_sfifo_grcstage_err[1] ||
          ctr_drbg_gen_sfifo_gbencack_err[1] ||
          ctr_drbg_upd_sfifo_final_err[1] ||
-         ctr_drbg_cmd_sfifo_keyvrc_err[1] ||
          (|cmd_stage_sfifo_genbits_err_rd) ||
          (|cmd_stage_sfifo_cmd_err_rd) ||
          err_code_test_bit[29];
@@ -492,7 +485,6 @@ module csrng_core import csrng_pkg::*; #(
          ctr_drbg_gen_sfifo_grcstage_err[0] ||
          ctr_drbg_gen_sfifo_gbencack_err[0] ||
          ctr_drbg_upd_sfifo_final_err[0] ||
-         ctr_drbg_cmd_sfifo_keyvrc_err[0] ||
          (|cmd_stage_sfifo_genbits_err_st) ||
          (|cmd_stage_sfifo_cmd_err_st) ||
          err_code_test_bit[30];
@@ -506,10 +498,6 @@ module csrng_core import csrng_pkg::*; #(
   assign hw2reg.err_code.sfifo_genbits_err.de = cs_enable_fo[3] &&
          (|cmd_stage_sfifo_genbits_err_sum);
 
-  assign hw2reg.err_code.sfifo_keyvrc_err.d = 1'b1;
-  assign hw2reg.err_code.sfifo_keyvrc_err.de = cs_enable_fo[6] &&
-         ctr_drbg_cmd_sfifo_keyvrc_err_sum;
-
   assign hw2reg.err_code.sfifo_final_err.d = 1'b1;
   assign hw2reg.err_code.sfifo_final_err.de = cs_enable_fo[11] &&
          ctr_drbg_upd_sfifo_final_err_sum;
@@ -1219,8 +1207,7 @@ module csrng_core import csrng_pkg::*; #(
     .update_rsp_rdy_o (cmd_upd_rsp_rdy),
     .update_rsp_data_i(upd_rsp_data),
 
-    .sm_err_o          (drbg_cmd_sm_err),
-    .fifo_keyvrc_err_o (ctr_drbg_cmd_sfifo_keyvrc_err)
+    .sm_err_o          (drbg_cmd_sm_err)
   );
 
   //-------------------------------------
@@ -1466,9 +1453,8 @@ module csrng_core import csrng_pkg::*; #(
   logic [SeedLen-1:0] unused_gen_rsp_pdata;
   logic               unused_state_db_inst_state;
 
-  assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[8:5]) ||
-                                    (|err_code_test_bit[3:2]);
-  assign unused_enable_fo = cs_enable_fo[42] || (|cs_enable_fo[9:7]) || |(cs_enable_fo[5:4]);
+  assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[8:2]);
+  assign unused_enable_fo = cs_enable_fo[42] || (|cs_enable_fo[9:4]);
   assign unused_reg2hw_genbits = (|reg2hw.genbits.q);
   assign unused_int_state_val = (|reg2hw.int_state_val.q);
   assign unused_reseed_interval = reg2hw.reseed_interval.qe;

hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv

@@ -41,32 +41,19 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; (
   input  csrng_upd_data_t    update_rsp_data_i,
 
   // Error status outputs
-  output logic               sm_err_o,
-  output logic         [2:0] fifo_keyvrc_err_o
+  output logic               sm_err_o
 );
 
-  localparam int KeyVRCFifoWidth  = CoreDataWidth + 1;
-
   // signals
   csrng_core_data_t   req_data;
   csrng_core_data_t   prep_core_data;
-  csrng_core_data_t   keyvrc_data;
-  logic               keyvrc_glast;
 
   logic [SeedLen-1:0] prep_seed_material;
   logic  [KeyLen-1:0] prep_key;
   logic  [BlkLen-1:0] prep_v;
   logic  [CtrLen-1:0] prep_rc;
   logic               bypass_upd;
 
-  // keyvrc fifo
-  logic                        sfifo_keyvrc_wvld;
-  logic                        sfifo_keyvrc_wrdy;
-  logic [KeyVRCFifoWidth-1:0]  sfifo_keyvrc_wdata;
-  logic                        sfifo_keyvrc_rvld;
-  logic                        sfifo_keyvrc_rrdy;
-  logic [KeyVRCFifoWidth-1:0]  sfifo_keyvrc_rdata;
-
 
   // Encoding generated with:
   // $ ./util/design/sparse-fsm-encode.py -d 3 -m 3 -n 5 \
@@ -98,7 +85,6 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; (
   // SEC_CM: UPDRSP.FSM.SPARSE
   `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, ReqIdle)
 
-
   //--------------------------------------------
   // Prepare/mux values for update step
   //--------------------------------------------
@@ -167,16 +153,16 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; (
   always_comb begin
     state_d = state_q;
     req_rdy_o = 1'b0;
+    rsp_vld_o = 1'b0;
     update_req_vld_o = 1'b0;
     update_rsp_rdy_o = 1'b0;
-    sfifo_keyvrc_wvld = 1'b0;
     sm_err_o = 1'b0;
 
     unique case (state_q)
       ReqIdle: begin
         if (bypass_upd) begin
-          req_rdy_o = enable_i && sfifo_keyvrc_wrdy;
-          sfifo_keyvrc_wvld = req_vld_i;
+          req_rdy_o = enable_i && rsp_rdy_i;
+          rsp_vld_o = req_vld_i;
         end else begin
           update_req_vld_o = req_vld_i;
           if (update_req_vld_o && update_req_rdy_i) begin
@@ -185,8 +171,8 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; (
         end
       end
       RspPend: begin
-        sfifo_keyvrc_wvld = update_rsp_vld_i;
-        update_rsp_rdy_o  = sfifo_keyvrc_wrdy;
+        rsp_vld_o = update_rsp_vld_i;
+        update_rsp_rdy_o = rsp_rdy_i;
         if (update_rsp_vld_i && update_rsp_rdy_o) begin
           req_rdy_o = 1'b1;
           state_d = ReqIdle;
@@ -202,66 +188,25 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; (
     endcase
   end
 
-
-  //--------------------------------------------
-  // final cmd block processing
-  //--------------------------------------------
-
-  prim_fifo_sync #(
-    .Width(KeyVRCFifoWidth),
-    .Pass(0),
-    .Depth(1),
-    .OutputZeroIfEmpty(1'b0)
-  ) u_prim_fifo_sync_keyvrc (
-    .clk_i   (clk_i),
-    .rst_ni  (rst_ni),
-    .clr_i   (!enable_i),
-    .wvalid_i(sfifo_keyvrc_wvld),
-    .wready_o(sfifo_keyvrc_wrdy),
-    .wdata_i (sfifo_keyvrc_wdata),
-    .rvalid_o(sfifo_keyvrc_rvld),
-    .rready_i(sfifo_keyvrc_rrdy),
-    .rdata_o (sfifo_keyvrc_rdata),
-    .full_o  (),
-    .depth_o (),
-    .err_o   ()
-  );
-
-  // Route either data from request input or update response into keyvrc FIFO
+  // Route either data from request input or update response to response output
   always_comb begin
-    keyvrc_data  = prep_core_data;
-    keyvrc_glast = req_glast_i;
-    if (prep_core_data.cmd == UNI) begin
+    rsp_data_o  = prep_core_data;
+    rsp_glast_o = req_glast_i;
+    if (req_data_i.cmd == UNI) begin
       // Zeroize everything but inst_id and cmd (?)
-      keyvrc_data = '{default: '0};
-      keyvrc_data.inst_id = prep_core_data.inst_id;
-      keyvrc_data.cmd     = prep_core_data.cmd;
+      rsp_data_o = '{default: '0};
+      rsp_data_o.inst_id = req_data_i.inst_id;
+      rsp_data_o.cmd     = req_data_i.cmd;
     end else if (!bypass_upd) begin
       // Update key and v with values from the update unit if
       // non-zero pdata were provided
-      keyvrc_data.key     = update_rsp_data_i.key;
-      keyvrc_data.v       = update_rsp_data_i.v;
-      keyvrc_data.inst_id = update_rsp_data_i.inst_id;
-      keyvrc_data.cmd     = update_rsp_data_i.cmd;
+      rsp_data_o.key     = update_rsp_data_i.key;
+      rsp_data_o.v       = update_rsp_data_i.v;
+      rsp_data_o.inst_id = update_rsp_data_i.inst_id;
+      rsp_data_o.cmd     = update_rsp_data_i.cmd;
     end
   end
 
-  assign sfifo_keyvrc_wdata = {keyvrc_glast,
-                               keyvrc_data};
-
-  assign sfifo_keyvrc_rrdy = rsp_rdy_i && sfifo_keyvrc_rvld;
-
-  // cmd response output assignments
-  assign {rsp_glast_o,
-          rsp_data_o} = sfifo_keyvrc_rdata;
-
-  assign rsp_vld_o = sfifo_keyvrc_rrdy;
-
-  assign fifo_keyvrc_err_o =
-         {( sfifo_keyvrc_wvld && !sfifo_keyvrc_wrdy),
-          ( sfifo_keyvrc_rrdy && !sfifo_keyvrc_rvld),
-          (!sfifo_keyvrc_wrdy && !sfifo_keyvrc_rvld)};
-
   // Unused signals
   logic [SeedLen-1:0] unused_upd_rsp_pdata;
   assign unused_upd_rsp_pdata = update_rsp_data_i.pdata;

hw/ip/csrng/rtl/csrng_main_sm.sv

@@ -95,7 +95,14 @@ module csrng_main_sm import csrng_pkg::*; (
         end
         MainSmCmdVld: begin
           cmd_vld_o = 1'b1;
-          if (cmd_rdy_i) state_d = MainSmClrAData;
+          if (cmd_rdy_i) begin
+            if (cmd_complete_i) begin
+              clr_adata_packer_o = 1'b1;
+              state_d = MainSmIdle;
+            end else begin
+              state_d = MainSmClrAData;
+            end
+          end
         end
         MainSmClrAData: begin
           clr_adata_packer_o = 1'b1;