[hw,rstmgr,dv] More templating for preferred IO clock

Signed-off-by: Robert Schilling <[email protected]>

Author: Razer6

hw/ip_templates/rstmgr/dv/env/rstmgr_if.sv renamed to hw/ip_templates/rstmgr/dv/env/rstmgr_if.sv.tpl

@@ -3,6 +3,18 @@
 // SPDX-License-Identifier: Apache-2.0
 //
 // clkmgr interface.
+<% 
+all_clks = set(clk_freqs.keys())
+
+if "io_div4" in all_clks:
+    preferred_domain = "io_div4"
+elif "io" in all_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_rst_n = f"rst_lc_{preferred_domain}_n"
+%>\
 
 interface rstmgr_if (
   input logic clk_aon,
@@ -65,5 +77,5 @@ interface rstmgr_if (
   always_comb cpu_info_en = `PATH_TO_DUT.reg2hw.cpu_info_ctrl.en.q;
 
   bit rst_ni_inactive;
-  always_comb rst_ni_inactive = resets_o.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel];
+  always_comb rst_ni_inactive = resets_o.${preferred_rst_n}[rstmgr_pkg::Domain0Sel];
 endinterface

hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_base_vseq.sv.tpl

@@ -4,9 +4,9 @@
 <% 
 sorted_clks = sorted(list(clk_freqs.keys()))
 
-def preferred_clk():
-    if "io_div4" in sorted_clks:
-        return "io_div4"
+def preferred_clk(preferred):
+    if preferred in sorted_clks:
+        return preferred
     elif "io" in sorted_clks:
         return "io"
     else:
@@ -280,7 +280,7 @@ class rstmgr_base_vseq extends cip_base_vseq #(
   virtual protected task clear_alert_and_cpu_info();
     set_alert_and_cpu_info_for_capture('0, '0);
     send_sw_reset();
-    cfg.${preferred_clk()}_clk_rst_vif.wait_clks(20);  // # of lc reset cycles measured from waveform
+    cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(20);  // # of lc reset cycles measured from waveform
     check_alert_and_cpu_info_after_reset(.alert_dump('0), .cpu_dump('0), .enable(0));
   endtask
 
@@ -332,7 +332,7 @@ class rstmgr_base_vseq extends cip_base_vseq #(
     csr_wr(.ptr(ral.sw_rst_ctrl_n[entry]), .value(sw_rst_ctrl_n[entry]));
     // And check that the reset outputs match the actual ctrl_n settings.
     // Allow for domain crossing delay.
-    cfg.io_div2_clk_rst_vif.wait_clks(3);
+    cfg.${preferred_clk("io_div2")}_clk_rst_vif.wait_clks(3);
     exp_ctrl_n = ~sw_rst_regwen | sw_rst_ctrl_n;
     `uvm_info(`gfn, $sformatf(
               "regwen=%b, ctrl_n=%b, expected=%b", sw_rst_regwen, sw_rst_ctrl_n, exp_ctrl_n),
@@ -368,7 +368,7 @@ class rstmgr_base_vseq extends cip_base_vseq #(
     set_reset_cause(reset_cause);
     // These lag the reset requests since they are set after the pwrmgr fast fsm has made some
     // state transitions.
-    cfg.${preferred_clk()}_clk_rst_vif.wait_clks(rst_to_req_cycles);
+    cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(rst_to_req_cycles);
     set_pwrmgr_rst_reqs(.rst_lc_req('1), .rst_sys_req('1));
     cfg.clk_rst_vif.stop_clk();
     if (reset_cause == pwrmgr_pkg::LowPwrEntry) begin
@@ -380,7 +380,7 @@ class rstmgr_base_vseq extends cip_base_vseq #(
     // And wait for the main reset to be done.
     `DV_WAIT(cfg.rstmgr_vif.rst_ni_inactive, "Time-out waiting for rst_ni becoming inactive");
     // And wait a few cycles for settling before allowing the sequences to start.
-    cfg.${preferred_clk()}_clk_rst_vif.wait_clks(8);
+    cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(8);
   endtask
 
   protected task reset_done();
@@ -391,10 +391,10 @@ class rstmgr_base_vseq extends cip_base_vseq #(
       control_all_clocks(.enable(1));
     end
     cfg.clk_rst_vif.start_clk();
-    cfg.${preferred_clk()}_clk_rst_vif.wait_clks(10);
+    cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(10);
     set_reset_cause(pwrmgr_pkg::ResetNone);
     set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('1));
-    cfg.${preferred_clk()}_clk_rst_vif.wait_clks(release_lc_to_release_sys_cycles);
+    cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(release_lc_to_release_sys_cycles);
     set_pwrmgr_rst_reqs(.rst_lc_req('0), .rst_sys_req('0));
     set_rstreqs(0);
     wait_till_active();
@@ -414,7 +414,7 @@ class rstmgr_base_vseq extends cip_base_vseq #(
               automatic int index = i;
               automatic bit [2:0] cycles;
               `DV_CHECK_STD_RANDOMIZE_FATAL(cycles)
-              cfg.${preferred_clk()}_clk_rst_vif.wait_clks(cycles);
+              cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(cycles);
               add_rstreqs(rstreqs & (1 << index));
             join_none
           end
@@ -438,11 +438,11 @@ class rstmgr_base_vseq extends cip_base_vseq #(
     `uvm_info(`gfn, "Sending scan reset", UVM_MEDIUM)
     fork
       begin
-        cfg.${preferred_clk()}_clk_rst_vif.wait_clks(scan_rst_cycles);
+        cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(scan_rst_cycles);
         update_scan_rst_n(1'b0);
       end
       begin
-        cfg.${preferred_clk()}_clk_rst_vif.wait_clks(scanmode_cycles);
+        cfg.${preferred_clk("io_div4")}_clk_rst_vif.wait_clks(scanmode_cycles);
         update_scanmode(prim_mubi_pkg::MuBi4True);
       end
     join
@@ -528,10 +528,10 @@ class rstmgr_base_vseq extends cip_base_vseq #(
 
   // setup basic rstmgr features
   virtual task rstmgr_init();
-    // Must set clk_rst_vif frequency to IO_DIV4_FREQ_MHZ since they are gated
+    // Must set clk_rst_vif frequency to ${preferred_clk("io_div4").upper()}_FREQ_MHZ since they are gated
     // versions of each other and have no clock domain crossings.
     // Notice they may still end up out of phase due to the way they get started.
-    cfg.clk_rst_vif.set_freq_mhz(IO_DIV4_FREQ_MHZ);
+    cfg.clk_rst_vif.set_freq_mhz(${preferred_clk("io_div4").upper()}_FREQ_MHZ);
 % for clk in sorted_clks:
     cfg.${clk}_clk_rst_vif.set_freq_mhz(${clk.upper()}_FREQ_MHZ);
 % endfor

hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv renamed to hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_cnsty_vseq.sv.tpl

@@ -10,6 +10,18 @@
 // 3 - sw reset
 // Create reset consistency errors in the current leaf, and check that a
 // fatal_cnsty_fault alert is generated.
+<% 
+all_clks = set(clk_freqs.keys())
+
+if "io_div4" in all_clks:
+    preferred_domain = "io_div4"
+elif "io" in all_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_clk_vif = f"{preferred_domain}_clk_rst_vif"
+%>\
 class rstmgr_leaf_rst_cnsty_vseq extends rstmgr_base_vseq;
   `uvm_object_utils(rstmgr_leaf_rst_cnsty_vseq)
 
@@ -68,7 +80,7 @@ class rstmgr_leaf_rst_cnsty_vseq extends rstmgr_base_vseq;
           check_alert_and_cpu_info_after_reset(alert_dump, cpu_dump, 1'b1);
 
           csr_wr(.ptr(ral.reset_info), .value('1));
-          cfg.io_div4_clk_rst_vif.wait_clks(10);
+          cfg.${preferred_clk_vif}.wait_clks(10);
 
           // Send HwReq.
           // Enable alert_info and cpu_info capture.

hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_leaf_rst_shadow_attack_vseq.sv.tpl

@@ -4,7 +4,20 @@
 // Description:
 // Test assert glitch to shadow leaf reset module and
 // check if nomal reset module got affected or vice versa
-<% has_sys_io_div4 = any(d.get('name') == 'sys_io_div4' for d in output_rsts) if output_rsts else False %>\
+<% 
+all_clks = set(clk_freqs.keys())
+has_sys_io = any("sys_io" in d.get('name') for d in output_rsts) if output_rsts else False
+
+if "io_div4" in all_clks:
+    preferred_domain = "io_div4"
+elif "io" in all_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_clk_rst_vif = f"{preferred_domain}_clk_rst_vif"
+preferred_rst_n = f"rst_sys_{preferred_domain}_n"
+%>\
 class rstmgr_leaf_rst_shadow_attack_vseq extends rstmgr_base_vseq;
   `uvm_object_utils(rstmgr_leaf_rst_shadow_attack_vseq)
 
@@ -23,9 +36,9 @@ class rstmgr_leaf_rst_shadow_attack_vseq extends rstmgr_base_vseq;
   endtask : body
 
   task leaf_rst_attack(string npath, string gpath);
-% if has_sys_io_div4:
+% if has_sys_io:
     // Wait for any bit in rst_sys_io_div4_n to become inactive.
-    wait(|cfg.rstmgr_vif.resets_o.rst_sys_io_div4_n);
+    wait(|cfg.rstmgr_vif.resets_o.${preferred_rst_n});
 % endif
     // Disable cascading reset assertions, since forcing related signals causes failures.
     cfg.rstmgr_cascading_sva_vif.disable_sva = 1'b1;
@@ -59,7 +72,7 @@ class rstmgr_leaf_rst_shadow_attack_vseq extends rstmgr_base_vseq;
 
     // Wait enough cycles to allow the uvm_hdl_force to take effect, since it is not instantaneous,
     // and for side-effects to propagate.
-    cfg.io_div4_clk_rst_vif.wait_clks(10);
+    cfg.${preferred_clk_rst_vif}.wait_clks(10);
 
     `uvm_info(`gfn, $sformatf("Checking rst and en for %s", path), UVM_MEDIUM)
     `DV_CHECK(uvm_hdl_read(epath, rst_en), $sformatf("Path %0s has problem", epath))

hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv renamed to hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_por_stretcher_vseq.sv.tpl

@@ -6,6 +6,18 @@
 // the test, and randomly glitches it for a few cycles at intervals less than the stretch cycle
 // count, which is at least 32 cycles, to make sure the internal and output resets won't be
 // released until the input is held steady for a sufficient number of cycles.
+<% 
+all_clks = set(clk_freqs.keys())
+
+if "io_div4" in all_clks:
+    preferred_domain = "io_div4"
+elif "io" in all_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_por_n = f"rst_por_{preferred_domain}_n"
+%>\
 class rstmgr_por_stretcher_vseq extends rstmgr_base_vseq;
   `uvm_object_utils(rstmgr_por_stretcher_vseq)
 
@@ -34,7 +46,7 @@ class rstmgr_por_stretcher_vseq extends rstmgr_base_vseq;
       cfg.aon_clk_rst_vif.wait_clks(glitch_separation_cycles);
       cfg.rstmgr_vif.por_n = 1'b0;
       cfg.aon_clk_rst_vif.wait_clks(glitch_duration_cycles);
-      `DV_CHECK_EQ(cfg.rstmgr_vif.resets_o.rst_por_io_div4_n[rstmgr_pkg::DomainAonSel], 1'b0)
+      `DV_CHECK_EQ(cfg.rstmgr_vif.resets_o.${preferred_por_n}[rstmgr_pkg::DomainAonSel], 1'b0)
     end
     por_reset_done(.complete_it(1));
     csr_rd_check(.ptr(ral.reset_info.por), .compare_value(1'b1),

hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv renamed to hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv.tpl

@@ -6,6 +6,18 @@
 // resets.
 //
 // Notice that for rstmgr both POR and scan reset have identical side-effects.
+<% 
+all_clks = set(clk_freqs.keys())
+
+if "io_div4" in all_clks:
+    preferred_domain = "io_div4"
+elif "io" in all_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_clk_rst_vif = f"{preferred_domain}_clk_rst_vif"
+%>\
 class rstmgr_reset_vseq extends rstmgr_base_vseq;
   `uvm_object_utils(rstmgr_reset_vseq)
 
@@ -156,22 +168,22 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
         if (which_resets[ResetPOR]) por_reset(.complete_it(0));
         if (which_resets[ResetScan]) send_scan_reset(.complete_it(0));
         if (which_resets[ResetLowPower]) begin
-          cfg.io_div4_clk_rst_vif.wait_clks(lowpower_rst_cycles);
+          cfg.${preferred_clk_rst_vif}.wait_clks(lowpower_rst_cycles);
           send_lowpower_reset(.complete_it(0));
         end
         if (which_resets[ResetSw]) begin
-          cfg.io_div4_clk_rst_vif.wait_clks(sw_rst_cycles);
+          cfg.${preferred_clk_rst_vif}.wait_clks(sw_rst_cycles);
           send_sw_reset(.complete_it(0));
         end
         if (which_resets[ResetHw]) begin
-          cfg.io_div4_clk_rst_vif.wait_clks(hw_rst_cycles);
+          cfg.${preferred_clk_rst_vif}.wait_clks(hw_rst_cycles);
           send_hw_reset(rstreqs, .complete_it(0));
         end
       join
       #(reset_us * 1us);
       reset_done();
 
-      cfg.io_div4_clk_rst_vif.wait_clks(8);
+      cfg.${preferred_clk_rst_vif}.wait_clks(8);
       wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
       check_reset_info(expected_reset_info_code);
       check_alert_info_after_reset(.alert_dump(expected_alert_dump),

hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv renamed to hw/ip_templates/rstmgr/dv/env/seq_lib/rstmgr_smoke_vseq.sv.tpl

@@ -4,6 +4,18 @@
 
 // Tests the different kinds of reset: POR, low power wakeup, hardware reset, debug_mode reset,
 // and software initiated peripheral resets.
+<% 
+all_clks = set(clk_freqs.keys())
+
+if "io_div4" in all_clks:
+    preferred_domain = "io_div4"
+elif "io" in all_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_clk_rst_vif = f"{preferred_domain}_clk_rst_vif"
+%>\
 class rstmgr_smoke_vseq extends rstmgr_base_vseq;
 
   `uvm_object_utils(rstmgr_smoke_vseq)
@@ -15,7 +27,7 @@ class rstmgr_smoke_vseq extends rstmgr_base_vseq;
   constraint sw_rst_some_reset_c {sw_rst_regwen & ~sw_rst_ctrl_n != '0;}
 
   local task wait_between_resets();
-    cfg.io_div4_clk_rst_vif.wait_clks(10);
+    cfg.${preferred_clk_rst_vif}.wait_clks(10);
   endtask
 
   task body();

hw/ip_templates/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv.tpl

@@ -2,17 +2,20 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-<% 
-sorted_clks = sorted(list(clk_freqs.keys())) 
+<%
+sorted_clks = sorted(list(clk_freqs.keys()))
 has_sys_io = any("sys_io" in d.get('name') for d in output_rsts) if output_rsts else False
 
-def preferred_domain():
-    if "io_div4" in sorted_clks:
-        return "io_div4"
-    elif "io" in sorted_clks:
-        return "io"
-    else:
-        assert 0, "No preferred clock available"
+if "io_div4" in sorted_clks:
+    preferred_domain = "io_div4"
+elif "io" in sorted_clks:
+    preferred_domain = "io"
+else:
+    assert 0, "No preferred clock available"
+
+preferred_por_n = f"rst_por_{preferred_domain}_n"
+preferred_rst_n = f"rst_sys_{preferred_domain}_n"
+preferred_clk_i = f"clk_{preferred_domain}_i"
 %>\
 // This has assertions that check the reset outputs of rstmgr cascade properly.
 // This means higher level resets always cause the lower level ones to assert.
@@ -137,10 +140,10 @@ interface rstmgr_cascading_sva_if (
 
   // The AON reset triggers the various POR reset for the different clock domains through
   // synchronizers.
-  // The current system doesn't have any consumers of domain 1 por_${preferred_domain()}, and thus only domain 0
-  // cascading is checked here.
+  // Only domain 0 cascading is checked here, because the current system doesn't have any consumers
+  // of ${preferred_por_n}.
   `CASCADED_ASSERTS(CascadeEffAonToRstPorIoDiv4, effective_aon_rst_n[0],
-                    resets_o.rst_por_${preferred_domain()}_n[0], SyncCycles, clk_${preferred_domain()}_i)
+                    resets_o.${preferred_por_n}[0], SyncCycles, ${preferred_clk_i})
 
   // The internal reset is triggered by one of synchronized por.
   logic [rstmgr_pkg::PowerDomains-1:0] por_rst_n;
@@ -164,9 +167,9 @@ interface rstmgr_cascading_sva_if (
 
 % if has_sys_io:
     // Controlled by rst_sys_src_n.
-    if (pd == rstmgr_pkg::DomainAonSel) begin : gen_sys_${preferred_domain()}_chk
-      `CASCADED_ASSERTS(CascadeSysToSysIoDiv4, rst_sys_src_n[pd], resets_o.rst_sys_${preferred_domain()}_n[pd],
-                        SysCycles, clk_${preferred_domain()}_i)
+    if (pd == rstmgr_pkg::DomainAonSel) begin : gen_sys_${preferred_domain}_chk
+      `CASCADED_ASSERTS(CascadeSysToSysIoDiv4, rst_sys_src_n[pd], resets_o.${preferred_rst_n}[pd],
+                        SysCycles, ${preferred_clk_i})
     end
 % endif
   end